Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22733

1

T1

62

T2

27

T5

3

auto[ADC_CTRL_FILTER_COND_OUT]

3755

1

T1

9

T3

13

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20365

1

T1

67

T3

12

T8

44

auto[1]

6123

1

T1

4

T2

27

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	221	1			T142	10		T147	1		T32	23
values[0]	61	1			T155	15		T237	30		T238	15
values[1]	821	1			T81	11		T27	18		T36	3
values[2]	655	1			T127	1		T165	20		T24	24
values[3]	662	1			T1	9		T81	1		T37	9
values[4]	643	1			T7	2		T8	13		T27	3
values[5]	3149	1			T2	27		T4	24		T5	3
values[6]	801	1			T1	4		T8	1		T37	5
values[7]	669	1			T3	12		T6	1		T7	1
values[8]	747	1			T9	6		T12	5		T168	1
values[9]	926	1			T3	1		T30	3		T125	24
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	752	1			T27	18		T36	3		T127	1
values[1]	679	1			T165	20		T137	1		T24	24
values[2]	729	1			T1	9		T8	13		T81	1
values[3]	2981	1			T2	27		T5	3		T7	2
values[4]	889	1			T4	24		T38	30		T165	15
values[5]	654	1			T1	4		T6	1		T7	1
values[6]	667	1			T3	12		T9	18		T29	12
values[7]	737	1			T12	5		T125	17		T225	9
values[8]	937	1			T3	1		T30	3		T125	13
values[9]	102	1			T125	11		T142	10		T147	1
minimum	17361	1			T1	58		T8	31		T9	95

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T36	3		T128	24		T129	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T27	8		T127	1		T130	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T226	12		T145	1		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T165	10		T137	1		T24	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	1		T12	1		T37	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	4		T81	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T2	3		T5	3		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	2		T81	1		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T38	11		T142	11		T251	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	2		T165	7		T154	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	4		T7	1		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	1		T37	5		T228	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	9		T29	12		T35	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	1		T9	3		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	3		T125	17		T225	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T23	1		T165	5		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T138	1		T141	12		T130	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T3	1		T30	2		T125	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T125	11		T142	5		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T147	1		T230	9		T73	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17067	1			T1	53		T8	31		T9	94
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T81	1		T33	3		T280	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T129	15		T139	4		T175	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T27	10		T25	1		T155	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T145	7		T14	2		T242	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T165	10		T24	12		T257	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	12		T129	9		T231	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	5		T13	1		T33	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T2	24		T11	31		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T81	6		T131	15		T155	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T38	19		T142	8		T32	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T4	22		T165	8		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T144	8		T131	3		T132	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T228	14		T31	1		T146	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	3		T35	17		T141	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	11		T9	3		T12	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	2		T142	9		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T165	4		T139	4		T175	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T138	10		T141	12		T146	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T30	1		T141	6		T24	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T142	5		T235	11		T222	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	5		T9	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T81	10		T33	2		T280	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T142	5		T15	8		T235	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T147	1		T32	13		T229	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T237	14		T325	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T155	1		T238	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T36	3		T128	24		T129	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T81	1		T27	8		T130	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T226	12		T139	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T127	1		T165	10		T24	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	9		T129	5		T239	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	4		T81	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T8	1		T27	2		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	2		T154	13		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1705	1			T2	3		T5	3		T11	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	2		T81	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	4		T8	1		T38	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T37	5		T228	12		T31	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	1		T9	9		T29	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T6	1		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	3		T125	17		T142	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	3		T168	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T125	11		T225	9		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	1		T30	2		T125	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T142	5		T15	8		T235	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T32	10		T292	14		T196	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T237	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T155	14		T238	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T129	15		T175	13		T241	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T81	10		T27	10		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T139	4		T145	7		T14	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T165	10		T24	12		T25	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T129	9		T239	11		T242	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	5		T33	2		T232	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	12		T27	1		T154	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T154	12		T131	15		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T2	24		T11	31		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T4	22		T81	6		T165	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T38	19		T142	8		T131	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T228	14		T31	1		T144	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	3		T35	17		T141	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	11		T12	8		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	2		T142	9		T231	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	3		T139	4		T147	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T138	10		T141	12		T146	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T30	1		T165	4		T141	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T36	1		T128	1		T129	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T27	11		T127	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T226	1		T145	8		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T165	11		T137	1		T24	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T8	13		T12	1		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	8		T81	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T2	27		T5	3		T11	34
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	2		T81	7		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T38	20		T142	9		T251	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T4	24		T165	9		T154	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	2		T7	1		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	1		T37	1		T228	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	9		T29	1		T35	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	12		T9	4		T12	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	4		T125	1		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T23	1		T165	5		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T138	11		T141	13		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T3	1		T30	2		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T125	1		T142	6		T235	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T147	1		T230	1		T73	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17171	1			T1	58		T8	31		T9	95
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T81	11		T33	3		T280	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T36	2		T128	23		T129	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T27	7		T130	13		T176	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T226	11		T14	2		T241	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T165	9		T24	11		T244	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T37	8		T129	4		T231	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	1		T13	1		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T27	1		T126	25		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T131	15		T155	11		T246	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	10		T142	10		T32	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T165	6		T154	12		T175	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T1	2		T131	3		T132	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T37	4		T228	11		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	3		T29	11		T35	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	2		T12	2		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T125	16		T225	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T165	4		T184	8		T159	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T141	11		T130	2		T26	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	1		T125	12		T141	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T125	10		T142	4		T222	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T230	8		T73	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T264	19		T326	13		T327	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T33	2		T280	2		T298	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T142	6		T15	14		T235	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T147	1		T32	12		T229	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T237	17		T325	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T155	15		T238	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T36	1		T128	1		T129	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T81	11		T27	11		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T226	1		T139	5		T145	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T127	1		T165	11		T24	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T37	1		T129	10		T239	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	8		T81	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	13		T27	2		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	2		T154	13		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T2	27		T5	3		T11	34
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T4	24		T81	7		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	2		T8	1		T38	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T37	1		T228	15		T31	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	1		T9	9		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	12		T6	1		T12	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	4		T125	1		T142	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	4		T168	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T125	1		T225	1		T138	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T3	1		T30	2		T125	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T142	4		T15	2		T328	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T32	11		T292	15		T73	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T237	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T238	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T36	2		T128	23		T129	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T27	7		T130	13		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T226	11		T14	2		T177	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T165	9		T24	11		T244	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T37	8		T129	4		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T1	1		T33	3		T34	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T27	1		T154	11		T231	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T154	12		T131	15		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T126	25		T129	10		T152	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T165	6		T155	11		T292	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	2		T38	10		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T37	4		T228	11		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T9	3		T29	11		T35	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	2		T245	16		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	1		T125	16		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	2		T184	8		T159	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T125	10		T225	8		T141	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T30	1		T125	12		T165	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11