Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22974

1

T1

67

T2

27

T4

24

auto[ADC_CTRL_FILTER_COND_OUT]

3514

1

T1

4

T3

13

T7

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20092

1

T1

58

T3

1

T7

3

auto[1]

6396

1

T1

13

T2

27

T3

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	227	1			T165	15		T144	10		T146	11
values[0]	92	1			T155	28		T88	14		T319	11
values[1]	781	1			T3	12		T7	1		T27	18
values[2]	659	1			T3	1		T8	13		T9	6
values[3]	569	1			T4	14		T6	1		T27	3
values[4]	818	1			T1	9		T81	18		T12	15
values[5]	640	1			T1	4		T81	1		T165	20
values[6]	716	1			T4	10		T29	12		T35	32
values[7]	840	1			T7	1		T8	1		T37	9
values[8]	662	1			T12	5		T125	13		T23	1
values[9]	3351	1			T2	27		T5	3		T7	1
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	695	1			T3	12		T7	1		T27	18
values[1]	724	1			T3	1		T6	1		T8	13
values[2]	601	1			T4	14		T81	7		T12	15
values[3]	781	1			T1	13		T81	11		T30	3
values[4]	545	1			T81	1		T141	13		T129	21
values[5]	830	1			T4	10		T29	12		T35	32
values[6]	3191	1			T2	27		T5	3		T7	1
values[7]	664	1			T9	12		T12	5		T228	26
values[8]	855	1			T7	1		T30	1		T165	15
values[9]	191	1			T38	30		T177	9		T162	4
minimum	17411	1			T1	58		T8	31		T9	95

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T27	8		T127	1		T226	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	1		T7	1		T141	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T9	3		T27	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	1		T8	1		T37	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	1		T81	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	7		T36	3		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	4		T125	17		T165	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	4		T81	1		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T131	16		T241	17		T16	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T81	1		T141	7		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	1		T168	1		T128	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T29	12		T35	15		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1759	1			T2	3		T5	3		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T154	12		T142	11		T231	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	9		T228	12		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	3		T142	13		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T30	1		T130	14		T142	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T7	1		T165	7		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T38	11		T162	1		T318	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T177	9		T96	1		T98	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T1	53		T8	31		T9	94
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T12	1		T33	3		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T27	10		T131	3		T32	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	11		T141	12		T25	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	3		T27	1		T100	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	12		T144	8		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	13		T81	6		T165	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	8		T144	10		T175	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	5		T165	10		T129	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T81	10		T30	1		T155	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T131	15		T16	2		T329	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T141	6		T129	10		T171	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	9		T138	10		T24	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T35	17		T147	8		T212	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T2	24		T11	31		T233	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T154	10		T142	8		T231	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	3		T228	14		T129	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	2		T142	9		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T142	5		T31	1		T146	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T165	8		T144	9		T257	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T38	19		T162	3		T318	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T96	1		T272	14		T330	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	5		T9	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T15	1		T275	6		T319	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T146	1		T331	1		T173	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T165	7		T144	1		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T155	12		T88	14		T322	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T319	1		T235	1		T320	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T27	8		T127	1		T154	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	1		T7	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	3		T143	1		T226	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	1		T8	1		T37	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	1		T6	1		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T36	3		T139	1		T175	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T1	4		T81	1		T125	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T81	1		T12	7		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T165	10		T251	1		T131	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	4		T81	1		T141	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	1		T168	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T29	12		T35	15		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T7	1		T8	1		T37	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T154	12		T142	11		T231	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T125	13		T23	1		T129	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	3		T142	13		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1746	1			T2	3		T5	3		T9	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T7	1		T257	17		T170	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T146	10		T331	3		T173	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T165	8		T144	9		T158	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T155	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T319	10		T235	11		T320	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T27	10		T154	12		T234	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	11		T141	12		T25	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	3		T292	14		T100	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	12		T144	8		T33	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T4	13		T27	1		T165	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T175	13		T100	2		T323	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	5		T81	6		T129	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T81	10		T12	8		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T165	10		T131	15		T282	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T141	6		T129	10		T26	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T4	9		T138	10		T24	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T35	17		T14	2		T172	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T141	12		T175	8		T282	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T154	10		T142	8		T231	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T129	9		T139	4		T33	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	2		T142	9		T139	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T2	24		T9	3		T11	31
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T257	16		T170	5		T32	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T27	11		T127	1		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	12		T7	1		T141	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	1		T9	4		T27	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	1		T8	13		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	14		T81	7		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	13		T36	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	8		T125	1		T165	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	2		T81	11		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T131	16		T241	1		T16	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T81	1		T141	7		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T4	10		T168	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T29	1		T35	18		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T2	27		T5	3		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T154	11		T142	9		T231	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T9	9		T228	15		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	4		T142	10		T139	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T30	1		T130	1		T142	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T7	1		T165	9		T144	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T38	20		T162	4		T318	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T177	1		T96	2		T98	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17226	1			T1	58		T8	31		T9	95
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T12	1		T33	2		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T27	7		T226	11		T131	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T141	11		T174	20		T280	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T9	2		T27	1		T100	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T37	4		T33	2		T246	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T165	4		T24	11		T186	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T12	2		T36	2		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T125	16		T165	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	2		T30	1		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T131	15		T241	16		T16	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T141	6		T129	10		T245	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T128	23		T24	4		T146	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T29	11		T35	14		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T37	8		T125	12		T126	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T154	11		T142	10		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	3		T228	11		T129	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	1		T142	12		T268	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T130	13		T142	4		T31	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T165	6		T257	16		T170	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T38	10		T314	1		T313	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T177	8		T98	8		T259	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T154	12		T234	7		T155	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T33	1		T15	1		T275	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T146	11		T331	4		T173	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T165	9		T144	10		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T155	17		T88	1		T322	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T319	11		T235	12		T320	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T27	11		T127	1		T154	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	12		T7	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	4		T143	1		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	1		T8	13		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	14		T6	1		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T36	1		T139	1		T175	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	8		T81	7		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T81	11		T12	13		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T165	11		T251	1		T131	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	2		T81	1		T141	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T4	10		T168	1		T138	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	1		T35	18		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	1		T8	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T154	11		T142	9		T231	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T125	1		T23	1		T129	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	4		T142	10		T139	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T2	27		T5	3		T9	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T7	1		T257	17		T170	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T163	12		T314	1		T222	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T165	6		T16	1		T177	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T155	11		T88	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T27	7		T154	12		T234	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T141	11		T174	20		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T226	11		T292	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T37	4		T33	2		T246	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T27	1		T165	4		T24	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T36	2		T175	4		T100	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T125	16		T129	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	2		T30	1		T225	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T165	9		T131	15		T241	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	2		T141	6		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T24	4		T146	10		T132	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T29	11		T35	14		T125	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T37	8		T128	23		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T154	11		T142	10		T231	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T125	12		T129	4		T130	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	1		T142	12		T268	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T9	3		T38	10		T228	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T257	16		T170	6		T32	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11