Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22887

1

T1

58

T2

27

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3601

1

T1

13

T3

12

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20316

1

T1

71

T3

13

T4

10

auto[1]

6172

1

T2

27

T4

14

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	204	1			T1	9		T7	1		T251	1
values[0]	50	1			T332	1		T249	22		T250	14
values[1]	696	1			T4	14		T37	5		T137	1
values[2]	778	1			T6	1		T8	1		T81	11
values[3]	751	1			T8	13		T27	18		T35	32
values[4]	808	1			T1	4		T7	1		T81	7
values[5]	781	1			T3	1		T29	12		T12	5
values[6]	747	1			T7	1		T12	1		T154	22
values[7]	710	1			T9	12		T30	3		T36	3
values[8]	2944	1			T2	27		T5	3		T9	6
values[9]	886	1			T3	12		T4	10		T81	1
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	703	1			T8	1		T37	5		T127	1
values[1]	764	1			T6	1		T81	11		T168	1
values[2]	828	1			T8	13		T27	18		T35	32
values[3]	799	1			T1	4		T3	1		T7	1
values[4]	687	1			T7	1		T29	12		T12	5
values[5]	800	1			T12	1		T165	9		T154	22
values[6]	2978	1			T2	27		T5	3		T9	12
values[7]	644	1			T9	6		T228	26		T23	1
values[8]	740	1			T1	9		T4	10		T7	1
values[9]	191	1			T3	12		T245	12		T251	1
minimum	17354	1			T1	58		T4	14		T8	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	1		T24	5		T174	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T37	5		T127	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	1		T81	1		T142	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T168	1		T165	7		T226	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T38	11		T128	24		T154	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T8	1		T27	8		T35	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	1		T81	1		T141	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	4		T7	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	1		T29	12		T165	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	3		T225	9		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T154	12		T142	11		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	1		T165	5		T141	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1698	1			T2	3		T5	3		T9	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T142	5		T234	8		T131	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T228	12		T23	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T9	3		T138	1		T251	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	1		T168	1		T37	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	4		T4	1		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T245	12		T251	1		T32	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T3	1		T163	14		T319	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17043	1			T1	53		T8	31		T9	94
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T4	1		T141	11		T332	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T24	10		T174	14		T33	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T243	7		T148	10		T15	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T81	10		T142	9		T144	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T165	8		T132	18		T32	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T38	19		T154	12		T129	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T8	12		T27	10		T35	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T81	6		T141	6		T129	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T27	1		T24	12		T231	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T165	10		T129	10		T172	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	2		T158	9		T242	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T154	10		T142	8		T139	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T165	4		T141	12		T231	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T2	24		T9	3		T11	31
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T142	5		T234	6		T131	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T228	14		T31	1		T132	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	3		T138	10		T145	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T170	5		T186	13		T242	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	5		T4	9		T139	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T32	14		T255	12		T256	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T3	11		T319	10		T333	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	5		T9	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T4	13		T141	12		T264	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T7	1		T251	1		T147	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T1	4		T241	17		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T250	1		T193	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T332	1		T249	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T24	5		T174	21		T33	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	1		T37	5		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	1		T8	1		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T168	1		T127	1		T165	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T38	11		T154	13		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T8	1		T27	8		T35	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T81	1		T128	24		T129	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	4		T7	1		T27	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	1		T29	12		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	3		T125	17		T225	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	1		T154	12		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	1		T141	12		T146	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	9		T30	2		T36	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T165	5		T142	5		T234	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T2	3		T5	3		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T9	3		T138	1		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T168	1		T37	9		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	1		T4	1		T81	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T170	5		T162	3		T255	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T1	5		T319	10		T321	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T250	13		T193	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T249	21		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T24	10		T174	14		T33	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	13		T141	12		T243	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T81	10		T142	9		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T165	8		T132	18		T32	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T38	19		T154	12		T129	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T8	12		T27	10		T35	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T81	6		T129	15		T155	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T27	1		T24	12		T231	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T165	10		T141	6		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	2		T158	9		T242	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T154	10		T129	10		T142	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T141	12		T146	12		T147	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	3		T30	1		T139	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T165	4		T142	5		T234	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T2	24		T11	31		T233	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	3		T138	10		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T31	1		T132	8		T32	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	11		T4	9		T139	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T8	1		T24	11		T174	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T37	1		T127	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	1		T81	11		T142	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T168	1		T165	9		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T38	20		T128	1		T154	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T8	13		T27	11		T35	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T3	1		T81	7		T141	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	2		T7	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	1		T29	1		T165	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	4		T225	1		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T154	11		T142	9		T139	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	1		T165	5		T141	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T2	27		T5	3		T9	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T142	6		T234	7		T131	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T228	15		T23	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	4		T138	11		T251	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	1		T168	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	8		T4	10		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T245	1		T251	1		T32	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T3	12		T163	1		T319	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17216	1			T1	58		T8	31		T9	95
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T4	14		T141	13		T332	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T24	4		T174	20		T33	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T37	4		T15	2		T288	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T142	12		T186	5		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T165	6		T226	11		T244	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T38	10		T128	23		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T27	7		T35	14		T12	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T141	6		T129	13		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	2		T27	1		T125	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T29	11		T165	9		T129	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	1		T225	8		T242	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T154	11		T142	10		T175	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T165	4		T141	11		T231	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T9	3		T30	1		T36	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T142	4		T234	7		T131	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T228	11		T31	1		T132	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T9	2		T146	10		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	8		T130	15		T170	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	1		T125	12		T131	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T245	11		T32	16		T255	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T163	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T334	21		T193	8		T335	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T141	10		T305	4		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T7	1		T251	1		T147	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T1	8		T241	1		T319	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T250	14		T193	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T332	1		T249	22		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	11		T174	15		T33	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	14		T37	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	1		T8	1		T81	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T168	1		T127	1		T165	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T38	20		T154	13		T129	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T8	13		T27	11		T35	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T81	7		T128	1		T129	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	2		T7	1		T27	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	1		T29	1		T165	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	4		T125	1		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	1		T154	11		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T141	13		T146	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	9		T30	2		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T165	5		T142	6		T234	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T2	27		T5	3		T11	34
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	4		T138	11		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T168	1		T37	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T3	12		T4	10		T81	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T170	6		T98	8		T255	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T1	1		T241	16		T336	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T193	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T24	4		T174	20		T33	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	4		T141	10		T195	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T142	12		T186	5		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T165	6		T226	11		T244	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T38	10		T154	12		T129	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T27	7		T35	14		T12	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T128	23		T129	13		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	2		T27	1		T125	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T29	11		T165	9		T141	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	1		T125	16		T225	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T154	11		T129	10		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T141	11		T146	12		T257	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	3		T30	1		T36	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T165	4		T142	4		T234	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T228	11		T126	25		T152	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T9	2		T13	1		T292	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T37	8		T130	15		T31	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T125	12		T131	15		T146	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11