Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22835

1

T1

58

T2

27

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3653

1

T1

13

T3

12

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20175

1

T1

67

T3

1

T7

2

auto[1]

6313

1

T1

4

T2

27

T3

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	432	1			T29	12		T37	5		T174	35
values[0]	25	1			T81	1		T142	19		T169	1
values[1]	664	1			T9	6		T27	18		T35	32
values[2]	2870	1			T2	27		T3	12		T5	3
values[3]	778	1			T81	11		T127	1		T165	15
values[4]	567	1			T4	14		T6	1		T27	3
values[5]	813	1			T8	13		T12	15		T38	30
values[6]	732	1			T4	10		T37	9		T141	60
values[7]	683	1			T1	4		T12	5		T30	1
values[8]	723	1			T3	1		T7	2		T9	12
values[9]	1068	1			T1	9		T7	1		T8	1
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	533	1			T9	6		T27	18		T12	1
values[1]	2936	1			T2	27		T3	12		T5	3
values[2]	758	1			T6	1		T127	1		T165	15
values[3]	665	1			T4	14		T27	3		T125	13
values[4]	694	1			T8	13		T12	15		T38	30
values[5]	753	1			T4	10		T37	9		T141	37
values[6]	631	1			T1	4		T12	5		T30	1
values[7]	770	1			T3	1		T7	2		T8	1
values[8]	1197	1			T1	9		T7	1		T29	12
values[9]	132	1			T174	35		T243	8		T287	6
minimum	17419	1			T1	58		T8	31		T9	95

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T27	8		T12	1		T31	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	3		T125	11		T165	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T2	3		T5	3		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T3	1		T137	1		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	1		T143	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T127	1		T165	7		T129	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T125	13		T143	1		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	1		T27	2		T154	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T231	3		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	7		T38	11		T228	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T37	9		T141	7		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T4	1		T141	12		T245	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	3		T30	1		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	4		T139	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	1		T7	2		T8	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T129	5		T142	5		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T7	1		T29	12		T225	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T1	4		T168	1		T37	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T243	1		T287	1		T285	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T174	21		T337	18		T338	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17095	1			T1	53		T8	31		T9	94
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T154	12		T131	4		T169	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T27	10		T31	1		T32	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	3		T165	4		T24	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T2	24		T11	31		T81	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	11		T25	1		T268	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T186	18		T282	6		T281	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T165	8		T129	10		T234	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T283	10		T242	11		T247	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	13		T27	1		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	12		T231	5		T175	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	8		T38	19		T228	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T141	6		T24	12		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	9		T141	12		T184	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	2		T144	10		T146	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T139	4		T144	9		T146	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	3		T165	10		T170	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T129	9		T142	5		T132	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T131	15		T171	8		T280	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T1	5		T129	15		T231	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T243	7		T287	5		T285	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T174	14		T337	4		T338	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	5		T9	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T154	10		T131	3		T339	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T29	12		T280	6		T17	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T37	5		T174	21		T304	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T81	1		T142	11		T308	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T169	1		T307	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T27	8		T35	15		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	3		T125	11		T165	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1656	1			T2	3		T5	3		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T3	1		T137	1		T24	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T81	1		T147	1		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T127	1		T165	7		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	1		T143	2		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	1		T27	2		T154	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	1		T125	13		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	7		T38	11		T228	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T37	9		T141	7		T24	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	1		T141	23		T245	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	3		T30	1		T36	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	4		T226	12		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	1		T7	2		T9	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T142	5		T146	11		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T7	1		T8	1		T225	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T1	4		T168	1		T129	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T280	3		T17	3		T287	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T174	14		T304	4		T340	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T142	8		T308	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T307	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T27	10		T35	17		T138	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T9	3		T165	4		T154	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T2	24		T11	31		T81	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	11		T24	10		T268	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T81	10		T147	8		T186	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T165	8		T129	10		T234	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T282	6		T283	10		T247	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	13		T27	1		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	12		T231	5		T175	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	8		T38	19		T228	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T141	6		T24	12		T144	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	9		T141	24		T184	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	2		T146	10		T257	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T139	4		T144	9		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	3		T165	10		T144	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T142	5		T146	9		T132	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T131	15		T170	5		T171	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	5		T129	24		T231	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T27	11		T12	1		T31	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	4		T125	1		T165	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T2	27		T5	3		T11	34
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	12		T137	1		T25	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T143	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T127	1		T165	9		T129	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T125	1		T143	1		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	14		T27	2		T154	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	13		T231	6		T175	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	13		T38	20		T228	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T37	1		T141	7		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	10		T141	13		T245	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	4		T30	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	2		T139	5		T144	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	1		T7	2		T8	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T129	10		T142	6		T132	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T7	1		T29	1		T225	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	401	1			T1	8		T168	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T243	8		T287	6		T285	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T174	15		T337	5		T338	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17235	1			T1	58		T8	31		T9	95
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T154	11		T131	4		T169	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T27	7		T31	1		T244	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	2		T125	10		T165	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T30	1		T126	25		T152	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T268	10		T309	6		T281	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T26	12		T186	15		T281	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T165	6		T129	10		T234	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T125	12		T241	16		T283	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T27	1		T154	12		T146	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T231	2		T88	2		T341	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	2		T38	10		T228	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	8		T141	6		T24	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T141	11		T245	16		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	1		T36	2		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T1	2		T146	10		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	3		T125	16		T165	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T129	4		T142	4		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T29	11		T225	8		T130	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T1	1		T37	4		T129	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T285	6		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T174	20		T337	17		T342	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T35	14		T128	23		T142	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T154	11		T131	3		T339	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T29	1		T280	7		T17	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T37	1		T174	15		T304	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T81	1		T142	9		T308	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T169	1		T307	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T27	11		T35	18		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	4		T125	1		T165	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T2	27		T5	3		T11	34
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	12		T137	1		T24	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T81	11		T147	9		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T127	1		T165	9		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T143	2		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	14		T27	2		T154	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	13		T125	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	13		T38	20		T228	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T37	1		T141	7		T24	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	10		T141	26		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	4		T30	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	2		T226	1		T139	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	1		T7	2		T9	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T142	6		T146	10		T132	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T7	1		T8	1		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T1	8		T168	1		T129	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T29	11		T280	2		T17	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T37	4		T174	20		T304	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T142	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T27	7		T35	14		T128	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	2		T125	10		T165	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T30	1		T126	25		T152	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T24	4		T268	10		T309	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T26	12		T186	15		T281	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T165	6		T129	10		T234	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T283	12		T247	10		T298	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T27	1		T154	12		T146	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T125	12		T231	2		T241	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	2		T38	10		T228	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T37	8		T141	6		T24	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T141	21		T245	16		T184	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	1		T36	2		T130	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	2		T226	11		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	3		T125	16		T165	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T142	4		T146	10		T155	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T225	8		T130	2		T131	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	1		T129	17		T231	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11