Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20372

1

T1

62

T3

12

T7

3

auto[ADC_CTRL_FILTER_COND_OUT]

6116

1

T1

9

T2

27

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20329

1

T1

58

T3

1

T4

24

auto[1]

6159

1

T1

13

T2

27

T3

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	329	1			T138	11		T141	13		T144	10
values[0]	32	1			T33	3		T96	2		T291	1
values[1]	848	1			T1	4		T6	1		T7	1
values[2]	731	1			T81	8		T125	17		T154	22
values[3]	723	1			T168	1		T30	3		T127	1
values[4]	899	1			T3	1		T4	10		T27	18
values[5]	650	1			T125	13		T23	1		T128	24
values[6]	824	1			T3	12		T81	11		T168	1
values[7]	604	1			T7	1		T29	12		T12	16
values[8]	587	1			T4	14		T8	13		T12	5
values[9]	3128	1			T1	9		T2	27		T5	3
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	958	1			T1	4		T6	1		T81	7
values[1]	2921	1			T2	27		T5	3		T11	34
values[2]	816	1			T27	18		T168	1		T30	3
values[3]	845	1			T3	1		T4	10		T35	32
values[4]	650	1			T168	1		T23	1		T128	24
values[5]	812	1			T3	12		T81	11		T29	12
values[6]	707	1			T4	14		T7	1		T12	16
values[7]	509	1			T7	1		T8	13		T9	12
values[8]	865	1			T1	9		T8	1		T125	11
values[9]	120	1			T27	3		T138	11		T15	16
minimum	17285	1			T1	58		T7	1		T8	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T1	4		T81	1		T130	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T6	1		T125	17		T154	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T81	1		T127	1		T146	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1680	1			T2	3		T5	3		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T27	8		T168	1		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T165	10		T142	5		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T132	5		T155	1		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	1		T4	1		T35	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T23	1		T139	1		T174	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T168	1		T128	24		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	1		T81	1		T29	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T30	1		T141	12		T129	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	1		T12	8		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	1		T129	11		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	1		T9	9		T37	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	1		T12	3		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T141	7		T143	1		T234	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T1	4		T8	1		T125	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T27	2		T138	1		T179	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T15	8		T87	1		T306	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17038	1			T1	53		T7	1		T8	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T154	13		T33	3		T275	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T81	6		T231	5		T147	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T154	10		T141	12		T144	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T146	12		T157	14		T280	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	966	1			T2	24		T11	31		T233	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T27	10		T30	1		T131	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T165	10		T142	5		T144	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T132	3		T155	14		T292	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T4	9		T35	17		T38	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T139	4		T174	14		T32	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T129	9		T175	8		T184	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	11		T81	10		T165	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T141	12		T129	15		T142	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	8		T165	4		T32	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	13		T129	10		T24	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T9	3		T194	2		T75	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	12		T12	2		T142	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T141	6		T234	6		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	5		T145	7		T132	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T27	1		T138	10		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T15	8		T306	7		T343	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	5		T9	4		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T154	12		T275	6		T164	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T138	1		T141	7		T144	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T277	1		T344	1		T15	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T96	1		T182	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T33	3		T291	1		T215	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T1	4		T7	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	1		T154	13		T141	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T81	2		T231	3		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T125	17		T154	12		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T168	1		T30	2		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T165	10		T142	5		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T27	8		T131	4		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	1		T4	1		T35	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T23	1		T139	1		T132	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T125	13		T128	24		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	1		T81	1		T165	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T168	1		T30	1		T141	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	1		T29	12		T12	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T143	1		T24	12		T245	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T37	14		T246	6		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	1		T8	1		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	1		T9	9		T27	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1738	1			T1	4		T2	3		T5	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T138	10		T141	6		T144	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T15	9		T159	7		T306	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T96	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T215	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	3		T147	8		T170	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T154	12		T141	12		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T81	6		T231	5		T146	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T154	10		T155	16		T212	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T30	1		T14	2		T309	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T165	10		T142	5		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T27	10		T131	3		T155	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T4	9		T35	17		T38	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T139	4		T132	3		T174	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T129	9		T175	8		T268	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T3	11		T81	10		T165	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T141	12		T129	15		T142	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	8		T165	4		T32	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T24	12		T131	15		T32	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T232	14		T176	7		T75	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	13		T8	12		T12	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	3		T27	1		T234	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1005	1			T1	5		T2	24		T11	31
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T1	2		T81	7		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	1		T125	1		T154	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T81	1		T127	1		T146	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1332	1			T2	27		T5	3		T11	34
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T27	11		T168	1		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T165	11		T142	6		T144	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T132	4		T155	15		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T3	1		T4	10		T35	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T23	1		T139	5		T174	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T168	1		T128	1		T129	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	12		T81	11		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T30	1		T141	13		T129	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T12	14		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	14		T129	11		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T7	1		T9	9		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	13		T12	4		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T141	7		T143	1		T234	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	8		T8	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T27	2		T138	11		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T15	14		T87	1		T306	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17165	1			T1	58		T7	1		T8	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T154	13		T33	2		T275	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	2		T130	13		T231	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T125	16		T154	11		T141	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T146	12		T280	2		T242	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1314	1			T126	25		T152	23		T260	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T27	7		T30	1		T130	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T165	9		T142	4		T186	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T132	4		T26	12		T292	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T35	14		T38	10		T125	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T174	20		T32	16		T26	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T128	23		T129	4		T175	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T29	11		T165	6		T226	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T141	11		T129	13		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	2		T36	2		T165	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T129	10		T24	11		T245	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T9	3		T37	12		T177	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T142	10		T24	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T141	6		T234	7		T231	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T125	10		T225	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T27	1		T179	5		T296	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T15	2		T343	18		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T9	2		T264	19		T321	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T154	12		T33	1		T275	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T138	11		T141	7		T144	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T277	1		T344	1		T15	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T96	2		T182	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T33	2		T291	1		T215	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	2		T7	1		T9	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T6	1		T154	13		T141	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T81	8		T231	6		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T125	1		T154	11		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T168	1		T30	2		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T165	11		T142	6		T144	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T27	11		T131	4		T155	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T3	1		T4	10		T35	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T23	1		T139	5		T132	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T125	1		T128	1		T129	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T3	12		T81	11		T165	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T168	1		T30	1		T141	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	1		T29	1		T12	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T143	1		T24	13		T245	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T37	2		T246	1		T232	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	14		T8	13		T12	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	1		T9	9		T27	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1371	1			T1	8		T2	27		T5	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T141	6		T247	10		T87	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T15	3		T288	10		T159	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T33	1		T215	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	2		T9	2		T130	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T154	12		T141	10		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T231	2		T146	12		T34	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T125	16		T154	11		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T30	1		T130	2		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T165	9		T142	4		T186	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T27	7		T131	3		T26	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T35	14		T38	10		T228	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T132	4		T174	20		T32	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T125	12		T128	23		T129	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T165	6		T226	11		T257	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T141	11		T129	13		T142	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T29	11		T12	2		T36	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T24	11		T245	16		T131	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T37	12		T246	5		T176	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T129	10		T245	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	3		T27	1		T234	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1372	1			T1	1		T125	10		T225	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11