Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22669

1

T1

67

T2

27

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3819

1

T1

4

T3

1

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20275

1

T1

62

T3

1

T4

14

auto[1]

6213

1

T1

9

T2

27

T3

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	174	1			T37	9		T23	1		T165	20
values[0]	74	1			T12	1		T141	23		T162	13
values[1]	605	1			T1	4		T9	6		T27	18
values[2]	690	1			T8	1		T168	1		T30	3
values[3]	846	1			T81	1		T129	29		T226	12
values[4]	3195	1			T2	27		T4	14		T5	3
values[5]	877	1			T81	7		T12	5		T225	9
values[6]	642	1			T7	1		T9	12		T81	11
values[7]	830	1			T1	9		T12	15		T127	1
values[8]	647	1			T3	13		T4	10		T7	1
values[9]	775	1			T7	1		T8	13		T29	12
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	629	1			T8	1		T9	6		T27	18
values[1]	762	1			T30	3		T138	11		T129	29
values[2]	892	1			T6	1		T127	1		T128	24
values[3]	3183	1			T2	27		T4	14		T5	3
values[4]	766	1			T12	5		T37	5		T225	9
values[5]	686	1			T7	1		T9	12		T81	11
values[6]	730	1			T1	9		T127	1		T165	24
values[7]	686	1			T3	13		T4	10		T7	1
values[8]	654	1			T7	1		T8	13		T29	12
values[9]	130	1			T165	20		T245	17		T169	1
minimum	17370	1			T1	62		T8	31		T9	95

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	1		T168	1		T125	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	3		T27	8		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T155	1		T33	3		T277	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T30	2		T138	1		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	1		T226	12		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T127	1		T128	24		T141	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1733	1			T2	3		T5	3		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	1		T81	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T37	5		T225	9		T131	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T12	3		T140	1		T131	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	9		T81	1		T35	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	1		T12	7		T141	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T1	4		T127	1		T165	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T165	7		T129	11		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T7	1		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	1		T4	1		T125	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	1		T27	2		T37	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	1		T29	12		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T169	1		T158	1		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T165	10		T245	17		T33	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	53		T8	31		T9	94
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T1	4		T228	12		T141	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T175	14		T15	8		T242	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	3		T27	10		T24	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T155	14		T158	9		T282	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T30	1		T138	10		T129	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T144	9		T268	2		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T141	12		T144	10		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T2	24		T11	31		T233	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	13		T81	6		T139	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T131	3		T231	5		T147	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	2		T131	15		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	3		T81	10		T35	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	8		T141	6		T139	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T165	4		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T165	8		T129	10		T14	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	11		T129	9		T142	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	9		T154	22		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	12		T27	1		T38	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T144	8		T231	2		T26	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T158	9		T264	1		T269	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T165	10		T33	2		T271	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	5		T9	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T228	14		T141	12		T309	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T37	9		T169	1		T158	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T23	1		T165	10		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T345	5		T263	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T12	1		T141	11		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T125	17		T130	3		T257	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	4		T9	3		T27	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T8	1		T168	1		T175	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	2		T138	1		T24	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T81	1		T226	12		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T129	14		T144	1		T146	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1737	1			T2	3		T5	3		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T4	1		T127	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T225	9		T131	4		T231	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T81	1		T12	3		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	9		T81	1		T35	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	1		T140	1		T131	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T1	4		T127	1		T165	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	7		T165	7		T141	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T7	1		T129	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	1		T4	1		T125	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	1		T27	2		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	1		T29	12		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T158	9		T264	1		T193	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T165	10		T144	8		T231	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T345	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T141	12		T162	12		T272	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T257	16		T32	14		T242	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T9	3		T27	10		T228	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T175	14		T158	9		T15	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T30	1		T138	10		T24	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T144	9		T155	14		T268	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T129	15		T144	10		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T2	24		T11	31		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	13		T141	12		T174	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T131	3		T231	5		T147	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T81	6		T12	2		T139	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	3		T81	10		T35	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T131	15		T232	12		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	5		T165	4		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	8		T165	8		T141	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	11		T129	9		T145	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	9		T154	22		T132	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	12		T27	1		T38	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T26	9		T282	10		T159	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	1		T168	1		T125	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	4		T27	11		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T155	15		T33	2		T277	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T30	2		T138	11		T129	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	1		T226	1		T144	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T127	1		T128	1		T141	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T2	27		T5	3		T11	34
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	14		T81	7		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T37	1		T225	1		T131	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	4		T140	1		T131	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	9		T81	11		T35	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	1		T12	13		T141	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	8		T127	1		T165	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T165	9		T129	11		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	12		T7	1		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	1		T4	10		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	13		T27	2		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	1		T29	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T169	1		T158	10		T264	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T165	11		T245	1		T33	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17211	1			T1	58		T8	31		T9	95
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T1	2		T228	15		T141	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T125	16		T130	2		T175	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T9	2		T27	7		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T33	1		T258	9		T273	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	1		T129	13		T247	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T226	11		T230	8		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T128	23		T141	11		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T126	25		T152	23		T260	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T174	20		T177	8		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T37	4		T225	8		T131	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	1		T131	15		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	3		T35	14		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	2		T141	6		T26	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T1	1		T165	4		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T165	6		T129	10		T34	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T129	4		T142	10		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T125	10		T154	23		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T27	1		T37	8		T38	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T29	11		T231	10		T26	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T240	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T165	9		T245	16		T33	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T257	16		T32	16		T345	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T1	2		T228	11		T141	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T37	1		T169	1		T158	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T23	1		T165	11		T144	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T345	5		T263	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T12	1		T141	13		T162	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T125	1		T130	1		T257	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	2		T9	4		T27	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	1		T168	1		T175	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T30	2		T138	11		T24	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T81	1		T226	1		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T129	16		T144	11		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T2	27		T5	3		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T4	14		T127	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T225	1		T131	4		T231	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T81	7		T12	4		T139	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	9		T81	11		T35	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T7	1		T140	1		T131	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	8		T127	1		T165	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	13		T165	9		T141	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	12		T7	1		T129	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	1		T4	10		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T8	13		T27	2		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	1		T29	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T37	8		T193	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T165	9		T231	10		T33	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T345	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T141	10		T272	8		T267	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T125	16		T130	2		T257	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T1	2		T9	2		T27	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T175	4		T33	1		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T30	1		T24	11		T170	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T226	11		T16	3		T275	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T129	13		T146	10		T276	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T126	25		T152	23		T260	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T128	23		T141	11		T174	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T225	8		T131	3		T231	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	1		T13	1		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	3		T35	14		T36	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T131	15		T26	12		T246	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T1	1		T165	4		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	2		T165	6		T141	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T129	4		T130	13		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T125	10		T154	23		T132	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T27	1		T38	10		T142	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T29	11		T245	16		T26	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11