Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	1		T24	11		T174	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T4	14		T37	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	1		T81	11		T165	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T168	1		T132	19		T244	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T38	20		T128	1		T154	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T8	13		T27	11		T35	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T3	1		T81	7		T141	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T1	2		T7	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	1		T29	1		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	4		T165	11		T252	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T154	11		T142	9		T139	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	1		T165	5		T141	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T2	27		T5	3		T9	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T36	1		T142	6		T234	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T23	1		T143	1		T31	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	4		T125	1		T228	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	1		T130	2		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	8		T4	10		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T37	1		T251	1		T32	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T3	12		T163	1		T253	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T254	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T24	4		T174	20		T33	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T37	4		T141	10		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T165	6		T142	12		T186	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T244	13		T32	11		T33	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T38	10		T128	23		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T27	7		T35	14		T12	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T141	6		T129	13		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	2		T27	1		T125	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T29	11		T129	10		T258	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	1		T165	9		T242	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T154	11		T142	10		T171	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T165	4		T141	11		T231	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T9	3		T30	1		T126	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T36	2		T142	4		T234	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T31	1		T132	7		T32	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	2		T125	12		T228	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T130	15		T245	11		T186	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	1		T131	15		T170	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T37	8		T32	16		T255	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T163	13		T240	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T248	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T174	15		T250	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T249	22		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	11		T33	5		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	14		T37	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T8	1		T81	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T168	1		T127	1		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T38	20		T154	13		T129	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	13		T27	11		T12	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T81	7		T128	1		T129	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	1		T27	2		T35	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	1		T29	1		T141	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	2		T12	4		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	1		T154	11		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	1		T146	13		T147	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T9	9		T30	2		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T36	1		T165	5		T141	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T2	27		T5	3		T11	34
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	10		T9	4		T228	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T7	1		T37	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T1	8		T3	12		T81	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T248	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T174	20		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T24	4		T33	3		T34	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T37	4		T141	10		T259	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T165	6		T142	12		T186	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T226	11		T244	13		T32	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T38	10		T154	12		T129	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T27	7		T12	2		T246	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T128	23		T129	13		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T27	1		T35	14		T125	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T29	11		T141	6		T184	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	2		T12	1		T125	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T154	11		T129	10		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T146	12		T257	16		T177	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	3		T30	1		T132	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T36	2		T165	4		T141	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T126	25		T152	23		T260	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	2		T228	11		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T37	8		T130	15		T31	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	1		T125	12		T131	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11