Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22657

1

T1

67

T2

27

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3831

1

T1

4

T3

1

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20263

1

T1

62

T3

1

T4

14

auto[1]

6225

1

T1

9

T2

27

T3

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	36	1			T261	28		T262	8		-	-
values[0]	60	1			T12	1		T141	23		T263	1
values[1]	605	1			T1	4		T9	6		T27	18
values[2]	722	1			T8	1		T168	1		T30	3
values[3]	818	1			T81	1		T129	29		T226	12
values[4]	3259	1			T2	27		T4	14		T5	3
values[5]	765	1			T81	7		T12	5		T139	5
values[6]	705	1			T7	1		T9	12		T81	11
values[7]	794	1			T1	9		T12	15		T127	1
values[8]	626	1			T3	13		T4	10		T7	1
values[9]	965	1			T7	1		T8	13		T29	12
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	894	1			T1	4		T8	1		T9	6
values[1]	727	1			T30	3		T129	29		T144	10
values[2]	929	1			T127	1		T137	1		T128	24
values[3]	3094	1			T2	27		T4	14		T5	3
values[4]	875	1			T9	12		T12	5		T37	5
values[5]	647	1			T7	1		T81	11		T35	32
values[6]	693	1			T1	9		T127	1		T165	24
values[7]	651	1			T3	13		T4	10		T168	1
values[8]	766	1			T7	2		T8	13		T29	12
values[9]	73	1			T37	9		T33	6		T177	9
minimum	17139	1			T1	58		T8	31		T9	95

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	1		T168	1		T125	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	4		T9	3		T27	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T144	1		T155	1		T33	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T30	2		T129	14		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T245	12		T226	12		T230	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T127	1		T137	1		T128	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1718	1			T2	3		T5	3		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	1		T81	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	9		T37	5		T225	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T12	3		T131	16		T13	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T81	1		T35	15		T36	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	1		T12	7		T141	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T1	4		T127	1		T165	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T165	7		T154	12		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T168	1		T142	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	1		T4	1		T125	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	1		T8	1		T27	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	1		T29	12		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T37	9		T264	1		T265	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T33	4		T177	9		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T267	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T257	16		T175	14		T32	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T9	3		T27	10		T228	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T144	9		T155	14		T158	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T30	1		T129	15		T132	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T268	2		T16	2		T172	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T138	10		T141	12		T144	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T2	24		T11	31		T233	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	13		T81	6		T139	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	3		T131	3		T231	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	2		T131	15		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T81	10		T35	17		T142	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	8		T141	6		T139	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	5		T165	4		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T165	8		T154	10		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	11		T142	8		T145	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	9		T154	12		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	12		T27	1		T38	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T165	10		T144	8		T231	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T264	1		T269	2		T270	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T33	2		T266	9		T271	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T261	17		T262	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T263	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T12	1		T141	11		T272	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T125	17		T257	17		T32	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T1	4		T9	3		T27	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	1		T168	1		T130	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T30	2		T138	1		T24	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T81	1		T226	12		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T129	14		T144	1		T146	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1751	1			T2	3		T5	3		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T4	1		T127	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T131	4		T231	3		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T81	1		T12	3		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	9		T81	1		T35	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T139	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T1	4		T127	1		T165	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	7		T165	7		T141	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	1		T7	1		T130	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T4	1		T125	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T8	1		T27	2		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T7	1		T29	12		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T261	11		T262	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T141	12		T272	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T257	16		T32	14		T242	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	3		T27	10		T228	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T175	14		T158	9		T15	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T30	1		T138	10		T24	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T144	9		T155	14		T268	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T129	15		T144	10		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T2	24		T11	31		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	13		T141	12		T174	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T131	3		T231	5		T147	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T81	6		T12	2		T139	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	3		T81	10		T35	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T139	4		T131	15		T232	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	5		T165	4		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	8		T165	8		T141	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T3	11		T234	6		T145	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	9		T154	22		T129	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	12		T27	1		T38	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T165	10		T144	8		T231	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T8	1		T168	1		T125	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T1	2		T9	4		T27	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T144	10		T155	15		T33	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T30	2		T129	16		T132	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T245	1		T226	1		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T127	1		T137	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T2	27		T5	3		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	14		T81	7		T139	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T9	9		T37	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	4		T131	16		T13	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T81	11		T35	18		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	1		T12	13		T141	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	8		T127	1		T165	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T165	9		T154	11		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	12		T168	1		T142	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	1		T4	10		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T7	1		T8	13		T27	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	1		T29	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T37	1		T264	2		T265	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T33	3		T177	1		T266	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T267	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T125	16		T130	2		T257	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	2		T9	2		T27	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T33	1		T258	9		T273	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T30	1		T129	13		T247	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T245	11		T226	11		T230	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T128	23		T141	11		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T126	25		T152	23		T260	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T155	11		T174	20		T242	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	3		T37	4		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	1		T131	15		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T35	14		T36	2		T142	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	2		T141	6		T26	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	1		T165	4		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T165	6		T154	11		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T142	10		T175	12		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T125	10		T154	12		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T27	1		T38	10		T129	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T29	11		T165	9		T245	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T37	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T33	3		T177	8		T274	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T267	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T261	12		T262	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T263	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T12	1		T141	13		T272	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T125	1		T257	17		T32	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	2		T9	4		T27	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	1		T168	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T30	2		T138	11		T24	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T81	1		T226	1		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T129	16		T144	11		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T2	27		T5	3		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T4	14		T127	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	4		T231	6		T147	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T81	7		T12	4		T139	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T9	9		T81	11		T35	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	1		T139	5		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	8		T127	1		T165	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	13		T165	9		T141	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	12		T7	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	1		T4	10		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T8	13		T27	2		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T7	1		T29	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T261	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T141	10		T272	8		T267	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T125	16		T257	16		T32	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T1	2		T9	2		T27	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T130	2		T175	4		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T30	1		T24	11		T170	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T226	11		T16	3		T275	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T129	13		T146	10		T276	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T225	8		T126	25		T152	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T128	23		T141	11		T174	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T131	3		T231	2		T132	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	1		T13	1		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	3		T35	14		T36	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T131	15		T26	12		T246	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	1		T165	4		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	2		T165	6		T141	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T130	13		T234	7		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T125	10		T154	23		T129	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T27	1		T37	8		T38	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T29	11		T165	9		T245	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11