Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22587

1

T1

58

T2

27

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3901

1

T1

13

T3

12

T4

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19995

1

T1

64

T3

12

T4

24

auto[1]

6493

1

T1

7

T2

27

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	410	1			T1	3		T9	1		T39	1
values[0]	37	1			T266	18		T299	1		T300	12
values[1]	604	1			T1	9		T81	7		T37	9
values[2]	3078	1			T2	27		T5	3		T11	34
values[3]	670	1			T6	1		T8	13		T29	12
values[4]	628	1			T3	12		T8	1		T37	5
values[5]	738	1			T4	24		T9	12		T27	18
values[6]	927	1			T168	1		T129	21		T142	10
values[7]	686	1			T1	4		T81	12		T12	15
values[8]	686	1			T9	6		T125	11		T127	1
values[9]	1278	1			T3	1		T7	3		T12	1
minimum	16746	1			T1	55		T8	31		T9	94

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	813	1			T81	7		T37	9		T125	13
values[1]	3076	1			T1	9		T2	27		T5	3
values[2]	536	1			T3	12		T6	1		T8	13
values[3]	796	1			T4	10		T8	1		T37	5
values[4]	881	1			T4	14		T9	12		T27	18
values[5]	675	1			T168	1		T142	10		T143	2
values[6]	639	1			T1	4		T81	12		T12	15
values[7]	818	1			T7	2		T9	6		T125	11
values[8]	901	1			T7	1		T27	3		T38	30
values[9]	209	1			T3	1		T12	1		T33	6
minimum	17144	1			T1	58		T8	31		T9	95

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T81	1		T125	13		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T37	9		T137	1		T129	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T2	3		T5	3		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	4		T225	9		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T8	1		T23	1		T24	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T6	1		T29	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T154	12		T142	11		T277	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	1		T8	1		T37	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T4	1		T30	1		T129	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	9		T27	8		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T168	1		T142	5		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T143	1		T139	1		T186	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T81	2		T12	7		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	4		T127	1		T154	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	2		T9	3		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T125	11		T228	12		T165	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T27	2		T38	11		T125	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T7	1		T245	17		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T3	1		T16	1		T281	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T12	1		T33	4		T232	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17003	1			T1	53		T8	31		T9	94
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T81	6		T131	15		T147	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T129	15		T131	3		T132	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T2	24		T11	31		T35	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	5		T144	8		T175	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T8	12		T24	12		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	11		T24	10		T157	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T154	10		T142	8		T282	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T4	9		T141	12		T132	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	13		T129	9		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	3		T27	10		T12	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T142	5		T145	7		T146	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T139	4		T186	13		T196	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T81	10		T12	8		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T154	12		T144	9		T146	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	3		T138	10		T142	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T228	14		T165	14		T141	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T27	1		T38	19		T234	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T139	4		T231	2		T132	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T281	11		T301	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T33	2		T232	14		T96	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T1	3		T9	1		T39	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T302	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T266	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T299	1		T300	1		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T81	1		T125	13		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	4		T37	9		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1672	1			T2	3		T5	3		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T127	1		T137	1		T175	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T8	1		T23	1		T277	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	1		T29	12		T225	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T154	12		T24	12		T148	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	1		T8	1		T37	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	1		T30	1		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	1		T9	9		T27	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T168	1		T142	5		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T129	11		T139	1		T13	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T81	2		T12	7		T30	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	4		T154	13		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	3		T138	1		T142	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T125	11		T127	1		T228	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T3	1		T7	2		T38	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	445	1			T7	1		T12	1		T165	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T1	50		T8	31		T9	93
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T27	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T302	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T266	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T300	11		T303	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T81	6		T131	15		T147	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	5		T129	15		T131	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T2	24		T11	31		T35	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T175	13		T184	11		T292	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	12		T148	10		T158	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T141	12		T24	10		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T154	10		T24	12		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	11		T132	18		T157	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	13		T129	9		T142	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	9		T9	3		T27	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T142	5		T145	7		T146	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T129	10		T139	4		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T81	10		T12	8		T30	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T154	12		T146	10		T171	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T9	3		T138	10		T142	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T228	14		T165	10		T141	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T38	19		T234	6		T231	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T165	4		T31	1		T139	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T81	7		T125	1		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T37	1		T137	1		T129	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T2	27		T5	3		T11	34
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	8		T225	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	13		T23	1		T24	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	12		T6	1		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T154	11		T142	9		T277	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T4	10		T8	1		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T4	14		T30	1		T129	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	9		T27	11		T12	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T168	1		T142	6		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T143	1		T139	5		T186	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T81	12		T12	13		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	2		T127	1		T154	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	2		T9	4		T138	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T125	1		T228	15		T165	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T27	2		T38	20		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T7	1		T245	1		T139	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T3	1		T16	1		T281	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T12	1		T33	3		T232	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17134	1			T1	58		T8	31		T9	95
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T125	12		T131	15		T246	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T37	8		T129	13		T131	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T35	14		T126	25		T165	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	1		T225	8		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T24	11		T15	1		T195	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	11		T130	13		T24	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	11		T142	10		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T37	4		T141	11		T130	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T129	4		T33	2		T212	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	3		T27	7		T12	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T142	4		T146	12		T244	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T186	10		T98	13		T196	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	2		T30	1		T141	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T1	2		T154	12		T171	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T9	2		T142	12		T170	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T125	10		T228	11		T165	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T27	1		T38	10		T125	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T245	16		T231	10		T132	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T281	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T33	3		T273	1		T272	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T288	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T1	3		T9	1		T39	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T302	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T266	18		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T299	1		T300	12		T303	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T81	7		T125	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	8		T37	1		T129	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T2	27		T5	3		T11	34
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T127	1		T137	1		T175	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	13		T23	1		T277	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	1		T29	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T154	11		T24	13		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	12		T8	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T4	14		T30	1		T129	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	10		T9	9		T27	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T168	1		T142	6		T145	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T129	11		T139	5		T13	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T81	12		T12	13		T30	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	2		T154	13		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T9	4		T138	11		T142	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T125	1		T127	1		T228	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	1		T7	2		T38	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	432	1			T7	1		T12	1		T165	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16746	1			T1	55		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T27	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T302	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T125	12		T131	15		T288	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T1	1		T37	8		T129	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T35	14		T126	25		T165	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T175	4		T184	8		T292	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T177	8		T195	8		T200	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T29	11		T225	8		T141	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T154	11		T24	11		T148	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T37	4		T130	2		T226	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T129	4		T142	10		T33	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	3		T27	7		T12	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T142	4		T146	12		T244	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T129	10		T13	1		T186	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	2		T30	1		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	2		T154	12		T171	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T9	2		T142	12		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T125	10		T228	11		T165	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T38	10		T125	16		T234	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T165	4		T31	1		T245	27

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11