Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22821

1

T1

58

T2

27

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3667

1

T1

13

T3

12

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20137

1

T1

67

T3

1

T7

2

auto[1]

6351

1

T1

4

T2

27

T3

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T304	7		T200	13		-	-
values[0]	74	1			T81	1		T142	19		T169	1
values[1]	639	1			T9	6		T27	18		T35	32
values[2]	2868	1			T2	27		T3	12		T5	3
values[3]	778	1			T4	14		T81	11		T165	15
values[4]	560	1			T6	1		T27	3		T154	25
values[5]	740	1			T8	13		T12	15		T38	30
values[6]	731	1			T4	10		T37	9		T141	60
values[7]	770	1			T1	4		T12	5		T30	1
values[8]	646	1			T3	1		T7	2		T9	12
values[9]	1529	1			T1	9		T7	1		T8	1
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	804	1			T9	6		T81	1		T27	18
values[1]	2942	1			T2	27		T3	12		T5	3
values[2]	802	1			T4	14		T6	1		T127	1
values[3]	612	1			T27	3		T125	13		T228	26
values[4]	735	1			T8	13		T12	15		T38	30
values[5]	680	1			T4	10		T37	9		T141	37
values[6]	715	1			T1	4		T12	5		T30	1
values[7]	783	1			T3	1		T7	3		T9	12
values[8]	1018	1			T1	9		T8	1		T29	12
values[9]	264	1			T174	35		T243	8		T75	26
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T81	1		T27	8		T35	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	3		T125	11		T165	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T2	3		T5	3		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	1		T137	1		T24	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	1		T143	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	1		T127	1		T165	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T125	13		T143	1		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T27	2		T228	12		T154	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	1		T231	3		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	7		T38	11		T141	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T37	9		T141	7		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	1		T141	12		T245	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	3		T30	1		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	4		T144	1		T146	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T3	1		T7	3		T9	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T129	5		T142	5		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T8	1		T29	12		T225	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T1	4		T168	1		T37	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T243	1		T287	1		T305	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T174	21		T75	13		T306	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T27	10		T35	17		T138	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	3		T165	4		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T2	24		T11	31		T81	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	11		T24	10		T25	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T186	18		T282	6		T281	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	13		T165	8		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T283	10		T242	11		T247	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T27	1		T228	14		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	12		T231	5		T175	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	8		T38	19		T141	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T141	6		T24	12		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	9		T141	12		T184	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	2		T144	10		T146	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T144	9		T146	9		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	3		T165	10		T131	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T129	9		T142	5		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T171	8		T280	3		T176	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	5		T129	15		T231	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T243	7		T287	5		T305	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T174	14		T75	13		T306	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T200	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T304	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T81	1		T142	11		T200	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T169	1		T298	12		T307	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T27	8		T35	15		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	3		T125	11		T165	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1694	1			T2	3		T5	3		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T3	1		T127	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T81	1		T147	1		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	1		T165	7		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	1		T143	2		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T27	2		T154	13		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	1		T125	13		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	7		T38	11		T228	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T37	9		T141	7		T24	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	1		T141	23		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	3		T30	1		T36	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	4		T226	12		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	1		T7	2		T9	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T142	5		T132	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T7	1		T8	1		T29	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	468	1			T1	4		T168	1		T37	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T304	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T142	8		T200	7		T308	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T298	4		T307	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T27	10		T35	17		T138	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	3		T165	4		T154	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T2	24		T11	31		T81	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T3	11		T24	10		T172	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T81	10		T147	8		T186	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	13		T165	8		T129	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T282	6		T283	10		T247	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T27	1		T154	12		T145	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	12		T231	5		T175	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	8		T38	19		T228	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T141	6		T24	12		T144	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	9		T141	24		T184	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	2		T146	10		T257	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T139	4		T144	9		T146	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T9	3		T144	10		T132	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T142	5		T132	18		T14	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T165	10		T131	15		T170	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	426	1			T1	5		T129	24		T231	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T81	1		T27	11		T35	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	4		T125	1		T165	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T2	27		T5	3		T11	34
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	12		T137	1		T24	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	1		T143	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T4	14		T127	1		T165	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T125	1		T143	1		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T27	2		T228	15		T154	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	13		T231	6		T175	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	13		T38	20		T141	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T37	1		T141	7		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	10		T141	13		T245	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	4		T30	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	2		T144	10		T146	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	1		T7	3		T9	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T129	10		T142	6		T139	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	1		T29	1		T225	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T1	8		T168	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T243	8		T287	6		T305	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T174	15		T75	14		T306	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T27	7		T35	14		T128	23
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	2		T125	10		T165	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T30	1		T126	25		T152	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T24	4		T268	10		T309	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	12		T186	15		T281	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T165	6		T129	10		T234	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T125	12		T283	12		T242	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T27	1		T228	11		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T231	2		T241	16		T88	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	2		T38	10		T141	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T37	8		T141	6		T24	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T141	11		T245	16		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T36	2		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	2		T146	10		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	3		T125	16		T165	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T129	4		T142	4		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T29	11		T225	8		T130	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	1		T37	4		T129	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T310	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T174	20		T75	12		T311	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T200	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T304	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T81	1		T142	9		T200	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T169	1		T298	5		T307	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T27	11		T35	18		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	4		T125	1		T165	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T2	27		T5	3		T11	34
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	12		T127	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T81	11		T147	9		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T4	14		T165	9		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T143	2		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T27	2		T154	13		T145	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T8	13		T125	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	13		T38	20		T228	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T37	1		T141	7		T24	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	10		T141	26		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	4		T30	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	2		T226	1		T139	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T7	2		T9	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T142	6		T132	19		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T7	1		T8	1		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	511	1			T1	8		T168	1		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T200	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T304	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T142	10		T200	8		T305	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T298	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T27	7		T35	14		T128	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	2		T125	10		T165	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T30	1		T126	25		T152	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T24	4		T246	8		T309	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T26	12		T186	15		T281	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T165	6		T129	10		T234	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T241	16		T283	12		T247	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T27	1		T154	12		T146	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T125	12		T231	2		T242	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	2		T38	10		T228	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T37	8		T141	6		T24	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T141	21		T184	8		T26	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T36	2		T130	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	2		T226	11		T146	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	3		T125	16		T132	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T142	4		T14	2		T230	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T29	11		T225	8		T165	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T1	1		T37	4		T129	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11