Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22803

1

T1

62

T2

27

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3685

1

T1

9

T3

12

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20134

1

T1

55

T3

12

T4

24

auto[1]

6354

1

T1

16

T2

27

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	647	1			T1	3		T3	1		T7	1
values[0]	20	1			T266	18		T188	2		-	-
values[1]	588	1			T1	9		T81	7		T37	9
values[2]	3129	1			T2	27		T5	3		T11	34
values[3]	557	1			T6	1		T8	13		T29	12
values[4]	737	1			T3	12		T8	1		T37	5
values[5]	712	1			T4	24		T9	12		T27	18
values[6]	979	1			T168	1		T129	21		T142	10
values[7]	635	1			T1	4		T81	12		T12	15
values[8]	705	1			T9	6		T125	11		T127	1
values[9]	1033	1			T7	2		T12	1		T38	30
minimum	16746	1			T1	55		T8	31		T9	94

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	623	1			T1	9		T81	7		T37	9
values[1]	3066	1			T2	27		T5	3		T11	34
values[2]	575	1			T3	12		T6	1		T8	13
values[3]	735	1			T4	10		T8	1		T30	1
values[4]	825	1			T4	14		T9	12		T27	18
values[5]	826	1			T81	11		T168	1		T129	21
values[6]	613	1			T1	4		T81	1		T12	15
values[7]	781	1			T7	2		T9	6		T125	11
values[8]	999	1			T7	1		T27	3		T38	30
values[9]	120	1			T3	1		T12	1		T234	14
minimum	17325	1			T1	58		T8	31		T9	95

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T37	9		T137	1		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	4		T81	1		T125	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T2	3		T5	3		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T168	1		T225	9		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T8	1		T29	12		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	1		T6	1		T130	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	1		T30	1		T154	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	1		T37	5		T141	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T4	1		T129	5		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	9		T27	8		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T81	1		T168	1		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T143	2		T139	1		T244	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	4		T81	1		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	7		T154	13		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T9	3		T125	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	1		T228	12		T165	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T27	2		T38	11		T125	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T7	1		T140	1		T231	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T3	1		T12	1		T234	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T33	4		T161	1		T312	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17048	1			T1	53		T8	31		T9	94
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T129	14		T33	1		T258	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T147	8		T184	11		T276	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	5		T81	6		T131	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T2	24		T11	31		T35	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T144	8		T175	13		T292	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T8	12		T24	12		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	11		T24	10		T132	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	9		T154	10		T142	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T141	12		T158	9		T283	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	13		T129	9		T145	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	3		T27	10		T12	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T81	10		T129	10		T142	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T139	4		T155	16		T186	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T30	1		T141	12		T144	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	8		T154	12		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	3		T142	9		T25	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T228	14		T165	14		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T27	1		T38	19		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T231	2		T132	3		T155	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T234	6		T266	12		T284	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T33	2		T272	9		T302	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	5		T9	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T129	15		T258	8		T313	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	443	1			T1	3		T3	1		T9	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T7	1		T140	1		T231	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T266	1		T188	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	9		T25	1		T131	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	4		T81	1		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1671	1			T2	3		T5	3		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T168	1		T125	13		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T8	1		T29	12		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	1		T225	9		T130	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T154	12		T142	11		T24	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	1		T8	1		T37	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	2		T30	1		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	9		T27	8		T12	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T168	1		T129	11		T142	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T143	1		T139	1		T244	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	4		T81	2		T30	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	7		T154	13		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	3		T125	11		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T228	12		T165	10		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T7	1		T12	1		T38	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T7	1		T165	5		T245	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T1	50		T8	31		T9	93
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T27	1		T234	6		T292	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T231	2		T243	7		T14	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T266	17		T188	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T131	15		T147	8		T268	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T1	5		T81	6		T129	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T2	24		T11	31		T35	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T175	13		T32	14		T292	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	12		T148	10		T158	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T24	10		T144	8		T158	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T154	10		T142	8		T24	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	11		T141	12		T132	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	22		T129	9		T33	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	3		T27	10		T12	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T129	10		T142	5		T145	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T139	4		T155	16		T186	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T81	10		T30	1		T141	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	8		T154	12		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T9	3		T142	9		T25	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T228	14		T165	10		T138	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T38	19		T139	4		T231	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T165	4		T132	3		T155	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T37	1		T137	1		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	8		T81	7		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T2	27		T5	3		T11	34
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T168	1		T225	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	13		T29	1		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	12		T6	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	10		T30	1		T154	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	1		T37	1		T141	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T4	14		T129	10		T145	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	9		T27	11		T12	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T81	11		T168	1		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T143	2		T139	5		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	2		T81	1		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	13		T154	13		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	1		T9	4		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	1		T228	15		T165	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T27	2		T38	20		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T7	1		T140	1		T231	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T3	1		T12	1		T234	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T33	3		T161	1		T312	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17200	1			T1	58		T8	31		T9	95
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T129	16		T33	1		T258	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T37	8		T184	8		T246	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T1	1		T125	12		T131	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T35	14		T126	25		T165	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T225	8		T175	4		T292	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T29	11		T24	11		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T130	13		T24	4		T241	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T154	11		T142	10		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T37	4		T141	11		T130	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T129	4		T33	3		T212	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	3		T27	7		T12	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T129	10		T142	4		T146	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T244	13		T155	11		T186	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T1	2		T30	1		T141	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	2		T154	12		T171	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	2		T125	10		T128	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T228	11		T165	13		T141	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T27	1		T38	10		T125	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T231	10		T132	4		T34	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T234	7		T273	1		T284	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T33	3		T272	7		T302	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T131	15		T288	10		T176	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T129	13		T258	9		T313	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	440	1			T1	3		T3	1		T9	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T7	1		T140	1		T231	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T266	18		T188	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T37	1		T25	1		T131	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	8		T81	7		T129	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T2	27		T5	3		T11	34
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T168	1		T125	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	13		T29	1		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	1		T225	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T154	11		T142	9		T24	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T3	12		T8	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T4	24		T30	1		T129	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	9		T27	11		T12	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T168	1		T129	11		T142	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T143	1		T139	5		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	2		T81	12		T30	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	13		T154	13		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	4		T125	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T228	15		T165	11		T138	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	1		T12	1		T38	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T7	1		T165	5		T245	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16746	1			T1	55		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T27	1		T234	7		T292	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T231	10		T14	2		T281	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	8		T131	15		T288	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T1	1		T129	13		T131	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T35	14		T126	25		T165	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T125	12		T175	4		T32	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T29	11		T314	1		T201	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T225	8		T130	13		T24	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T154	11		T142	10		T24	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T37	4		T141	11		T130	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T129	4		T33	3		T212	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	3		T27	7		T12	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T129	10		T142	4		T146	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T244	13		T155	11		T186	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	2		T30	1		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	2		T154	12		T171	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	2		T125	10		T128	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T228	11		T165	9		T141	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T38	10		T125	16		T245	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T165	4		T245	11		T132	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11