Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23095

1

T1

71

T2

27

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3393

1

T6

1

T8

1

T9

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

62

T3

13

T4

24

auto[1]

6348

1

T1

9

T2

27

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	389	1			T234	14		T245	12		T133	1
values[0]	28	1			T284	28		-	-		-	-
values[1]	740	1			T6	1		T9	6		T81	11
values[2]	503	1			T30	3		T36	3		T128	24
values[3]	613	1			T168	1		T125	13		T165	15
values[4]	530	1			T8	1		T81	8		T168	1
values[5]	2852	1			T1	4		T2	27		T3	1
values[6]	645	1			T37	9		T127	1		T137	1
values[7]	886	1			T3	12		T4	14		T9	12
values[8]	868	1			T7	2		T8	13		T29	12
values[9]	1301	1			T1	9		T4	10		T7	1
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	718	1			T9	6		T81	11		T35	32
values[1]	573	1			T30	3		T36	3		T128	24
values[2]	540	1			T168	2		T125	13		T225	9
values[3]	2989	1			T2	27		T5	3		T8	1
values[4]	444	1			T1	4		T3	1		T127	2
values[5]	691	1			T3	12		T4	14		T37	9
values[6]	811	1			T9	12		T27	21		T154	25
values[7]	958	1			T7	3		T8	13		T29	12
values[8]	1274	1			T1	9		T4	10		T12	5
values[9]	175	1			T125	11		T234	14		T245	12
minimum	17315	1			T1	58		T6	1		T8	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	3		T81	1		T35	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T145	1		T33	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T30	2		T129	11		T257	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T36	3		T128	24		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T168	1		T130	3		T142	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T168	1		T125	13		T225	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1725	1			T2	3		T5	3		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	1		T81	2		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T1	4		T3	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T127	1		T141	11		T231	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	1		T4	1		T37	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T137	1		T32	17		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T27	8		T154	13		T129	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	9		T27	2		T231	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T7	3		T8	1		T29	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T144	1		T147	1		T132	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T1	4		T4	1		T154	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T12	3		T165	15		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T125	11		T234	8		T131	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T245	12		T177	9		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17071	1			T1	53		T8	31		T9	94
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T6	1		T125	17		T308	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	3		T81	10		T35	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T145	7		T33	2		T232	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T30	1		T129	10		T257	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T132	8		T232	10		T176	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T142	8		T24	12		T196	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T165	8		T132	18		T33	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T2	24		T11	31		T233	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T81	6		T228	14		T232	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T144	9		T268	2		T159	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T141	12		T231	5		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	11		T4	13		T142	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T32	14		T282	16		T100	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T27	10		T154	12		T129	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	3		T27	1		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T8	12		T12	8		T138	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T144	8		T147	8		T132	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T1	5		T4	9		T154	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T12	2		T165	14		T175	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T234	6		T131	15		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T315	15		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	5		T9	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T308	1		T316	1		T307	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T234	8		T133	1		T174	21
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T245	12		T184	9		T241	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T284	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	3		T81	1		T35	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	1		T12	1		T125	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T30	2		T129	11		T170	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	3		T128	24		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T168	1		T24	12		T245	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T125	13		T165	7		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T141	12		T130	3		T142	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T8	1		T81	2		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1690	1			T1	4		T2	3		T3	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T30	1		T127	1		T228	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T37	9		T127	1		T142	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T137	1		T141	11		T231	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	1		T4	1		T27	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	9		T27	2		T231	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T7	2		T8	1		T29	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T144	1		T147	1		T186	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T1	4		T4	1		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T12	3		T165	15		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T234	6		T174	14		T15	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T184	11		T241	2		T283	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T284	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	3		T81	10		T35	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T132	8		T33	2		T232	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T30	1		T129	10		T170	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T145	7		T232	10		T148	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T24	12		T14	2		T281	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T165	8		T132	18		T186	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T141	12		T142	8		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T81	6		T33	2		T232	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T2	24		T11	31		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T228	14		T13	1		T171	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T142	5		T139	4		T144	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T141	12		T231	5		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	11		T4	13		T27	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	3		T27	1		T231	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T8	12		T12	8		T154	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T144	8		T147	8		T186	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T1	5		T4	9		T154	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T12	2		T165	14		T132	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	4		T81	11		T35	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	1		T145	8		T33	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T30	2		T129	11		T257	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T36	1		T128	1		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T168	1		T130	1		T142	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T168	1		T125	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T2	27		T5	3		T11	34
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	1		T81	8		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	2		T3	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T127	1		T141	13		T231	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	12		T4	14		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T137	1		T32	15		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T27	11		T154	13		T129	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	9		T27	2		T231	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T7	3		T8	13		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T144	9		T147	9		T132	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T1	8		T4	10		T154	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	416	1			T12	4		T165	16		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T125	1		T234	7		T131	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T245	1		T177	1		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17186	1			T1	58		T8	31		T9	95
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T6	1		T125	1		T308	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T35	14		T230	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T33	3		T178	8		T286	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T30	1		T129	10		T257	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T36	2		T128	23		T132	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T130	2		T142	10		T24	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T125	12		T225	8		T165	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T126	25		T141	11		T152	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T228	11		T226	11		T177	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T1	2		T159	11		T258	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T141	10		T231	2		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T37	8		T142	4		T34	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T32	16		T196	13		T264	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T27	7		T154	12		T129	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	3		T27	1		T231	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T29	11		T12	2		T37	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T132	4		T186	10		T241	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T154	11		T131	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T12	1		T165	13		T244	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T125	10		T234	7		T131	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T245	11		T177	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T38	10		T141	6		T246	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T125	16		T190	16		T317	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T234	7		T133	1		T174	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T245	1		T184	12		T241	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T284	17		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	4		T81	11		T35	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	1		T12	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T30	2		T129	11		T170	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T36	1		T128	1		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T168	1		T24	13		T245	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T125	1		T165	9		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T141	13		T130	1		T142	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T8	1		T81	8		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T1	2		T2	27		T3	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T30	1		T127	1		T228	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	1		T127	1		T142	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T137	1		T141	13		T231	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	12		T4	14		T27	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	9		T27	2		T231	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T7	2		T8	13		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T144	9		T147	9		T186	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	381	1			T1	8		T4	10		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T12	4		T165	16		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T234	7		T174	20		T15	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T245	11		T184	8		T241	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T284	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	2		T35	14		T38	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T125	16		T132	3		T33	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T30	1		T129	10		T170	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T36	2		T128	23		T176	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	11		T245	16		T246	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T125	12		T165	6		T186	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T141	11		T130	2		T142	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T225	8		T226	11		T33	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T1	2		T126	25		T152	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T228	11		T13	1		T171	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T37	8		T142	4		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T141	10		T231	2		T196	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T27	7		T129	13		T130	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	3		T27	1		T231	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T29	11		T12	2		T37	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T186	10		T298	11		T99	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	1		T125	10		T154	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T12	1		T165	13		T132	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11