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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.07 96.67 100.00 100.00 98.83 98.33 91.32


Total test records in report: 919
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T793 /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.256975638 Jul 23 07:01:15 PM PDT 24 Jul 23 07:13:08 PM PDT 24 313143946974 ps
T794 /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.469131922 Jul 23 07:02:08 PM PDT 24 Jul 23 07:25:12 PM PDT 24 605614459326 ps
T795 /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1094780720 Jul 23 07:00:52 PM PDT 24 Jul 23 07:02:38 PM PDT 24 161401935393 ps
T796 /workspace/coverage/default/37.adc_ctrl_filters_wakeup.798653714 Jul 23 07:02:19 PM PDT 24 Jul 23 07:05:24 PM PDT 24 340246208488 ps
T52 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3142799235 Jul 23 05:43:02 PM PDT 24 Jul 23 05:43:06 PM PDT 24 900406768 ps
T46 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1120016475 Jul 23 05:43:25 PM PDT 24 Jul 23 05:43:30 PM PDT 24 4947228267 ps
T53 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.527037485 Jul 23 05:43:15 PM PDT 24 Jul 23 05:43:26 PM PDT 24 4099864853 ps
T797 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2957557205 Jul 23 05:43:42 PM PDT 24 Jul 23 05:43:45 PM PDT 24 526372432 ps
T798 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.674329232 Jul 23 05:43:49 PM PDT 24 Jul 23 05:43:52 PM PDT 24 404769435 ps
T104 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.13997310 Jul 23 05:43:29 PM PDT 24 Jul 23 05:43:31 PM PDT 24 493774026 ps
T47 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1074998260 Jul 23 05:43:16 PM PDT 24 Jul 23 05:43:28 PM PDT 24 4967443278 ps
T799 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2918994610 Jul 23 05:43:35 PM PDT 24 Jul 23 05:43:38 PM PDT 24 313619014 ps
T49 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.862008151 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:45 PM PDT 24 8661440770 ps
T800 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.177315735 Jul 23 05:43:44 PM PDT 24 Jul 23 05:43:46 PM PDT 24 386756399 ps
T801 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1034049530 Jul 23 05:43:16 PM PDT 24 Jul 23 05:43:18 PM PDT 24 608258845 ps
T122 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3385906128 Jul 23 05:43:09 PM PDT 24 Jul 23 05:43:14 PM PDT 24 1003976584 ps
T50 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2690611096 Jul 23 05:43:25 PM PDT 24 Jul 23 05:43:37 PM PDT 24 4288750421 ps
T105 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1890556499 Jul 23 05:43:17 PM PDT 24 Jul 23 05:43:19 PM PDT 24 405099420 ps
T57 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1340079246 Jul 23 05:43:36 PM PDT 24 Jul 23 05:43:40 PM PDT 24 375394129 ps
T58 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.183705999 Jul 23 05:43:33 PM PDT 24 Jul 23 05:43:35 PM PDT 24 534551205 ps
T48 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3995997844 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:29 PM PDT 24 2472998198 ps
T802 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1668752140 Jul 23 05:43:19 PM PDT 24 Jul 23 05:43:21 PM PDT 24 336486950 ps
T59 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.114451790 Jul 23 05:43:15 PM PDT 24 Jul 23 05:43:18 PM PDT 24 1261102099 ps
T84 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1668055387 Jul 23 05:43:14 PM PDT 24 Jul 23 05:43:17 PM PDT 24 499965373 ps
T803 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.554873549 Jul 23 05:43:42 PM PDT 24 Jul 23 05:43:44 PM PDT 24 337808179 ps
T62 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3429498565 Jul 23 05:43:31 PM PDT 24 Jul 23 05:43:34 PM PDT 24 552939878 ps
T119 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.741098170 Jul 23 05:43:16 PM PDT 24 Jul 23 05:43:23 PM PDT 24 5374798006 ps
T106 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3305025227 Jul 23 05:43:34 PM PDT 24 Jul 23 05:43:36 PM PDT 24 418626226 ps
T64 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4247562467 Jul 23 05:43:17 PM PDT 24 Jul 23 05:43:20 PM PDT 24 548506690 ps
T65 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4024853845 Jul 23 05:43:29 PM PDT 24 Jul 23 05:43:32 PM PDT 24 689168050 ps
T804 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1685498515 Jul 23 05:43:08 PM PDT 24 Jul 23 05:43:10 PM PDT 24 402464638 ps
T805 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.35950714 Jul 23 05:43:34 PM PDT 24 Jul 23 05:43:37 PM PDT 24 458193108 ps
T107 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3340735339 Jul 23 05:43:02 PM PDT 24 Jul 23 05:43:06 PM PDT 24 815572085 ps
T51 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.192075765 Jul 23 05:43:32 PM PDT 24 Jul 23 05:43:53 PM PDT 24 8322399341 ps
T806 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1850616327 Jul 23 05:43:17 PM PDT 24 Jul 23 05:43:19 PM PDT 24 526328420 ps
T120 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3831125429 Jul 23 05:43:09 PM PDT 24 Jul 23 05:43:13 PM PDT 24 2615957796 ps
T807 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.826289335 Jul 23 05:43:00 PM PDT 24 Jul 23 05:43:02 PM PDT 24 499140950 ps
T121 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1590419267 Jul 23 05:43:15 PM PDT 24 Jul 23 05:43:17 PM PDT 24 491187148 ps
T63 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1924518627 Jul 23 05:43:08 PM PDT 24 Jul 23 05:43:10 PM PDT 24 525658103 ps
T808 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.759184487 Jul 23 05:43:41 PM PDT 24 Jul 23 05:43:43 PM PDT 24 531533906 ps
T809 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2603945649 Jul 23 05:43:27 PM PDT 24 Jul 23 05:43:29 PM PDT 24 809391469 ps
T108 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3196608726 Jul 23 05:43:09 PM PDT 24 Jul 23 05:43:11 PM PDT 24 383780351 ps
T109 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.75271105 Jul 23 05:43:08 PM PDT 24 Jul 23 05:43:10 PM PDT 24 306456149 ps
T110 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.317195540 Jul 23 05:43:28 PM PDT 24 Jul 23 05:43:31 PM PDT 24 501368965 ps
T111 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1822317918 Jul 23 05:43:08 PM PDT 24 Jul 23 05:43:11 PM PDT 24 1255136786 ps
T810 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.212292485 Jul 23 05:43:15 PM PDT 24 Jul 23 05:43:18 PM PDT 24 708882915 ps
T811 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.563449708 Jul 23 05:43:45 PM PDT 24 Jul 23 05:43:47 PM PDT 24 492580234 ps
T812 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3718323943 Jul 23 05:43:47 PM PDT 24 Jul 23 05:43:49 PM PDT 24 381340173 ps
T813 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2108663789 Jul 23 05:43:10 PM PDT 24 Jul 23 05:43:12 PM PDT 24 388199336 ps
T814 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3563517652 Jul 23 05:43:34 PM PDT 24 Jul 23 05:43:36 PM PDT 24 489167097 ps
T815 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.119576622 Jul 23 05:43:35 PM PDT 24 Jul 23 05:43:38 PM PDT 24 411813891 ps
T816 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1215379576 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:39 PM PDT 24 4877346095 ps
T817 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3973232658 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:31 PM PDT 24 371092762 ps
T112 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2712508985 Jul 23 05:43:11 PM PDT 24 Jul 23 05:44:27 PM PDT 24 34650917846 ps
T818 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.42117975 Jul 23 05:43:14 PM PDT 24 Jul 23 05:43:16 PM PDT 24 414653596 ps
T348 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.639473072 Jul 23 05:43:09 PM PDT 24 Jul 23 05:43:27 PM PDT 24 8035975928 ps
T819 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2636026280 Jul 23 05:43:34 PM PDT 24 Jul 23 05:43:36 PM PDT 24 539293207 ps
T820 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.796832439 Jul 23 05:43:09 PM PDT 24 Jul 23 05:43:13 PM PDT 24 465061416 ps
T821 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.816185592 Jul 23 05:43:14 PM PDT 24 Jul 23 05:43:17 PM PDT 24 584634156 ps
T822 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.24328749 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:29 PM PDT 24 509331942 ps
T823 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3638715387 Jul 23 05:43:51 PM PDT 24 Jul 23 05:43:53 PM PDT 24 316814472 ps
T824 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.379528736 Jul 23 05:43:48 PM PDT 24 Jul 23 05:43:50 PM PDT 24 503671220 ps
T113 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3373443636 Jul 23 05:43:11 PM PDT 24 Jul 23 05:43:13 PM PDT 24 389929084 ps
T825 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3719865003 Jul 23 05:43:42 PM PDT 24 Jul 23 05:43:44 PM PDT 24 480397652 ps
T826 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3228655650 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:29 PM PDT 24 560655402 ps
T346 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.346161157 Jul 23 05:43:02 PM PDT 24 Jul 23 05:43:16 PM PDT 24 4291652411 ps
T827 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.29769243 Jul 23 05:43:25 PM PDT 24 Jul 23 05:43:27 PM PDT 24 386566446 ps
T828 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.370536063 Jul 23 05:43:48 PM PDT 24 Jul 23 05:43:50 PM PDT 24 517449404 ps
T829 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.620454649 Jul 23 05:43:06 PM PDT 24 Jul 23 05:43:09 PM PDT 24 2969087007 ps
T830 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1671082021 Jul 23 05:43:36 PM PDT 24 Jul 23 05:43:45 PM PDT 24 2220555763 ps
T831 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2057033160 Jul 23 05:43:09 PM PDT 24 Jul 23 05:43:14 PM PDT 24 593889905 ps
T114 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1058212889 Jul 23 05:43:13 PM PDT 24 Jul 23 05:44:54 PM PDT 24 20620257881 ps
T832 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1074734865 Jul 23 05:43:42 PM PDT 24 Jul 23 05:43:44 PM PDT 24 461959414 ps
T833 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3740677699 Jul 23 05:43:48 PM PDT 24 Jul 23 05:43:51 PM PDT 24 513099851 ps
T834 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.361991145 Jul 23 05:43:39 PM PDT 24 Jul 23 05:43:40 PM PDT 24 526878746 ps
T835 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3556948808 Jul 23 05:43:16 PM PDT 24 Jul 23 05:43:22 PM PDT 24 626732017 ps
T836 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2765641512 Jul 23 05:43:41 PM PDT 24 Jul 23 05:43:44 PM PDT 24 333972895 ps
T837 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.748108534 Jul 23 05:43:17 PM PDT 24 Jul 23 05:43:31 PM PDT 24 3990434588 ps
T838 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1605596742 Jul 23 05:43:47 PM PDT 24 Jul 23 05:43:50 PM PDT 24 532592327 ps
T839 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.951558838 Jul 23 05:43:47 PM PDT 24 Jul 23 05:43:49 PM PDT 24 474274679 ps
T840 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1127458855 Jul 23 05:43:14 PM PDT 24 Jul 23 05:43:23 PM PDT 24 8009120147 ps
T841 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4134263570 Jul 23 05:43:15 PM PDT 24 Jul 23 05:43:22 PM PDT 24 5018788473 ps
T842 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1281851706 Jul 23 05:43:00 PM PDT 24 Jul 23 05:43:02 PM PDT 24 2001723896 ps
T66 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2015203183 Jul 23 05:43:17 PM PDT 24 Jul 23 05:43:24 PM PDT 24 8746418885 ps
T843 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.420504574 Jul 23 05:43:34 PM PDT 24 Jul 23 05:43:37 PM PDT 24 1930171522 ps
T844 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4065798755 Jul 23 05:43:27 PM PDT 24 Jul 23 05:43:31 PM PDT 24 462395871 ps
T845 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1923371829 Jul 23 05:43:41 PM PDT 24 Jul 23 05:43:42 PM PDT 24 528110805 ps
T115 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2648874111 Jul 23 05:43:12 PM PDT 24 Jul 23 05:43:17 PM PDT 24 1089075160 ps
T846 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1790381316 Jul 23 05:43:09 PM PDT 24 Jul 23 05:43:12 PM PDT 24 417542770 ps
T847 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1226268552 Jul 23 05:43:46 PM PDT 24 Jul 23 05:43:48 PM PDT 24 405389797 ps
T848 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2753179244 Jul 23 05:43:25 PM PDT 24 Jul 23 05:43:28 PM PDT 24 468924749 ps
T849 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3096872430 Jul 23 05:43:48 PM PDT 24 Jul 23 05:43:50 PM PDT 24 299765684 ps
T850 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3967392378 Jul 23 05:43:01 PM PDT 24 Jul 23 05:43:03 PM PDT 24 440461800 ps
T851 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1740678842 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:29 PM PDT 24 601151249 ps
T852 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.289757313 Jul 23 05:43:28 PM PDT 24 Jul 23 05:43:31 PM PDT 24 413106503 ps
T853 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3598369184 Jul 23 05:43:11 PM PDT 24 Jul 23 05:43:15 PM PDT 24 1180925073 ps
T854 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2967274207 Jul 23 05:43:39 PM PDT 24 Jul 23 05:43:42 PM PDT 24 388499436 ps
T855 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1600847632 Jul 23 05:43:47 PM PDT 24 Jul 23 05:43:50 PM PDT 24 361207076 ps
T856 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.568399299 Jul 23 05:43:25 PM PDT 24 Jul 23 05:43:27 PM PDT 24 529563053 ps
T857 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2166688389 Jul 23 05:43:15 PM PDT 24 Jul 23 05:43:18 PM PDT 24 2280338827 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.746476330 Jul 23 05:43:08 PM PDT 24 Jul 23 05:43:10 PM PDT 24 684605481 ps
T859 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3828707394 Jul 23 05:43:51 PM PDT 24 Jul 23 05:43:54 PM PDT 24 406240033 ps
T860 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1125384057 Jul 23 05:43:10 PM PDT 24 Jul 23 05:43:12 PM PDT 24 784549603 ps
T861 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1899776951 Jul 23 05:43:39 PM PDT 24 Jul 23 05:43:42 PM PDT 24 764059027 ps
T862 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2544519772 Jul 23 05:43:33 PM PDT 24 Jul 23 05:43:44 PM PDT 24 4386868580 ps
T863 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.4237837652 Jul 23 05:43:49 PM PDT 24 Jul 23 05:43:52 PM PDT 24 438333348 ps
T864 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2809195068 Jul 23 05:43:28 PM PDT 24 Jul 23 05:43:34 PM PDT 24 4110650594 ps
T865 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2434424054 Jul 23 05:43:42 PM PDT 24 Jul 23 05:43:45 PM PDT 24 437103005 ps
T866 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2377649285 Jul 23 05:43:50 PM PDT 24 Jul 23 05:43:53 PM PDT 24 414504591 ps
T867 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.407197355 Jul 23 05:43:03 PM PDT 24 Jul 23 05:43:06 PM PDT 24 856515752 ps
T349 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4170672352 Jul 23 05:43:16 PM PDT 24 Jul 23 05:43:23 PM PDT 24 7997626920 ps
T868 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2233214118 Jul 23 05:43:39 PM PDT 24 Jul 23 05:43:45 PM PDT 24 2535521013 ps
T869 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2844780064 Jul 23 05:43:27 PM PDT 24 Jul 23 05:43:51 PM PDT 24 8415098519 ps
T116 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3595590903 Jul 23 05:43:13 PM PDT 24 Jul 23 05:43:15 PM PDT 24 1003173707 ps
T870 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1404037519 Jul 23 05:43:10 PM PDT 24 Jul 23 05:43:14 PM PDT 24 4994282709 ps
T871 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1141877507 Jul 23 05:43:35 PM PDT 24 Jul 23 05:43:39 PM PDT 24 580047265 ps
T872 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3866035230 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:29 PM PDT 24 359464205 ps
T873 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1815484274 Jul 23 05:43:41 PM PDT 24 Jul 23 05:43:43 PM PDT 24 435071280 ps
T874 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3918966512 Jul 23 05:43:27 PM PDT 24 Jul 23 05:43:30 PM PDT 24 561280593 ps
T875 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3670619899 Jul 23 05:43:41 PM PDT 24 Jul 23 05:43:50 PM PDT 24 2488371114 ps
T117 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.127671469 Jul 23 05:43:10 PM PDT 24 Jul 23 05:43:13 PM PDT 24 397956700 ps
T876 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2736019936 Jul 23 05:43:27 PM PDT 24 Jul 23 05:43:29 PM PDT 24 491166189 ps
T877 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.348492411 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:35 PM PDT 24 4297562051 ps
T878 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.910243778 Jul 23 05:43:35 PM PDT 24 Jul 23 05:43:37 PM PDT 24 438259048 ps
T879 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.466770429 Jul 23 05:43:11 PM PDT 24 Jul 23 05:43:14 PM PDT 24 391298766 ps
T880 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2129345791 Jul 23 05:43:13 PM PDT 24 Jul 23 05:43:16 PM PDT 24 382460742 ps
T881 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2098667068 Jul 23 05:43:15 PM PDT 24 Jul 23 05:43:17 PM PDT 24 501103158 ps
T882 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1844681171 Jul 23 05:43:47 PM PDT 24 Jul 23 05:43:49 PM PDT 24 460828430 ps
T883 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.824113789 Jul 23 05:43:25 PM PDT 24 Jul 23 05:43:31 PM PDT 24 4349545535 ps
T67 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.993279403 Jul 23 05:43:36 PM PDT 24 Jul 23 05:43:58 PM PDT 24 8719242545 ps
T884 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.487241393 Jul 23 05:43:25 PM PDT 24 Jul 23 05:43:28 PM PDT 24 4169223313 ps
T885 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4145183226 Jul 23 05:43:41 PM PDT 24 Jul 23 05:43:43 PM PDT 24 522983295 ps
T886 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1044333723 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:29 PM PDT 24 468334080 ps
T887 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1869999081 Jul 23 05:43:42 PM PDT 24 Jul 23 05:43:45 PM PDT 24 414605288 ps
T888 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2639656479 Jul 23 05:43:28 PM PDT 24 Jul 23 05:43:31 PM PDT 24 394518868 ps
T889 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2061880509 Jul 23 05:43:15 PM PDT 24 Jul 23 05:43:19 PM PDT 24 326776202 ps
T890 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.633082596 Jul 23 05:43:34 PM PDT 24 Jul 23 05:43:42 PM PDT 24 4102441068 ps
T891 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.560860661 Jul 23 05:43:14 PM PDT 24 Jul 23 05:43:20 PM PDT 24 5086184064 ps
T892 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3284380377 Jul 23 05:43:16 PM PDT 24 Jul 23 05:43:20 PM PDT 24 503218801 ps
T118 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3379776208 Jul 23 05:43:41 PM PDT 24 Jul 23 05:43:43 PM PDT 24 314331287 ps
T893 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1013439429 Jul 23 05:43:13 PM PDT 24 Jul 23 05:43:14 PM PDT 24 344511613 ps
T347 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1209381615 Jul 23 05:43:14 PM PDT 24 Jul 23 05:43:26 PM PDT 24 4314036915 ps
T894 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3889459781 Jul 23 05:43:27 PM PDT 24 Jul 23 05:43:29 PM PDT 24 538017005 ps
T895 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.752935494 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:29 PM PDT 24 390449788 ps
T896 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.338319182 Jul 23 05:43:34 PM PDT 24 Jul 23 05:43:45 PM PDT 24 4466933310 ps
T897 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3207075206 Jul 23 05:43:14 PM PDT 24 Jul 23 05:43:16 PM PDT 24 392285283 ps
T898 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4123128449 Jul 23 05:43:16 PM PDT 24 Jul 23 05:43:19 PM PDT 24 566781127 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3111926421 Jul 23 05:43:08 PM PDT 24 Jul 23 05:43:37 PM PDT 24 27051409889 ps
T900 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1033957189 Jul 23 05:43:17 PM PDT 24 Jul 23 05:43:20 PM PDT 24 539407598 ps
T901 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1547803487 Jul 23 05:43:34 PM PDT 24 Jul 23 05:43:35 PM PDT 24 927899577 ps
T902 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3387169903 Jul 23 05:43:11 PM PDT 24 Jul 23 05:43:14 PM PDT 24 4893225352 ps
T903 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2722434919 Jul 23 05:43:09 PM PDT 24 Jul 23 05:43:13 PM PDT 24 2429685384 ps
T904 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1002846141 Jul 23 05:43:37 PM PDT 24 Jul 23 05:43:38 PM PDT 24 529422247 ps
T905 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3080377331 Jul 23 05:43:15 PM PDT 24 Jul 23 05:43:18 PM PDT 24 663641060 ps
T906 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3292343387 Jul 23 05:43:14 PM PDT 24 Jul 23 05:43:16 PM PDT 24 595013439 ps
T907 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3717479922 Jul 23 05:43:26 PM PDT 24 Jul 23 05:43:29 PM PDT 24 513891116 ps
T908 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.417061377 Jul 23 05:43:42 PM PDT 24 Jul 23 05:43:44 PM PDT 24 357059132 ps
T909 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2098496030 Jul 23 05:43:13 PM PDT 24 Jul 23 05:43:15 PM PDT 24 844711106 ps
T910 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1744549192 Jul 23 05:43:15 PM PDT 24 Jul 23 05:43:18 PM PDT 24 411482961 ps
T911 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.847726042 Jul 23 05:43:09 PM PDT 24 Jul 23 05:43:22 PM PDT 24 27487159611 ps
T912 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1460401103 Jul 23 05:43:25 PM PDT 24 Jul 23 05:43:29 PM PDT 24 896908237 ps
T913 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1043083030 Jul 23 05:43:27 PM PDT 24 Jul 23 05:43:36 PM PDT 24 2823461930 ps
T914 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2405486997 Jul 23 05:43:10 PM PDT 24 Jul 23 05:43:14 PM PDT 24 934826254 ps
T915 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1369730736 Jul 23 05:43:15 PM PDT 24 Jul 23 05:43:18 PM PDT 24 578300421 ps
T916 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2591365122 Jul 23 05:43:04 PM PDT 24 Jul 23 05:43:10 PM PDT 24 1169559863 ps
T68 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.824453307 Jul 23 05:43:02 PM PDT 24 Jul 23 05:43:11 PM PDT 24 8301977021 ps
T917 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2226666860 Jul 23 05:43:41 PM PDT 24 Jul 23 05:43:43 PM PDT 24 456721787 ps
T918 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1642138646 Jul 23 05:43:02 PM PDT 24 Jul 23 05:43:13 PM PDT 24 7580384862 ps
T919 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2337042530 Jul 23 05:43:49 PM PDT 24 Jul 23 05:43:52 PM PDT 24 484326848 ps

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.881289735
Short name T1
Test name
Test status
Simulation time 155978851867 ps
CPU time 125.28 seconds
Started Jul 23 07:00:49 PM PDT 24
Finished Jul 23 07:02:56 PM PDT 24
Peak memory 210036 kb
Host smart-b42aa389-b1a7-4fd6-84a3-aafd7864deb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881289735 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.881289735
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.196484327
Short name T41
Test name
Test status
Simulation time 106612820335 ps
CPU time 403.22 seconds
Started Jul 23 07:02:10 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 201696 kb
Host smart-7d2baea4-ad86-494f-b27c-15251ec804a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196484327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.196484327
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2915962682
Short name T4
Test name
Test status
Simulation time 323417885840 ps
CPU time 47.57 seconds
Started Jul 23 07:00:47 PM PDT 24
Finished Jul 23 07:01:35 PM PDT 24
Peak memory 201240 kb
Host smart-b5950320-d928-4a84-b5de-3fb475b3dd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915962682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2915962682
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3330587417
Short name T142
Test name
Test status
Simulation time 527011021753 ps
CPU time 1038.8 seconds
Started Jul 23 07:02:12 PM PDT 24
Finished Jul 23 07:19:32 PM PDT 24
Peak memory 201284 kb
Host smart-0c7a4469-bf80-4c57-83c9-1108a9b66c31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330587417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3330587417
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2996899168
Short name T12
Test name
Test status
Simulation time 168611209034 ps
CPU time 136.77 seconds
Started Jul 23 07:00:35 PM PDT 24
Finished Jul 23 07:02:54 PM PDT 24
Peak memory 217568 kb
Host smart-464c4b2d-4e62-4083-b7fd-f09af96b1df5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996899168 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2996899168
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.207912720
Short name T33
Test name
Test status
Simulation time 319014515827 ps
CPU time 156.69 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:03:55 PM PDT 24
Peak memory 210572 kb
Host smart-203cf310-f588-4210-843a-3ceb33b4ad1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207912720 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.207912720
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3937467063
Short name T141
Test name
Test status
Simulation time 495500620274 ps
CPU time 283.73 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:06:02 PM PDT 24
Peak memory 201280 kb
Host smart-1d7d001a-76d9-4a3c-9619-e7bd7bd0330b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937467063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3937467063
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2331225530
Short name T129
Test name
Test status
Simulation time 494127923600 ps
CPU time 1149.73 seconds
Started Jul 23 07:02:52 PM PDT 24
Finished Jul 23 07:22:03 PM PDT 24
Peak memory 201236 kb
Host smart-55804570-3139-4e04-847d-a89bba614b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331225530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2331225530
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1546042163
Short name T9
Test name
Test status
Simulation time 261117253342 ps
CPU time 159.41 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:03:23 PM PDT 24
Peak memory 217400 kb
Host smart-20d3533c-8375-49cd-9f8d-a997fd18de5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546042163 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1546042163
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2483607664
Short name T662
Test name
Test status
Simulation time 270726918808 ps
CPU time 440.72 seconds
Started Jul 23 07:03:18 PM PDT 24
Finished Jul 23 07:10:40 PM PDT 24
Peak memory 218052 kb
Host smart-ccfb614f-92d8-4c92-bc4e-8223d20cb459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483607664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2483607664
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.60402367
Short name T132
Test name
Test status
Simulation time 556401809958 ps
CPU time 641.39 seconds
Started Jul 23 07:03:10 PM PDT 24
Finished Jul 23 07:13:53 PM PDT 24
Peak memory 201244 kb
Host smart-dcdfd1cd-09d2-4a75-9849-4ebbc5bd648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60402367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.60402367
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3142799235
Short name T52
Test name
Test status
Simulation time 900406768 ps
CPU time 3.02 seconds
Started Jul 23 05:43:02 PM PDT 24
Finished Jul 23 05:43:06 PM PDT 24
Peak memory 218144 kb
Host smart-bbc37e89-66c2-4790-9717-fe8699b84be6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142799235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3142799235
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2877345760
Short name T177
Test name
Test status
Simulation time 538436591864 ps
CPU time 192.27 seconds
Started Jul 23 07:00:33 PM PDT 24
Finished Jul 23 07:03:46 PM PDT 24
Peak memory 201244 kb
Host smart-7f697cb0-00f3-4723-ae4f-6bb674e9b8f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877345760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2877345760
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2495434295
Short name T131
Test name
Test status
Simulation time 326010636501 ps
CPU time 193.47 seconds
Started Jul 23 07:00:03 PM PDT 24
Finished Jul 23 07:03:18 PM PDT 24
Peak memory 201212 kb
Host smart-095fd9bc-8bfc-40f8-bda1-7abea54f198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495434295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2495434295
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2910036399
Short name T175
Test name
Test status
Simulation time 504343341718 ps
CPU time 254.1 seconds
Started Jul 23 07:03:18 PM PDT 24
Finished Jul 23 07:07:34 PM PDT 24
Peak memory 201092 kb
Host smart-041ea57c-4713-4ae9-8416-ab6c695c0ff0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910036399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2910036399
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3047218575
Short name T136
Test name
Test status
Simulation time 487276926649 ps
CPU time 129.46 seconds
Started Jul 23 07:02:54 PM PDT 24
Finished Jul 23 07:05:04 PM PDT 24
Peak memory 201296 kb
Host smart-2299d1b8-38c6-4e1c-b984-4c6af54babc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047218575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3047218575
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1544059332
Short name T28
Test name
Test status
Simulation time 396948247 ps
CPU time 1.49 seconds
Started Jul 23 07:00:34 PM PDT 24
Finished Jul 23 07:00:37 PM PDT 24
Peak memory 201092 kb
Host smart-920f65e3-87aa-4698-910f-416d2e75edde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544059332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1544059332
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2047115905
Short name T24
Test name
Test status
Simulation time 328537233575 ps
CPU time 770.86 seconds
Started Jul 23 07:02:52 PM PDT 24
Finished Jul 23 07:15:43 PM PDT 24
Peak memory 201180 kb
Host smart-5c68b2df-8f0b-4231-be4f-bffb08491d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047115905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2047115905
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2712508985
Short name T112
Test name
Test status
Simulation time 34650917846 ps
CPU time 74.31 seconds
Started Jul 23 05:43:11 PM PDT 24
Finished Jul 23 05:44:27 PM PDT 24
Peak memory 201776 kb
Host smart-13904d8e-7ad4-464f-a9b9-b6b72d7b575c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712508985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2712508985
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1016305210
Short name T242
Test name
Test status
Simulation time 334302067072 ps
CPU time 633.16 seconds
Started Jul 23 07:01:07 PM PDT 24
Finished Jul 23 07:11:42 PM PDT 24
Peak memory 201280 kb
Host smart-2771b438-7c36-435a-81f6-ad7a86cf4434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016305210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1016305210
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.701883016
Short name T71
Test name
Test status
Simulation time 4441489628 ps
CPU time 10.35 seconds
Started Jul 23 06:59:50 PM PDT 24
Finished Jul 23 07:00:08 PM PDT 24
Peak memory 216780 kb
Host smart-415bc069-eb8e-40a1-95f2-fd535c02012c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701883016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.701883016
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1686405017
Short name T174
Test name
Test status
Simulation time 188878599955 ps
CPU time 104.91 seconds
Started Jul 23 07:02:23 PM PDT 24
Finished Jul 23 07:04:09 PM PDT 24
Peak memory 201244 kb
Host smart-7f967934-137d-4ad7-9f30-d33509faa129
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686405017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1686405017
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3645723089
Short name T155
Test name
Test status
Simulation time 518939780260 ps
CPU time 462.47 seconds
Started Jul 23 07:00:46 PM PDT 24
Finished Jul 23 07:08:30 PM PDT 24
Peak memory 209804 kb
Host smart-7d410e01-7ce9-4929-82ba-b85f8d449f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645723089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3645723089
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3424565042
Short name T125
Test name
Test status
Simulation time 544809030116 ps
CPU time 199.83 seconds
Started Jul 23 07:02:35 PM PDT 24
Finished Jul 23 07:05:56 PM PDT 24
Peak memory 201216 kb
Host smart-0783f5d3-05f6-4ce4-9dd3-8fdb4864510d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424565042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3424565042
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2044912518
Short name T264
Test name
Test status
Simulation time 342603655939 ps
CPU time 99.07 seconds
Started Jul 23 07:00:57 PM PDT 24
Finished Jul 23 07:02:39 PM PDT 24
Peak memory 201096 kb
Host smart-782a0809-10a4-4262-aff0-e0cf53f76535
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044912518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2044912518
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.183432503
Short name T281
Test name
Test status
Simulation time 367176157328 ps
CPU time 188.51 seconds
Started Jul 23 07:01:16 PM PDT 24
Finished Jul 23 07:04:27 PM PDT 24
Peak memory 201224 kb
Host smart-83a4db7f-db46-4e19-aab6-c6c7c8872f7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183432503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.183432503
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1349352517
Short name T144
Test name
Test status
Simulation time 489901505455 ps
CPU time 572.41 seconds
Started Jul 23 06:59:54 PM PDT 24
Finished Jul 23 07:09:32 PM PDT 24
Peak memory 201280 kb
Host smart-295dafab-0e58-4d1a-904c-9fd41c662b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349352517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1349352517
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1601539760
Short name T256
Test name
Test status
Simulation time 372608969988 ps
CPU time 432.4 seconds
Started Jul 23 06:59:53 PM PDT 24
Finished Jul 23 07:07:11 PM PDT 24
Peak memory 201316 kb
Host smart-3304bc19-8ce8-427d-a154-b3f807263dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601539760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1601539760
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1985757185
Short name T27
Test name
Test status
Simulation time 183845249960 ps
CPU time 109.16 seconds
Started Jul 23 07:01:18 PM PDT 24
Finished Jul 23 07:03:09 PM PDT 24
Peak memory 209548 kb
Host smart-c867175b-09f3-47a8-8e78-a267d9dcf1f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985757185 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1985757185
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2015203183
Short name T66
Test name
Test status
Simulation time 8746418885 ps
CPU time 6.04 seconds
Started Jul 23 05:43:17 PM PDT 24
Finished Jul 23 05:43:24 PM PDT 24
Peak memory 201828 kb
Host smart-778844ec-e086-4bea-85d3-e06a6eb2fee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015203183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2015203183
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.4086867707
Short name T284
Test name
Test status
Simulation time 540806932421 ps
CPU time 87.54 seconds
Started Jul 23 07:01:03 PM PDT 24
Finished Jul 23 07:02:31 PM PDT 24
Peak memory 201216 kb
Host smart-4033da11-0305-4017-8d37-4d89e2670590
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086867707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.4086867707
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1916739134
Short name T146
Test name
Test status
Simulation time 723826105606 ps
CPU time 481.51 seconds
Started Jul 23 07:02:24 PM PDT 24
Finished Jul 23 07:10:26 PM PDT 24
Peak memory 201232 kb
Host smart-8684a5c7-5a7e-4477-bdbf-d62f8ec8aabc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916739134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1916739134
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.705402187
Short name T370
Test name
Test status
Simulation time 397990302028 ps
CPU time 286.61 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:05:42 PM PDT 24
Peak memory 201248 kb
Host smart-39489ccb-d515-4905-a4db-55384be5a88c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705402187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.705402187
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.962780277
Short name T73
Test name
Test status
Simulation time 171558856839 ps
CPU time 92.12 seconds
Started Jul 23 07:02:06 PM PDT 24
Finished Jul 23 07:03:39 PM PDT 24
Peak memory 201232 kb
Host smart-8969c256-cb5c-44cc-a0eb-281326897720
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962780277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.962780277
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1609650288
Short name T15
Test name
Test status
Simulation time 133303693185 ps
CPU time 161.03 seconds
Started Jul 23 07:03:11 PM PDT 24
Finished Jul 23 07:05:53 PM PDT 24
Peak memory 209544 kb
Host smart-fd8246a6-c865-4a3e-9e1d-ec4ddbf8e36a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609650288 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1609650288
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.13997310
Short name T104
Test name
Test status
Simulation time 493774026 ps
CPU time 1.05 seconds
Started Jul 23 05:43:29 PM PDT 24
Finished Jul 23 05:43:31 PM PDT 24
Peak memory 201416 kb
Host smart-ea8eaea6-2295-4220-b757-58771b0ed0d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13997310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.13997310
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2617940560
Short name T14
Test name
Test status
Simulation time 1046307748381 ps
CPU time 810.46 seconds
Started Jul 23 07:01:00 PM PDT 24
Finished Jul 23 07:14:32 PM PDT 24
Peak memory 210256 kb
Host smart-3e1652c3-29a4-474d-b3ab-43abec97be3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617940560 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2617940560
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2357945207
Short name T287
Test name
Test status
Simulation time 496716254418 ps
CPU time 1191.06 seconds
Started Jul 23 07:01:28 PM PDT 24
Finished Jul 23 07:21:21 PM PDT 24
Peak memory 201256 kb
Host smart-503e1369-ca44-444b-8b91-5364a9b95d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357945207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2357945207
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.4110253365
Short name T259
Test name
Test status
Simulation time 536660124830 ps
CPU time 1251.5 seconds
Started Jul 23 06:59:56 PM PDT 24
Finished Jul 23 07:20:52 PM PDT 24
Peak memory 201252 kb
Host smart-ea68df0e-9109-4e37-829f-597f99445b04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110253365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.4110253365
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2969455595
Short name T298
Test name
Test status
Simulation time 330267490728 ps
CPU time 750.28 seconds
Started Jul 23 07:00:37 PM PDT 24
Finished Jul 23 07:13:09 PM PDT 24
Peak memory 201240 kb
Host smart-29c326f9-9326-4ce1-accc-a5a6ff6f9da3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969455595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2969455595
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4191787727
Short name T3
Test name
Test status
Simulation time 334268176025 ps
CPU time 235.98 seconds
Started Jul 23 07:01:29 PM PDT 24
Finished Jul 23 07:05:26 PM PDT 24
Peak memory 201240 kb
Host smart-9a5dba5b-bcff-4c0d-a163-37bdd8ee1e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191787727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4191787727
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.260911689
Short name T237
Test name
Test status
Simulation time 194528832312 ps
CPU time 81.79 seconds
Started Jul 23 07:00:43 PM PDT 24
Finished Jul 23 07:02:06 PM PDT 24
Peak memory 201220 kb
Host smart-9a3f914e-922d-492a-9806-1ba3ee16c6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260911689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.260911689
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.45847708
Short name T266
Test name
Test status
Simulation time 493165029301 ps
CPU time 1188.02 seconds
Started Jul 23 07:02:42 PM PDT 24
Finished Jul 23 07:22:30 PM PDT 24
Peak memory 201232 kb
Host smart-f04b84b2-8336-4725-80e5-c4f169974b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45847708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.45847708
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1518775071
Short name T222
Test name
Test status
Simulation time 518797305664 ps
CPU time 261.83 seconds
Started Jul 23 07:03:22 PM PDT 24
Finished Jul 23 07:07:45 PM PDT 24
Peak memory 201240 kb
Host smart-38749239-006d-4fe8-a655-ab846b1eadf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518775071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1518775071
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3497119249
Short name T261
Test name
Test status
Simulation time 333887906719 ps
CPU time 730.08 seconds
Started Jul 23 07:00:39 PM PDT 24
Finished Jul 23 07:12:51 PM PDT 24
Peak memory 201172 kb
Host smart-0900a438-7b60-4e0b-97ee-f6be8cf916df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497119249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3497119249
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1979415837
Short name T249
Test name
Test status
Simulation time 342295019503 ps
CPU time 409.91 seconds
Started Jul 23 07:03:06 PM PDT 24
Finished Jul 23 07:09:57 PM PDT 24
Peak memory 201152 kb
Host smart-f1e7396d-67c9-4685-9dff-fa333fc2ce2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979415837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1979415837
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.459491023
Short name T272
Test name
Test status
Simulation time 530827962561 ps
CPU time 186.68 seconds
Started Jul 23 07:00:35 PM PDT 24
Finished Jul 23 07:03:43 PM PDT 24
Peak memory 201276 kb
Host smart-554f5675-a93d-446c-b723-f38a15ccad41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459491023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.459491023
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2011598590
Short name T162
Test name
Test status
Simulation time 485078033430 ps
CPU time 1051.75 seconds
Started Jul 23 06:59:50 PM PDT 24
Finished Jul 23 07:17:29 PM PDT 24
Peak memory 201292 kb
Host smart-d3dcdff0-7ab2-41ff-a399-c703deb40577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011598590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2011598590
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.362600248
Short name T215
Test name
Test status
Simulation time 969613028960 ps
CPU time 1406.98 seconds
Started Jul 23 07:00:07 PM PDT 24
Finished Jul 23 07:23:36 PM PDT 24
Peak memory 209848 kb
Host smart-1bc89051-62eb-4759-8e8d-1823a2cb02d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362600248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.362600248
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1214559423
Short name T248
Test name
Test status
Simulation time 533760953473 ps
CPU time 331.48 seconds
Started Jul 23 07:00:57 PM PDT 24
Finished Jul 23 07:06:31 PM PDT 24
Peak memory 201304 kb
Host smart-d3ac3bfb-a2ea-4d36-91c8-f8f2739376e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214559423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1214559423
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.816464519
Short name T278
Test name
Test status
Simulation time 547813530591 ps
CPU time 1195.13 seconds
Started Jul 23 07:03:30 PM PDT 24
Finished Jul 23 07:23:26 PM PDT 24
Peak memory 201248 kb
Host smart-277e1905-cf5a-4062-84fa-46fc94d20336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816464519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.816464519
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.546306779
Short name T193
Test name
Test status
Simulation time 523760034197 ps
CPU time 71.2 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:01:53 PM PDT 24
Peak memory 201152 kb
Host smart-2b0865ad-a6d9-4aa1-8d1c-630623e6fb78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546306779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.546306779
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3682703922
Short name T201
Test name
Test status
Simulation time 556714901589 ps
CPU time 324.9 seconds
Started Jul 23 07:00:51 PM PDT 24
Finished Jul 23 07:06:18 PM PDT 24
Peak memory 201244 kb
Host smart-7b71b7c3-029c-4f3a-abab-4eaada8f0d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682703922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3682703922
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.4011945193
Short name T304
Test name
Test status
Simulation time 164327856692 ps
CPU time 132 seconds
Started Jul 23 07:02:53 PM PDT 24
Finished Jul 23 07:05:06 PM PDT 24
Peak memory 201240 kb
Host smart-41baa507-4d8f-4286-b74f-d1a19118c499
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011945193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.4011945193
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.543843669
Short name T345
Test name
Test status
Simulation time 235538858948 ps
CPU time 746.68 seconds
Started Jul 23 07:00:38 PM PDT 24
Finished Jul 23 07:13:06 PM PDT 24
Peak memory 201608 kb
Host smart-6c5fb8ee-89a1-4305-bbd6-19fc5803537f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543843669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.543843669
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.551305197
Short name T220
Test name
Test status
Simulation time 525663687704 ps
CPU time 1502.56 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:25:57 PM PDT 24
Peak memory 209880 kb
Host smart-7f31a56b-a45b-4a28-950b-0f50670c5bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551305197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
551305197
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3620662513
Short name T291
Test name
Test status
Simulation time 166053210095 ps
CPU time 185.37 seconds
Started Jul 23 07:01:03 PM PDT 24
Finished Jul 23 07:04:09 PM PDT 24
Peak memory 201132 kb
Host smart-53547a2c-5899-4219-bcc5-4820c3d76b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620662513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3620662513
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.257955025
Short name T307
Test name
Test status
Simulation time 358047365336 ps
CPU time 64.16 seconds
Started Jul 23 07:01:41 PM PDT 24
Finished Jul 23 07:02:46 PM PDT 24
Peak memory 201352 kb
Host smart-8f599e97-5302-464e-a8a8-3be3e1374d0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257955025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.257955025
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3545386464
Short name T302
Test name
Test status
Simulation time 176717721643 ps
CPU time 90.24 seconds
Started Jul 23 07:02:08 PM PDT 24
Finished Jul 23 07:03:40 PM PDT 24
Peak memory 201064 kb
Host smart-69e7d5c3-97be-4eba-b8c1-28466b631e89
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545386464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3545386464
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3604661426
Short name T240
Test name
Test status
Simulation time 560690744105 ps
CPU time 111.77 seconds
Started Jul 23 07:02:41 PM PDT 24
Finished Jul 23 07:04:33 PM PDT 24
Peak memory 201232 kb
Host smart-e9589143-d541-4caf-b64d-e2fa1adfe8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604661426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3604661426
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1740678842
Short name T851
Test name
Test status
Simulation time 601151249 ps
CPU time 1.94 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 201872 kb
Host smart-edaeb0e0-44c5-491e-9589-b5b0b8526dc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740678842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1740678842
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3506736913
Short name T300
Test name
Test status
Simulation time 676205782425 ps
CPU time 704.85 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:12:28 PM PDT 24
Peak memory 201212 kb
Host smart-6b08118a-83b0-4640-8c01-f4a536515e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506736913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3506736913
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1800110640
Short name T267
Test name
Test status
Simulation time 387906397940 ps
CPU time 417.51 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:07:55 PM PDT 24
Peak memory 201196 kb
Host smart-12953fbf-4685-48ca-b67b-b485d0c73b73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800110640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1800110640
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1484983194
Short name T235
Test name
Test status
Simulation time 329348261537 ps
CPU time 782.02 seconds
Started Jul 23 07:00:51 PM PDT 24
Finished Jul 23 07:13:54 PM PDT 24
Peak memory 201312 kb
Host smart-3bf36d54-0156-4b33-bfc5-7fcd9dde4034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484983194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1484983194
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3114773233
Short name T200
Test name
Test status
Simulation time 353938367451 ps
CPU time 774.92 seconds
Started Jul 23 07:01:56 PM PDT 24
Finished Jul 23 07:14:52 PM PDT 24
Peak memory 201236 kb
Host smart-b5237484-d213-4e05-acdf-310a83b0da4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114773233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3114773233
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2202332190
Short name T254
Test name
Test status
Simulation time 170481288780 ps
CPU time 368.32 seconds
Started Jul 23 07:02:50 PM PDT 24
Finished Jul 23 07:08:59 PM PDT 24
Peak memory 201304 kb
Host smart-127d36e4-48cd-4dc3-889f-8b37eae6f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202332190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2202332190
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2048867667
Short name T96
Test name
Test status
Simulation time 327245364815 ps
CPU time 109.28 seconds
Started Jul 23 07:00:32 PM PDT 24
Finished Jul 23 07:02:22 PM PDT 24
Peak memory 201172 kb
Host smart-552b4839-3745-4baf-a38a-ca7fce8c0602
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048867667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2048867667
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1729192556
Short name T321
Test name
Test status
Simulation time 161455193865 ps
CPU time 132.15 seconds
Started Jul 23 06:59:50 PM PDT 24
Finished Jul 23 07:02:09 PM PDT 24
Peak memory 218040 kb
Host smart-c925a1ac-812b-4aaf-a1cf-4dc8ecb58be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729192556 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1729192556
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3129727417
Short name T277
Test name
Test status
Simulation time 336355956745 ps
CPU time 353.92 seconds
Started Jul 23 07:00:49 PM PDT 24
Finished Jul 23 07:06:45 PM PDT 24
Peak memory 201236 kb
Host smart-a62ccab8-7094-454b-9593-b1a79ea0044b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129727417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3129727417
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1372422869
Short name T354
Test name
Test status
Simulation time 93808482129 ps
CPU time 322.45 seconds
Started Jul 23 07:01:08 PM PDT 24
Finished Jul 23 07:06:33 PM PDT 24
Peak memory 201664 kb
Host smart-9288bf05-93d8-4c03-8721-8663a265fe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372422869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1372422869
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.140454709
Short name T196
Test name
Test status
Simulation time 320824349433 ps
CPU time 166.15 seconds
Started Jul 23 07:01:20 PM PDT 24
Finished Jul 23 07:04:07 PM PDT 24
Peak memory 201204 kb
Host smart-3f36ed80-2916-4a8b-8d4e-41577f0ce989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140454709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.140454709
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1313385845
Short name T322
Test name
Test status
Simulation time 326134478920 ps
CPU time 727.31 seconds
Started Jul 23 06:59:59 PM PDT 24
Finished Jul 23 07:12:09 PM PDT 24
Peak memory 201228 kb
Host smart-934df946-9f92-4a7c-9e37-80856ae92d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313385845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1313385845
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3918128120
Short name T263
Test name
Test status
Simulation time 161361468139 ps
CPU time 354.15 seconds
Started Jul 23 07:02:16 PM PDT 24
Finished Jul 23 07:08:11 PM PDT 24
Peak memory 201240 kb
Host smart-991bbb9b-b648-4e64-9c49-460b8b9ab2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918128120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3918128120
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3140452641
Short name T315
Test name
Test status
Simulation time 325502754887 ps
CPU time 199.89 seconds
Started Jul 23 07:02:47 PM PDT 24
Finished Jul 23 07:06:07 PM PDT 24
Peak memory 201296 kb
Host smart-05e02f24-b3c8-4ed2-8b18-80094d3afd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140452641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3140452641
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3301064
Short name T219
Test name
Test status
Simulation time 118902096994 ps
CPU time 339.02 seconds
Started Jul 23 07:03:12 PM PDT 24
Finished Jul 23 07:08:52 PM PDT 24
Peak memory 201672 kb
Host smart-71747d6f-0a9e-459f-89ed-4fec902b6a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3301064
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.346161157
Short name T346
Test name
Test status
Simulation time 4291652411 ps
CPU time 11.35 seconds
Started Jul 23 05:43:02 PM PDT 24
Finished Jul 23 05:43:16 PM PDT 24
Peak memory 201828 kb
Host smart-ad348664-e074-42d1-ad61-432e10169640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346161157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.346161157
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2851071518
Short name T213
Test name
Test status
Simulation time 119314973107 ps
CPU time 675.08 seconds
Started Jul 23 06:59:55 PM PDT 24
Finished Jul 23 07:11:15 PM PDT 24
Peak memory 201632 kb
Host smart-d81f4297-cf70-4e27-818c-e1892e49e2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851071518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2851071518
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.165819048
Short name T288
Test name
Test status
Simulation time 172892836583 ps
CPU time 185.87 seconds
Started Jul 23 07:00:43 PM PDT 24
Finished Jul 23 07:03:50 PM PDT 24
Peak memory 201240 kb
Host smart-71610372-4226-4076-a0b4-4c819d2f9eff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165819048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.165819048
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.580236210
Short name T216
Test name
Test status
Simulation time 85021043132 ps
CPU time 336.23 seconds
Started Jul 23 07:00:55 PM PDT 24
Finished Jul 23 07:06:35 PM PDT 24
Peak memory 201656 kb
Host smart-8710872b-e6dc-445c-b703-735cea0fc5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580236210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.580236210
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3493602464
Short name T324
Test name
Test status
Simulation time 537520490178 ps
CPU time 294.87 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:05:52 PM PDT 24
Peak memory 201216 kb
Host smart-4af592ff-b248-488e-8a30-32eb8a779148
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493602464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3493602464
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1819931156
Short name T350
Test name
Test status
Simulation time 81887749028 ps
CPU time 254.65 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:05:13 PM PDT 24
Peak memory 201724 kb
Host smart-ec62fadb-a9f2-465f-b5da-64ebd976eb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819931156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1819931156
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2417140532
Short name T709
Test name
Test status
Simulation time 559266041743 ps
CPU time 1228.17 seconds
Started Jul 23 07:01:03 PM PDT 24
Finished Jul 23 07:21:32 PM PDT 24
Peak memory 201168 kb
Host smart-1adab2fa-c995-4884-8f23-ce4025daeeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417140532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2417140532
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1146911454
Short name T285
Test name
Test status
Simulation time 616395967310 ps
CPU time 543.53 seconds
Started Jul 23 07:01:26 PM PDT 24
Finished Jul 23 07:10:31 PM PDT 24
Peak memory 209868 kb
Host smart-7875e416-3a2d-4787-bfe4-c25011bccd07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146911454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1146911454
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2046762961
Short name T176
Test name
Test status
Simulation time 526772899917 ps
CPU time 129.14 seconds
Started Jul 23 07:02:06 PM PDT 24
Finished Jul 23 07:04:16 PM PDT 24
Peak memory 201376 kb
Host smart-a11c68c5-1a37-4ae5-9c1a-f6097784d9e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046762961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2046762961
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2774178740
Short name T238
Test name
Test status
Simulation time 54545303251 ps
CPU time 37.16 seconds
Started Jul 23 07:02:11 PM PDT 24
Finished Jul 23 07:02:50 PM PDT 24
Peak memory 209556 kb
Host smart-3ed08815-d47f-4b92-b502-fd6254974f0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774178740 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2774178740
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2180129316
Short name T318
Test name
Test status
Simulation time 487473527910 ps
CPU time 296.45 seconds
Started Jul 23 07:02:13 PM PDT 24
Finished Jul 23 07:07:11 PM PDT 24
Peak memory 201248 kb
Host smart-cd9c70ee-2012-4f14-aba8-6c831752db6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180129316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2180129316
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3805324424
Short name T163
Test name
Test status
Simulation time 350069799675 ps
CPU time 96.21 seconds
Started Jul 23 07:02:59 PM PDT 24
Finished Jul 23 07:04:35 PM PDT 24
Peak memory 201248 kb
Host smart-3c9314be-9006-4cd5-89fe-438a8d0f7f8a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805324424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3805324424
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.878892549
Short name T37
Test name
Test status
Simulation time 492612532393 ps
CPU time 1109.94 seconds
Started Jul 23 07:03:28 PM PDT 24
Finished Jul 23 07:21:58 PM PDT 24
Peak memory 201256 kb
Host smart-ecc62673-8a99-423e-9f20-85e65221a06f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878892549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.878892549
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1859561395
Short name T310
Test name
Test status
Simulation time 235547585592 ps
CPU time 529.16 seconds
Started Jul 23 07:00:22 PM PDT 24
Finished Jul 23 07:09:13 PM PDT 24
Peak memory 201224 kb
Host smart-2ece0bc4-d629-4c98-be24-637e5f0c5879
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859561395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1859561395
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2591365122
Short name T916
Test name
Test status
Simulation time 1169559863 ps
CPU time 4.6 seconds
Started Jul 23 05:43:04 PM PDT 24
Finished Jul 23 05:43:10 PM PDT 24
Peak memory 201572 kb
Host smart-e710770a-ebcb-4cd4-bbff-7c0ee128b5f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591365122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2591365122
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1642138646
Short name T918
Test name
Test status
Simulation time 7580384862 ps
CPU time 9.46 seconds
Started Jul 23 05:43:02 PM PDT 24
Finished Jul 23 05:43:13 PM PDT 24
Peak memory 201624 kb
Host smart-8d863e0f-b748-4447-b576-87bdcda62bee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642138646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1642138646
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.407197355
Short name T867
Test name
Test status
Simulation time 856515752 ps
CPU time 1.44 seconds
Started Jul 23 05:43:03 PM PDT 24
Finished Jul 23 05:43:06 PM PDT 24
Peak memory 201432 kb
Host smart-13fba7a0-0534-4201-b0c9-f304abebbee0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407197355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.407197355
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1685498515
Short name T804
Test name
Test status
Simulation time 402464638 ps
CPU time 1.8 seconds
Started Jul 23 05:43:08 PM PDT 24
Finished Jul 23 05:43:10 PM PDT 24
Peak memory 201476 kb
Host smart-3fe4430a-92d7-45d2-bb38-c6a1993815f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685498515 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1685498515
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.75271105
Short name T109
Test name
Test status
Simulation time 306456149 ps
CPU time 1.36 seconds
Started Jul 23 05:43:08 PM PDT 24
Finished Jul 23 05:43:10 PM PDT 24
Peak memory 201348 kb
Host smart-0bb0617f-8dfc-435d-a43f-fe46f4fadeda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75271105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.75271105
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.826289335
Short name T807
Test name
Test status
Simulation time 499140950 ps
CPU time 1.73 seconds
Started Jul 23 05:43:00 PM PDT 24
Finished Jul 23 05:43:02 PM PDT 24
Peak memory 201468 kb
Host smart-149617f6-13f3-4575-b730-706c7e5a85ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826289335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.826289335
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1281851706
Short name T842
Test name
Test status
Simulation time 2001723896 ps
CPU time 1.64 seconds
Started Jul 23 05:43:00 PM PDT 24
Finished Jul 23 05:43:02 PM PDT 24
Peak memory 201428 kb
Host smart-a3d3caa1-fe41-4322-9f43-a843a931b616
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281851706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1281851706
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3385906128
Short name T122
Test name
Test status
Simulation time 1003976584 ps
CPU time 2.76 seconds
Started Jul 23 05:43:09 PM PDT 24
Finished Jul 23 05:43:14 PM PDT 24
Peak memory 201640 kb
Host smart-b36fec8d-c990-4c8c-a514-8ffb49fbc64b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385906128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3385906128
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3111926421
Short name T899
Test name
Test status
Simulation time 27051409889 ps
CPU time 28.4 seconds
Started Jul 23 05:43:08 PM PDT 24
Finished Jul 23 05:43:37 PM PDT 24
Peak memory 201692 kb
Host smart-ddca6c4a-f4ef-469d-85ef-d29739a4ed3a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111926421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3111926421
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3340735339
Short name T107
Test name
Test status
Simulation time 815572085 ps
CPU time 2.62 seconds
Started Jul 23 05:43:02 PM PDT 24
Finished Jul 23 05:43:06 PM PDT 24
Peak memory 201304 kb
Host smart-f56d0421-98fd-4727-a149-7d0ffae075b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340735339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3340735339
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2108663789
Short name T813
Test name
Test status
Simulation time 388199336 ps
CPU time 1 seconds
Started Jul 23 05:43:10 PM PDT 24
Finished Jul 23 05:43:12 PM PDT 24
Peak memory 201592 kb
Host smart-98fcdf54-a986-45c0-8557-6c8cf4b15cd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108663789 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2108663789
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.127671469
Short name T117
Test name
Test status
Simulation time 397956700 ps
CPU time 1.3 seconds
Started Jul 23 05:43:10 PM PDT 24
Finished Jul 23 05:43:13 PM PDT 24
Peak memory 201428 kb
Host smart-3e8f2ab0-bbc1-4bd0-812b-51c0bf8bbf18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127671469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.127671469
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3967392378
Short name T850
Test name
Test status
Simulation time 440461800 ps
CPU time 0.85 seconds
Started Jul 23 05:43:01 PM PDT 24
Finished Jul 23 05:43:03 PM PDT 24
Peak memory 201368 kb
Host smart-20be4ec1-5493-436f-94d5-cd0d26d903d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967392378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3967392378
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.620454649
Short name T829
Test name
Test status
Simulation time 2969087007 ps
CPU time 2.32 seconds
Started Jul 23 05:43:06 PM PDT 24
Finished Jul 23 05:43:09 PM PDT 24
Peak memory 201516 kb
Host smart-1bbffe88-7c7b-4ad0-a978-dc6068fd1b74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620454649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.620454649
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1924518627
Short name T63
Test name
Test status
Simulation time 525658103 ps
CPU time 1.73 seconds
Started Jul 23 05:43:08 PM PDT 24
Finished Jul 23 05:43:10 PM PDT 24
Peak memory 201728 kb
Host smart-47de24a0-140f-4cc2-8a88-6c438b9a7b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924518627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1924518627
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.824453307
Short name T68
Test name
Test status
Simulation time 8301977021 ps
CPU time 6.75 seconds
Started Jul 23 05:43:02 PM PDT 24
Finished Jul 23 05:43:11 PM PDT 24
Peak memory 201748 kb
Host smart-790915c4-6019-4c51-a2bb-daae477fcc12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824453307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.824453307
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2736019936
Short name T876
Test name
Test status
Simulation time 491166189 ps
CPU time 1.24 seconds
Started Jul 23 05:43:27 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 201484 kb
Host smart-06ec2f09-0338-41a5-b808-734a2581002b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736019936 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2736019936
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.24328749
Short name T822
Test name
Test status
Simulation time 509331942 ps
CPU time 1.66 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 201476 kb
Host smart-6c7a370d-137b-4bee-9cd4-9ba136d900c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24328749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.24328749
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.29769243
Short name T827
Test name
Test status
Simulation time 386566446 ps
CPU time 1.56 seconds
Started Jul 23 05:43:25 PM PDT 24
Finished Jul 23 05:43:27 PM PDT 24
Peak memory 201480 kb
Host smart-3a85500e-ebe4-4ccd-bce8-43db23561cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29769243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.29769243
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.487241393
Short name T884
Test name
Test status
Simulation time 4169223313 ps
CPU time 3.38 seconds
Started Jul 23 05:43:25 PM PDT 24
Finished Jul 23 05:43:28 PM PDT 24
Peak memory 201752 kb
Host smart-52bcb456-c5b9-467c-9c5d-659d049a03cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487241393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.487241393
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2690611096
Short name T50
Test name
Test status
Simulation time 4288750421 ps
CPU time 10.21 seconds
Started Jul 23 05:43:25 PM PDT 24
Finished Jul 23 05:43:37 PM PDT 24
Peak memory 201820 kb
Host smart-288fbad2-0184-4d64-89a9-48fafb8f9a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690611096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2690611096
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2603945649
Short name T809
Test name
Test status
Simulation time 809391469 ps
CPU time 1 seconds
Started Jul 23 05:43:27 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 201596 kb
Host smart-73b63936-6032-4beb-91fc-e10e8184282d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603945649 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2603945649
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.752935494
Short name T895
Test name
Test status
Simulation time 390449788 ps
CPU time 1.5 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 201444 kb
Host smart-08f66137-9852-4e5d-820b-43eaac974fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752935494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.752935494
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1043083030
Short name T913
Test name
Test status
Simulation time 2823461930 ps
CPU time 7 seconds
Started Jul 23 05:43:27 PM PDT 24
Finished Jul 23 05:43:36 PM PDT 24
Peak memory 201496 kb
Host smart-c071fd62-8ab7-4dea-b7db-e42376bb99e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043083030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1043083030
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4024853845
Short name T65
Test name
Test status
Simulation time 689168050 ps
CPU time 1.93 seconds
Started Jul 23 05:43:29 PM PDT 24
Finished Jul 23 05:43:32 PM PDT 24
Peak memory 201772 kb
Host smart-471e30d8-645f-43fd-ad54-3594f8d350f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024853845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.4024853845
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.862008151
Short name T49
Test name
Test status
Simulation time 8661440770 ps
CPU time 17.43 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:45 PM PDT 24
Peak memory 201752 kb
Host smart-12e57757-d547-4960-8f6b-1015d622dba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862008151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.862008151
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2753179244
Short name T848
Test name
Test status
Simulation time 468924749 ps
CPU time 1.94 seconds
Started Jul 23 05:43:25 PM PDT 24
Finished Jul 23 05:43:28 PM PDT 24
Peak memory 201524 kb
Host smart-26260f3f-81de-4d0f-ba8e-5aa27b855b52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753179244 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2753179244
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.317195540
Short name T110
Test name
Test status
Simulation time 501368965 ps
CPU time 1 seconds
Started Jul 23 05:43:28 PM PDT 24
Finished Jul 23 05:43:31 PM PDT 24
Peak memory 201444 kb
Host smart-a239c5ba-66eb-4118-9240-8fc025124433
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317195540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.317195540
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.289757313
Short name T852
Test name
Test status
Simulation time 413106503 ps
CPU time 1.1 seconds
Started Jul 23 05:43:28 PM PDT 24
Finished Jul 23 05:43:31 PM PDT 24
Peak memory 201404 kb
Host smart-1b0724a4-8b18-4ff7-88d8-e7a67adaa1ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289757313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.289757313
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3995997844
Short name T48
Test name
Test status
Simulation time 2472998198 ps
CPU time 1.27 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 201588 kb
Host smart-598d8ed0-5990-4f81-a9c5-55884a5fc49e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995997844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3995997844
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4065798755
Short name T844
Test name
Test status
Simulation time 462395871 ps
CPU time 3.1 seconds
Started Jul 23 05:43:27 PM PDT 24
Finished Jul 23 05:43:31 PM PDT 24
Peak memory 209812 kb
Host smart-aaecac5a-6330-4406-a91a-84830ab40eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065798755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4065798755
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2809195068
Short name T864
Test name
Test status
Simulation time 4110650594 ps
CPU time 3.81 seconds
Started Jul 23 05:43:28 PM PDT 24
Finished Jul 23 05:43:34 PM PDT 24
Peak memory 201840 kb
Host smart-810f185b-8dce-490a-bc7f-d691be1907d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809195068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2809195068
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3866035230
Short name T872
Test name
Test status
Simulation time 359464205 ps
CPU time 1.17 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 201632 kb
Host smart-3c43980a-6cfa-4243-affd-ad956e959b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866035230 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3866035230
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3918966512
Short name T874
Test name
Test status
Simulation time 561280593 ps
CPU time 1.07 seconds
Started Jul 23 05:43:27 PM PDT 24
Finished Jul 23 05:43:30 PM PDT 24
Peak memory 201448 kb
Host smart-759122c8-9aa4-4d8d-83b6-ed2f673cfe1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918966512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3918966512
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3889459781
Short name T894
Test name
Test status
Simulation time 538017005 ps
CPU time 0.99 seconds
Started Jul 23 05:43:27 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 201448 kb
Host smart-68d85b38-86c7-4e02-ac58-0f932b320cae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889459781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3889459781
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.348492411
Short name T877
Test name
Test status
Simulation time 4297562051 ps
CPU time 7.18 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:35 PM PDT 24
Peak memory 201764 kb
Host smart-16fb231d-7114-4c72-bce8-77107d444f2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348492411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.348492411
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3973232658
Short name T817
Test name
Test status
Simulation time 371092762 ps
CPU time 2.81 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:31 PM PDT 24
Peak memory 201832 kb
Host smart-132d04d4-999f-4290-a345-412bad366f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973232658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3973232658
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.824113789
Short name T883
Test name
Test status
Simulation time 4349545535 ps
CPU time 4.31 seconds
Started Jul 23 05:43:25 PM PDT 24
Finished Jul 23 05:43:31 PM PDT 24
Peak memory 201844 kb
Host smart-8e1d9b8e-c1d3-4a4e-905f-02e36300fd2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824113789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.824113789
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3228655650
Short name T826
Test name
Test status
Simulation time 560655402 ps
CPU time 1.38 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 201492 kb
Host smart-43c19a63-ef50-4010-8ee0-965ef102fe4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228655650 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3228655650
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.568399299
Short name T856
Test name
Test status
Simulation time 529563053 ps
CPU time 0.94 seconds
Started Jul 23 05:43:25 PM PDT 24
Finished Jul 23 05:43:27 PM PDT 24
Peak memory 201400 kb
Host smart-4d5b6be4-83a6-4c52-9ae4-847a8fcc130c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568399299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.568399299
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3717479922
Short name T907
Test name
Test status
Simulation time 513891116 ps
CPU time 1.72 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 201360 kb
Host smart-5ae24224-dac2-4cbc-baa9-8a9804158d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717479922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3717479922
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1120016475
Short name T46
Test name
Test status
Simulation time 4947228267 ps
CPU time 3.83 seconds
Started Jul 23 05:43:25 PM PDT 24
Finished Jul 23 05:43:30 PM PDT 24
Peak memory 201712 kb
Host smart-4494c9a0-ebbb-4a95-a5ff-70ee84d40962
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120016475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1120016475
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1460401103
Short name T912
Test name
Test status
Simulation time 896908237 ps
CPU time 2.66 seconds
Started Jul 23 05:43:25 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 218136 kb
Host smart-1b53c700-89fa-481b-ba2d-f943a45deb05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460401103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1460401103
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1215379576
Short name T816
Test name
Test status
Simulation time 4877346095 ps
CPU time 12.26 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:39 PM PDT 24
Peak memory 201704 kb
Host smart-353a7d35-3157-4032-b2c7-9dc220aa4e04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215379576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1215379576
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1547803487
Short name T901
Test name
Test status
Simulation time 927899577 ps
CPU time 1.22 seconds
Started Jul 23 05:43:34 PM PDT 24
Finished Jul 23 05:43:35 PM PDT 24
Peak memory 209728 kb
Host smart-be6ec5ec-5036-453c-9a57-4108848fc8e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547803487 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1547803487
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2636026280
Short name T819
Test name
Test status
Simulation time 539293207 ps
CPU time 1.08 seconds
Started Jul 23 05:43:34 PM PDT 24
Finished Jul 23 05:43:36 PM PDT 24
Peak memory 201436 kb
Host smart-6fe277ae-00ad-49d4-8904-5ce8c15a1d30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636026280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2636026280
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2639656479
Short name T888
Test name
Test status
Simulation time 394518868 ps
CPU time 0.94 seconds
Started Jul 23 05:43:28 PM PDT 24
Finished Jul 23 05:43:31 PM PDT 24
Peak memory 201408 kb
Host smart-66da3872-50c8-44e3-8792-ff6a6362d722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639656479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2639656479
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2544519772
Short name T862
Test name
Test status
Simulation time 4386868580 ps
CPU time 10.51 seconds
Started Jul 23 05:43:33 PM PDT 24
Finished Jul 23 05:43:44 PM PDT 24
Peak memory 201816 kb
Host smart-48a848a3-5bc5-469c-bfd0-15554ec9e733
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544519772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2544519772
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1044333723
Short name T886
Test name
Test status
Simulation time 468334080 ps
CPU time 2.25 seconds
Started Jul 23 05:43:26 PM PDT 24
Finished Jul 23 05:43:29 PM PDT 24
Peak memory 201712 kb
Host smart-dfa0ab39-f433-4dbc-94e3-c7a31da4be2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044333723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1044333723
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2844780064
Short name T869
Test name
Test status
Simulation time 8415098519 ps
CPU time 22.33 seconds
Started Jul 23 05:43:27 PM PDT 24
Finished Jul 23 05:43:51 PM PDT 24
Peak memory 201704 kb
Host smart-0c58679b-fab6-4abe-8d2c-eeca2d970d28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844780064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2844780064
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.183705999
Short name T58
Test name
Test status
Simulation time 534551205 ps
CPU time 1.49 seconds
Started Jul 23 05:43:33 PM PDT 24
Finished Jul 23 05:43:35 PM PDT 24
Peak memory 201500 kb
Host smart-f55abdca-d1ab-4b29-9095-8511405ac1f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183705999 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.183705999
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1002846141
Short name T904
Test name
Test status
Simulation time 529422247 ps
CPU time 0.82 seconds
Started Jul 23 05:43:37 PM PDT 24
Finished Jul 23 05:43:38 PM PDT 24
Peak memory 201436 kb
Host smart-32a16f47-600d-4663-8bba-c39fbe57ecf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002846141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1002846141
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3563517652
Short name T814
Test name
Test status
Simulation time 489167097 ps
CPU time 0.99 seconds
Started Jul 23 05:43:34 PM PDT 24
Finished Jul 23 05:43:36 PM PDT 24
Peak memory 201420 kb
Host smart-27df061a-cfa1-4d78-94a7-47f376830a9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563517652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3563517652
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2233214118
Short name T868
Test name
Test status
Simulation time 2535521013 ps
CPU time 5.3 seconds
Started Jul 23 05:43:39 PM PDT 24
Finished Jul 23 05:43:45 PM PDT 24
Peak memory 201532 kb
Host smart-66e24ee2-d888-40d0-ac14-8d5bb4a9b487
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233214118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2233214118
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1141877507
Short name T871
Test name
Test status
Simulation time 580047265 ps
CPU time 2.73 seconds
Started Jul 23 05:43:35 PM PDT 24
Finished Jul 23 05:43:39 PM PDT 24
Peak memory 201776 kb
Host smart-66a3a98b-faa5-45e4-87be-ee0026425b89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141877507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1141877507
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.338319182
Short name T896
Test name
Test status
Simulation time 4466933310 ps
CPU time 11.06 seconds
Started Jul 23 05:43:34 PM PDT 24
Finished Jul 23 05:43:45 PM PDT 24
Peak memory 201772 kb
Host smart-e8a569c2-e845-4c54-a339-fe71509901f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338319182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.338319182
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.119576622
Short name T815
Test name
Test status
Simulation time 411813891 ps
CPU time 1.41 seconds
Started Jul 23 05:43:35 PM PDT 24
Finished Jul 23 05:43:38 PM PDT 24
Peak memory 201572 kb
Host smart-7e0764b8-a0b6-47e0-a557-67c4d67fb137
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119576622 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.119576622
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.910243778
Short name T878
Test name
Test status
Simulation time 438259048 ps
CPU time 1.08 seconds
Started Jul 23 05:43:35 PM PDT 24
Finished Jul 23 05:43:37 PM PDT 24
Peak memory 201400 kb
Host smart-e58b1a4f-7a02-41e0-bf41-7eac3570753c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910243778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.910243778
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2918994610
Short name T799
Test name
Test status
Simulation time 313619014 ps
CPU time 0.96 seconds
Started Jul 23 05:43:35 PM PDT 24
Finished Jul 23 05:43:38 PM PDT 24
Peak memory 201360 kb
Host smart-85c1304c-e7eb-4369-8ba3-4c1497a2497a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918994610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2918994610
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1671082021
Short name T830
Test name
Test status
Simulation time 2220555763 ps
CPU time 8.63 seconds
Started Jul 23 05:43:36 PM PDT 24
Finished Jul 23 05:43:45 PM PDT 24
Peak memory 201504 kb
Host smart-5baa5c69-8eab-4d69-abae-5f4ddc2c822e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671082021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1671082021
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1899776951
Short name T861
Test name
Test status
Simulation time 764059027 ps
CPU time 1.98 seconds
Started Jul 23 05:43:39 PM PDT 24
Finished Jul 23 05:43:42 PM PDT 24
Peak memory 201720 kb
Host smart-f9471841-44da-47e4-ad28-2f39096e5fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899776951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1899776951
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.993279403
Short name T67
Test name
Test status
Simulation time 8719242545 ps
CPU time 21.59 seconds
Started Jul 23 05:43:36 PM PDT 24
Finished Jul 23 05:43:58 PM PDT 24
Peak memory 201704 kb
Host smart-bf5989d8-7539-4c0c-adad-298ffe06b6dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993279403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.993279403
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2967274207
Short name T854
Test name
Test status
Simulation time 388499436 ps
CPU time 1.41 seconds
Started Jul 23 05:43:39 PM PDT 24
Finished Jul 23 05:43:42 PM PDT 24
Peak memory 201552 kb
Host smart-18444106-fb88-42f5-b00a-4c3d9120f7e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967274207 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2967274207
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3305025227
Short name T106
Test name
Test status
Simulation time 418626226 ps
CPU time 1.06 seconds
Started Jul 23 05:43:34 PM PDT 24
Finished Jul 23 05:43:36 PM PDT 24
Peak memory 201440 kb
Host smart-4cc98730-4e7e-4601-b54d-1a4d4f0c6851
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305025227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3305025227
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.35950714
Short name T805
Test name
Test status
Simulation time 458193108 ps
CPU time 1.69 seconds
Started Jul 23 05:43:34 PM PDT 24
Finished Jul 23 05:43:37 PM PDT 24
Peak memory 201456 kb
Host smart-d0d3d6a0-a943-4af8-9680-42cde53f70a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35950714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.35950714
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.420504574
Short name T843
Test name
Test status
Simulation time 1930171522 ps
CPU time 1.64 seconds
Started Jul 23 05:43:34 PM PDT 24
Finished Jul 23 05:43:37 PM PDT 24
Peak memory 201464 kb
Host smart-990350cc-5d33-49ea-96cf-9f7c5134b9fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420504574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.420504574
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3429498565
Short name T62
Test name
Test status
Simulation time 552939878 ps
CPU time 2.21 seconds
Started Jul 23 05:43:31 PM PDT 24
Finished Jul 23 05:43:34 PM PDT 24
Peak memory 217524 kb
Host smart-adeea7d4-aeb4-4022-ae42-66b9e443d53f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429498565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3429498565
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.192075765
Short name T51
Test name
Test status
Simulation time 8322399341 ps
CPU time 20.58 seconds
Started Jul 23 05:43:32 PM PDT 24
Finished Jul 23 05:43:53 PM PDT 24
Peak memory 201828 kb
Host smart-40e12f88-fde0-4a63-84f5-729bcf3dbdba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192075765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.192075765
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1869999081
Short name T887
Test name
Test status
Simulation time 414605288 ps
CPU time 1.36 seconds
Started Jul 23 05:43:42 PM PDT 24
Finished Jul 23 05:43:45 PM PDT 24
Peak memory 201600 kb
Host smart-d8988784-919e-4935-b091-10e1a225cf48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869999081 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1869999081
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3379776208
Short name T118
Test name
Test status
Simulation time 314331287 ps
CPU time 1.43 seconds
Started Jul 23 05:43:41 PM PDT 24
Finished Jul 23 05:43:43 PM PDT 24
Peak memory 201448 kb
Host smart-8e3f9934-0a30-4d36-8ac9-41bf3c2e5a92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379776208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3379776208
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.361991145
Short name T834
Test name
Test status
Simulation time 526878746 ps
CPU time 0.79 seconds
Started Jul 23 05:43:39 PM PDT 24
Finished Jul 23 05:43:40 PM PDT 24
Peak memory 201400 kb
Host smart-e9f67833-2d49-4002-a4ef-18b96c3af8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361991145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.361991145
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3670619899
Short name T875
Test name
Test status
Simulation time 2488371114 ps
CPU time 7.8 seconds
Started Jul 23 05:43:41 PM PDT 24
Finished Jul 23 05:43:50 PM PDT 24
Peak memory 201568 kb
Host smart-f4171e20-5737-4c4b-81c3-38dbb5fa6c6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670619899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3670619899
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1340079246
Short name T57
Test name
Test status
Simulation time 375394129 ps
CPU time 3.65 seconds
Started Jul 23 05:43:36 PM PDT 24
Finished Jul 23 05:43:40 PM PDT 24
Peak memory 201816 kb
Host smart-132967d7-5dcb-44a5-aed4-3f7cd294bbbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340079246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1340079246
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.633082596
Short name T890
Test name
Test status
Simulation time 4102441068 ps
CPU time 6.31 seconds
Started Jul 23 05:43:34 PM PDT 24
Finished Jul 23 05:43:42 PM PDT 24
Peak memory 201816 kb
Host smart-3898c9f7-4c1b-48ab-8ea5-8f6d3c1af7a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633082596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.633082596
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1822317918
Short name T111
Test name
Test status
Simulation time 1255136786 ps
CPU time 2.91 seconds
Started Jul 23 05:43:08 PM PDT 24
Finished Jul 23 05:43:11 PM PDT 24
Peak memory 201672 kb
Host smart-edb597d0-2ea6-49df-89bd-5b10fb31d4e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822317918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1822317918
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3595590903
Short name T116
Test name
Test status
Simulation time 1003173707 ps
CPU time 1.29 seconds
Started Jul 23 05:43:13 PM PDT 24
Finished Jul 23 05:43:15 PM PDT 24
Peak memory 201488 kb
Host smart-39b5c12f-68fa-474e-9e74-a9a8890230fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595590903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3595590903
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1790381316
Short name T846
Test name
Test status
Simulation time 417542770 ps
CPU time 1.28 seconds
Started Jul 23 05:43:09 PM PDT 24
Finished Jul 23 05:43:12 PM PDT 24
Peak memory 201472 kb
Host smart-605aba9d-ff4e-4652-ae01-031851620220
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790381316 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1790381316
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.466770429
Short name T879
Test name
Test status
Simulation time 391298766 ps
CPU time 1.67 seconds
Started Jul 23 05:43:11 PM PDT 24
Finished Jul 23 05:43:14 PM PDT 24
Peak memory 201448 kb
Host smart-f5e1c0d8-8990-43e1-ad0a-e25c43d6a6d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466770429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.466770429
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.796832439
Short name T820
Test name
Test status
Simulation time 465061416 ps
CPU time 1.71 seconds
Started Jul 23 05:43:09 PM PDT 24
Finished Jul 23 05:43:13 PM PDT 24
Peak memory 201352 kb
Host smart-49366205-954b-4896-8f7e-831f357e866a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796832439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.796832439
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2722434919
Short name T903
Test name
Test status
Simulation time 2429685384 ps
CPU time 3.2 seconds
Started Jul 23 05:43:09 PM PDT 24
Finished Jul 23 05:43:13 PM PDT 24
Peak memory 201552 kb
Host smart-d8611fa2-4750-4ef2-a1e0-0be9693a4482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722434919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2722434919
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.816185592
Short name T821
Test name
Test status
Simulation time 584634156 ps
CPU time 2.02 seconds
Started Jul 23 05:43:14 PM PDT 24
Finished Jul 23 05:43:17 PM PDT 24
Peak memory 201816 kb
Host smart-861111b6-1ca9-4d29-ba40-78bcddcd4657
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816185592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.816185592
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1404037519
Short name T870
Test name
Test status
Simulation time 4994282709 ps
CPU time 3.21 seconds
Started Jul 23 05:43:10 PM PDT 24
Finished Jul 23 05:43:14 PM PDT 24
Peak memory 201828 kb
Host smart-80ade345-419d-481e-a232-cc1eb38df375
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404037519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1404037519
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2434424054
Short name T865
Test name
Test status
Simulation time 437103005 ps
CPU time 1.54 seconds
Started Jul 23 05:43:42 PM PDT 24
Finished Jul 23 05:43:45 PM PDT 24
Peak memory 201408 kb
Host smart-68cc8e43-09e4-4ff1-8db4-aa7d88bd2f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434424054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2434424054
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2226666860
Short name T917
Test name
Test status
Simulation time 456721787 ps
CPU time 0.96 seconds
Started Jul 23 05:43:41 PM PDT 24
Finished Jul 23 05:43:43 PM PDT 24
Peak memory 201436 kb
Host smart-69326d3d-ed32-4877-8b9f-f4378370d8d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226666860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2226666860
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.759184487
Short name T808
Test name
Test status
Simulation time 531533906 ps
CPU time 0.73 seconds
Started Jul 23 05:43:41 PM PDT 24
Finished Jul 23 05:43:43 PM PDT 24
Peak memory 201356 kb
Host smart-2854f01d-9abe-422b-ab19-181cd5cde2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759184487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.759184487
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2957557205
Short name T797
Test name
Test status
Simulation time 526372432 ps
CPU time 1.72 seconds
Started Jul 23 05:43:42 PM PDT 24
Finished Jul 23 05:43:45 PM PDT 24
Peak memory 201408 kb
Host smart-4379f41c-bd36-4d98-a803-6ca3fafc9ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957557205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2957557205
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4145183226
Short name T885
Test name
Test status
Simulation time 522983295 ps
CPU time 0.93 seconds
Started Jul 23 05:43:41 PM PDT 24
Finished Jul 23 05:43:43 PM PDT 24
Peak memory 201388 kb
Host smart-5480190f-e72d-4274-a3ac-006b9aff99cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145183226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.4145183226
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.554873549
Short name T803
Test name
Test status
Simulation time 337808179 ps
CPU time 0.8 seconds
Started Jul 23 05:43:42 PM PDT 24
Finished Jul 23 05:43:44 PM PDT 24
Peak memory 201452 kb
Host smart-e515e1d0-d1d1-4f3d-a1e1-0b076e10b9ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554873549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.554873549
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.177315735
Short name T800
Test name
Test status
Simulation time 386756399 ps
CPU time 1.18 seconds
Started Jul 23 05:43:44 PM PDT 24
Finished Jul 23 05:43:46 PM PDT 24
Peak memory 201396 kb
Host smart-6283d27c-bc00-47df-aeb1-bc5c4df1b7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177315735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.177315735
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.417061377
Short name T908
Test name
Test status
Simulation time 357059132 ps
CPU time 0.74 seconds
Started Jul 23 05:43:42 PM PDT 24
Finished Jul 23 05:43:44 PM PDT 24
Peak memory 201424 kb
Host smart-60a7d8e1-0ad4-491a-b513-7954bc8287a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417061377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.417061377
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1815484274
Short name T873
Test name
Test status
Simulation time 435071280 ps
CPU time 1.36 seconds
Started Jul 23 05:43:41 PM PDT 24
Finished Jul 23 05:43:43 PM PDT 24
Peak memory 201360 kb
Host smart-4da35215-d133-4582-8aa2-872143cf5f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815484274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1815484274
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1074734865
Short name T832
Test name
Test status
Simulation time 461959414 ps
CPU time 1.17 seconds
Started Jul 23 05:43:42 PM PDT 24
Finished Jul 23 05:43:44 PM PDT 24
Peak memory 201392 kb
Host smart-537bddb5-e889-40fd-a74f-6b2c9f98b320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074734865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1074734865
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2648874111
Short name T115
Test name
Test status
Simulation time 1089075160 ps
CPU time 4.69 seconds
Started Jul 23 05:43:12 PM PDT 24
Finished Jul 23 05:43:17 PM PDT 24
Peak memory 201672 kb
Host smart-7536ca86-4dba-4a1b-91ca-443fc0532aa2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648874111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2648874111
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1058212889
Short name T114
Test name
Test status
Simulation time 20620257881 ps
CPU time 101.21 seconds
Started Jul 23 05:43:13 PM PDT 24
Finished Jul 23 05:44:54 PM PDT 24
Peak memory 201776 kb
Host smart-12b1a87c-e131-4077-9343-a1963f29e520
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058212889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1058212889
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1125384057
Short name T860
Test name
Test status
Simulation time 784549603 ps
CPU time 1.18 seconds
Started Jul 23 05:43:10 PM PDT 24
Finished Jul 23 05:43:12 PM PDT 24
Peak memory 201460 kb
Host smart-fa06e86e-610d-490c-83c7-84568edbcbc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125384057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1125384057
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2129345791
Short name T880
Test name
Test status
Simulation time 382460742 ps
CPU time 1.38 seconds
Started Jul 23 05:43:13 PM PDT 24
Finished Jul 23 05:43:16 PM PDT 24
Peak memory 201548 kb
Host smart-032aea5d-c548-4caf-a576-c33ccc5d0749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129345791 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2129345791
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3196608726
Short name T108
Test name
Test status
Simulation time 383780351 ps
CPU time 0.98 seconds
Started Jul 23 05:43:09 PM PDT 24
Finished Jul 23 05:43:11 PM PDT 24
Peak memory 201456 kb
Host smart-56022a56-8125-48dd-a257-682630f07d64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196608726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3196608726
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3207075206
Short name T897
Test name
Test status
Simulation time 392285283 ps
CPU time 0.86 seconds
Started Jul 23 05:43:14 PM PDT 24
Finished Jul 23 05:43:16 PM PDT 24
Peak memory 201436 kb
Host smart-e4d84a38-f04a-4d0b-97cc-f23fdf6f44c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207075206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3207075206
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3831125429
Short name T120
Test name
Test status
Simulation time 2615957796 ps
CPU time 3.02 seconds
Started Jul 23 05:43:09 PM PDT 24
Finished Jul 23 05:43:13 PM PDT 24
Peak memory 201568 kb
Host smart-7d73a6a6-3cf6-4f0f-afda-2aca5193ef73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831125429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3831125429
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.746476330
Short name T858
Test name
Test status
Simulation time 684605481 ps
CPU time 1.78 seconds
Started Jul 23 05:43:08 PM PDT 24
Finished Jul 23 05:43:10 PM PDT 24
Peak memory 201760 kb
Host smart-df7c76e3-e041-4b10-b1f2-da626afd149d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746476330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.746476330
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.639473072
Short name T348
Test name
Test status
Simulation time 8035975928 ps
CPU time 17.57 seconds
Started Jul 23 05:43:09 PM PDT 24
Finished Jul 23 05:43:27 PM PDT 24
Peak memory 201684 kb
Host smart-0ef03938-e915-4199-b6e2-61df7d738f1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639473072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.639473072
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3719865003
Short name T825
Test name
Test status
Simulation time 480397652 ps
CPU time 1.35 seconds
Started Jul 23 05:43:42 PM PDT 24
Finished Jul 23 05:43:44 PM PDT 24
Peak memory 201320 kb
Host smart-6587eea7-aa9d-411e-ad9d-01895a8cca14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719865003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3719865003
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1923371829
Short name T845
Test name
Test status
Simulation time 528110805 ps
CPU time 0.92 seconds
Started Jul 23 05:43:41 PM PDT 24
Finished Jul 23 05:43:42 PM PDT 24
Peak memory 201344 kb
Host smart-c444a211-50ea-4b6d-8acf-02c2961a4a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923371829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1923371829
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2765641512
Short name T836
Test name
Test status
Simulation time 333972895 ps
CPU time 1.05 seconds
Started Jul 23 05:43:41 PM PDT 24
Finished Jul 23 05:43:44 PM PDT 24
Peak memory 201396 kb
Host smart-f2fd3ab9-0a0c-4abb-ab20-9c21ed83f4b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765641512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2765641512
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.951558838
Short name T839
Test name
Test status
Simulation time 474274679 ps
CPU time 1.64 seconds
Started Jul 23 05:43:47 PM PDT 24
Finished Jul 23 05:43:49 PM PDT 24
Peak memory 201432 kb
Host smart-a762bf1f-4aa5-4881-bc18-25d5e482a5ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951558838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.951558838
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1600847632
Short name T855
Test name
Test status
Simulation time 361207076 ps
CPU time 1.02 seconds
Started Jul 23 05:43:47 PM PDT 24
Finished Jul 23 05:43:50 PM PDT 24
Peak memory 201432 kb
Host smart-18394a54-8769-407c-8155-5b9ac95b78db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600847632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1600847632
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3638715387
Short name T823
Test name
Test status
Simulation time 316814472 ps
CPU time 0.8 seconds
Started Jul 23 05:43:51 PM PDT 24
Finished Jul 23 05:43:53 PM PDT 24
Peak memory 201344 kb
Host smart-ba4a22fb-c705-4644-8610-622ca69c924c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638715387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3638715387
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3828707394
Short name T859
Test name
Test status
Simulation time 406240033 ps
CPU time 1.6 seconds
Started Jul 23 05:43:51 PM PDT 24
Finished Jul 23 05:43:54 PM PDT 24
Peak memory 201344 kb
Host smart-de86d4f1-c505-4ba3-9637-baa1630ff464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828707394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3828707394
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2337042530
Short name T919
Test name
Test status
Simulation time 484326848 ps
CPU time 1.17 seconds
Started Jul 23 05:43:49 PM PDT 24
Finished Jul 23 05:43:52 PM PDT 24
Peak memory 201348 kb
Host smart-a1a832e1-3b94-46c2-bad8-a0b7fe9c5028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337042530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2337042530
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3096872430
Short name T849
Test name
Test status
Simulation time 299765684 ps
CPU time 1.38 seconds
Started Jul 23 05:43:48 PM PDT 24
Finished Jul 23 05:43:50 PM PDT 24
Peak memory 201420 kb
Host smart-f87e86b4-55d7-4bdd-bcbd-810abc4d47f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096872430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3096872430
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.370536063
Short name T828
Test name
Test status
Simulation time 517449404 ps
CPU time 1.22 seconds
Started Jul 23 05:43:48 PM PDT 24
Finished Jul 23 05:43:50 PM PDT 24
Peak memory 201672 kb
Host smart-7d19ec3d-61ab-4bb5-9b4a-ada42b848f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370536063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.370536063
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3598369184
Short name T853
Test name
Test status
Simulation time 1180925073 ps
CPU time 2.89 seconds
Started Jul 23 05:43:11 PM PDT 24
Finished Jul 23 05:43:15 PM PDT 24
Peak memory 201660 kb
Host smart-6fc521a6-f14d-457c-b58d-7e4d18f8e194
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598369184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3598369184
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.847726042
Short name T911
Test name
Test status
Simulation time 27487159611 ps
CPU time 11.47 seconds
Started Jul 23 05:43:09 PM PDT 24
Finished Jul 23 05:43:22 PM PDT 24
Peak memory 201744 kb
Host smart-9679acec-dd7b-4171-a255-d006484e29ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847726042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.847726042
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2405486997
Short name T914
Test name
Test status
Simulation time 934826254 ps
CPU time 2.66 seconds
Started Jul 23 05:43:10 PM PDT 24
Finished Jul 23 05:43:14 PM PDT 24
Peak memory 201400 kb
Host smart-eb7615e5-dfd4-46d8-9cfa-bdba9ba7574a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405486997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2405486997
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4247562467
Short name T64
Test name
Test status
Simulation time 548506690 ps
CPU time 1.89 seconds
Started Jul 23 05:43:17 PM PDT 24
Finished Jul 23 05:43:20 PM PDT 24
Peak memory 201548 kb
Host smart-c37c76e4-bc05-4ac6-af2f-3b0b38ec0dc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247562467 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.4247562467
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3373443636
Short name T113
Test name
Test status
Simulation time 389929084 ps
CPU time 1.18 seconds
Started Jul 23 05:43:11 PM PDT 24
Finished Jul 23 05:43:13 PM PDT 24
Peak memory 201376 kb
Host smart-65e345dc-01d6-4185-8623-0eb9bde8d711
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373443636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3373443636
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.42117975
Short name T818
Test name
Test status
Simulation time 414653596 ps
CPU time 1.49 seconds
Started Jul 23 05:43:14 PM PDT 24
Finished Jul 23 05:43:16 PM PDT 24
Peak memory 201412 kb
Host smart-25fe803d-12f9-4897-8232-e079ae863b22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42117975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.42117975
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3387169903
Short name T902
Test name
Test status
Simulation time 4893225352 ps
CPU time 2.03 seconds
Started Jul 23 05:43:11 PM PDT 24
Finished Jul 23 05:43:14 PM PDT 24
Peak memory 201756 kb
Host smart-e36cedc4-16b5-4832-93ca-1d14d36a526e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387169903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3387169903
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2057033160
Short name T831
Test name
Test status
Simulation time 593889905 ps
CPU time 2.56 seconds
Started Jul 23 05:43:09 PM PDT 24
Finished Jul 23 05:43:14 PM PDT 24
Peak memory 201700 kb
Host smart-972fd14e-b148-4268-adb3-c98a2b64388e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057033160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2057033160
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1127458855
Short name T840
Test name
Test status
Simulation time 8009120147 ps
CPU time 7.66 seconds
Started Jul 23 05:43:14 PM PDT 24
Finished Jul 23 05:43:23 PM PDT 24
Peak memory 201772 kb
Host smart-810a703e-e521-42c8-a173-323cc6d644e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127458855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1127458855
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3718323943
Short name T812
Test name
Test status
Simulation time 381340173 ps
CPU time 1.09 seconds
Started Jul 23 05:43:47 PM PDT 24
Finished Jul 23 05:43:49 PM PDT 24
Peak memory 201436 kb
Host smart-6a6b3d11-f498-46e4-8360-4b2a212dde17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718323943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3718323943
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.563449708
Short name T811
Test name
Test status
Simulation time 492580234 ps
CPU time 0.93 seconds
Started Jul 23 05:43:45 PM PDT 24
Finished Jul 23 05:43:47 PM PDT 24
Peak memory 201380 kb
Host smart-dc03f714-a6a8-4024-b8ba-47336a1045db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563449708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.563449708
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1226268552
Short name T847
Test name
Test status
Simulation time 405389797 ps
CPU time 1.57 seconds
Started Jul 23 05:43:46 PM PDT 24
Finished Jul 23 05:43:48 PM PDT 24
Peak memory 201464 kb
Host smart-c72a6caf-67c4-4fcd-b678-aa30165a184f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226268552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1226268552
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1844681171
Short name T882
Test name
Test status
Simulation time 460828430 ps
CPU time 1.2 seconds
Started Jul 23 05:43:47 PM PDT 24
Finished Jul 23 05:43:49 PM PDT 24
Peak memory 201424 kb
Host smart-8b857259-8ce2-4145-bcc5-03060e8af676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844681171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1844681171
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2377649285
Short name T866
Test name
Test status
Simulation time 414504591 ps
CPU time 1.14 seconds
Started Jul 23 05:43:50 PM PDT 24
Finished Jul 23 05:43:53 PM PDT 24
Peak memory 201320 kb
Host smart-f0d3d71e-d3f6-4461-9cae-a7e8cb4c51f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377649285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2377649285
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.4237837652
Short name T863
Test name
Test status
Simulation time 438333348 ps
CPU time 1.5 seconds
Started Jul 23 05:43:49 PM PDT 24
Finished Jul 23 05:43:52 PM PDT 24
Peak memory 201436 kb
Host smart-186d48fb-9206-436e-81a5-28ab02abe99c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237837652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.4237837652
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.674329232
Short name T798
Test name
Test status
Simulation time 404769435 ps
CPU time 1.57 seconds
Started Jul 23 05:43:49 PM PDT 24
Finished Jul 23 05:43:52 PM PDT 24
Peak memory 201352 kb
Host smart-5b3307ec-c786-4f09-bbe3-52926447fc57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674329232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.674329232
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.379528736
Short name T824
Test name
Test status
Simulation time 503671220 ps
CPU time 1.13 seconds
Started Jul 23 05:43:48 PM PDT 24
Finished Jul 23 05:43:50 PM PDT 24
Peak memory 201292 kb
Host smart-aa88dce4-fea5-4758-bace-c93ea111201a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379528736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.379528736
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1605596742
Short name T838
Test name
Test status
Simulation time 532592327 ps
CPU time 1.92 seconds
Started Jul 23 05:43:47 PM PDT 24
Finished Jul 23 05:43:50 PM PDT 24
Peak memory 201448 kb
Host smart-228c1961-bda0-419c-a84a-2915fc59d098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605596742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1605596742
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3740677699
Short name T833
Test name
Test status
Simulation time 513099851 ps
CPU time 1.87 seconds
Started Jul 23 05:43:48 PM PDT 24
Finished Jul 23 05:43:51 PM PDT 24
Peak memory 201436 kb
Host smart-888cfb58-55ee-4902-8a10-b6b1e759a737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740677699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3740677699
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3080377331
Short name T905
Test name
Test status
Simulation time 663641060 ps
CPU time 1.48 seconds
Started Jul 23 05:43:15 PM PDT 24
Finished Jul 23 05:43:18 PM PDT 24
Peak memory 210052 kb
Host smart-41f7116c-56be-4969-9af7-fa58221e28ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080377331 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3080377331
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1033957189
Short name T900
Test name
Test status
Simulation time 539407598 ps
CPU time 1.11 seconds
Started Jul 23 05:43:17 PM PDT 24
Finished Jul 23 05:43:20 PM PDT 24
Peak memory 201376 kb
Host smart-549b0abc-fc7c-4281-8c42-e8d976b50e7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033957189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1033957189
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1850616327
Short name T806
Test name
Test status
Simulation time 526328420 ps
CPU time 0.9 seconds
Started Jul 23 05:43:17 PM PDT 24
Finished Jul 23 05:43:19 PM PDT 24
Peak memory 201372 kb
Host smart-218e1b13-8483-4275-a4a6-1aaf972da171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850616327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1850616327
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.748108534
Short name T837
Test name
Test status
Simulation time 3990434588 ps
CPU time 12.43 seconds
Started Jul 23 05:43:17 PM PDT 24
Finished Jul 23 05:43:31 PM PDT 24
Peak memory 201728 kb
Host smart-76cbdb2a-e2c1-4ab2-a23c-7f3320d2a103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748108534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.748108534
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1369730736
Short name T915
Test name
Test status
Simulation time 578300421 ps
CPU time 2.07 seconds
Started Jul 23 05:43:15 PM PDT 24
Finished Jul 23 05:43:18 PM PDT 24
Peak memory 209896 kb
Host smart-d4a8f6c3-f2f1-47c3-b67e-d08159fc0049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369730736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1369730736
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1209381615
Short name T347
Test name
Test status
Simulation time 4314036915 ps
CPU time 10.66 seconds
Started Jul 23 05:43:14 PM PDT 24
Finished Jul 23 05:43:26 PM PDT 24
Peak memory 201724 kb
Host smart-c7d09009-7384-4950-a9bb-05b26895349e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209381615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1209381615
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1668055387
Short name T84
Test name
Test status
Simulation time 499965373 ps
CPU time 1.22 seconds
Started Jul 23 05:43:14 PM PDT 24
Finished Jul 23 05:43:17 PM PDT 24
Peak memory 201556 kb
Host smart-f360a9d6-689b-466e-84bb-cb296c82deea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668055387 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1668055387
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1590419267
Short name T121
Test name
Test status
Simulation time 491187148 ps
CPU time 0.96 seconds
Started Jul 23 05:43:15 PM PDT 24
Finished Jul 23 05:43:17 PM PDT 24
Peak memory 201400 kb
Host smart-7a6baefa-6ac7-467c-925d-fc401385847b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590419267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1590419267
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1034049530
Short name T801
Test name
Test status
Simulation time 608258845 ps
CPU time 0.69 seconds
Started Jul 23 05:43:16 PM PDT 24
Finished Jul 23 05:43:18 PM PDT 24
Peak memory 201436 kb
Host smart-89c1d8c7-2cb4-470d-8305-b3c4a701e949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034049530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1034049530
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1074998260
Short name T47
Test name
Test status
Simulation time 4967443278 ps
CPU time 11.11 seconds
Started Jul 23 05:43:16 PM PDT 24
Finished Jul 23 05:43:28 PM PDT 24
Peak memory 201736 kb
Host smart-aab8adc6-909e-4c06-98a7-84b8ae3b705a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074998260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1074998260
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3284380377
Short name T892
Test name
Test status
Simulation time 503218801 ps
CPU time 2.77 seconds
Started Jul 23 05:43:16 PM PDT 24
Finished Jul 23 05:43:20 PM PDT 24
Peak memory 201756 kb
Host smart-e0985159-80f8-4aa4-a740-d5eaa3dd4c09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284380377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3284380377
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2098667068
Short name T881
Test name
Test status
Simulation time 501103158 ps
CPU time 1.17 seconds
Started Jul 23 05:43:15 PM PDT 24
Finished Jul 23 05:43:17 PM PDT 24
Peak memory 201576 kb
Host smart-c43be678-a7d2-4e1b-8ac2-e144100d9d7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098667068 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2098667068
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1744549192
Short name T910
Test name
Test status
Simulation time 411482961 ps
CPU time 1.61 seconds
Started Jul 23 05:43:15 PM PDT 24
Finished Jul 23 05:43:18 PM PDT 24
Peak memory 201428 kb
Host smart-069022e0-b085-4abb-aae0-5899e0e5d968
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744549192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1744549192
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1013439429
Short name T893
Test name
Test status
Simulation time 344511613 ps
CPU time 0.89 seconds
Started Jul 23 05:43:13 PM PDT 24
Finished Jul 23 05:43:14 PM PDT 24
Peak memory 201464 kb
Host smart-e697f5ec-c7d3-443f-8144-5c48347a2d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013439429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1013439429
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.741098170
Short name T119
Test name
Test status
Simulation time 5374798006 ps
CPU time 5.53 seconds
Started Jul 23 05:43:16 PM PDT 24
Finished Jul 23 05:43:23 PM PDT 24
Peak memory 201796 kb
Host smart-eb51b2dd-0c4f-4ec0-879b-e4a1a851d346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741098170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.741098170
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3556948808
Short name T835
Test name
Test status
Simulation time 626732017 ps
CPU time 3.74 seconds
Started Jul 23 05:43:16 PM PDT 24
Finished Jul 23 05:43:22 PM PDT 24
Peak memory 217700 kb
Host smart-221d158b-2e69-4d41-8570-0fd5c15bc947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556948808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3556948808
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.527037485
Short name T53
Test name
Test status
Simulation time 4099864853 ps
CPU time 9.5 seconds
Started Jul 23 05:43:15 PM PDT 24
Finished Jul 23 05:43:26 PM PDT 24
Peak memory 201716 kb
Host smart-071e0238-dd37-4491-aada-843d79ed4571
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527037485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.527037485
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2061880509
Short name T889
Test name
Test status
Simulation time 326776202 ps
CPU time 1.56 seconds
Started Jul 23 05:43:15 PM PDT 24
Finished Jul 23 05:43:19 PM PDT 24
Peak memory 201592 kb
Host smart-87ee9fa7-f5a4-4403-a4f3-ce5847b00e66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061880509 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2061880509
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4123128449
Short name T898
Test name
Test status
Simulation time 566781127 ps
CPU time 1.05 seconds
Started Jul 23 05:43:16 PM PDT 24
Finished Jul 23 05:43:19 PM PDT 24
Peak memory 201460 kb
Host smart-cae4b1fd-eefe-4ec1-86e6-b16f3aa3e062
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123128449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4123128449
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3292343387
Short name T906
Test name
Test status
Simulation time 595013439 ps
CPU time 0.7 seconds
Started Jul 23 05:43:14 PM PDT 24
Finished Jul 23 05:43:16 PM PDT 24
Peak memory 201428 kb
Host smart-d5905423-c141-4435-8c9a-8fe81d9ef058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292343387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3292343387
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.560860661
Short name T891
Test name
Test status
Simulation time 5086184064 ps
CPU time 4.94 seconds
Started Jul 23 05:43:14 PM PDT 24
Finished Jul 23 05:43:20 PM PDT 24
Peak memory 201796 kb
Host smart-369a099f-6a2d-4630-8f14-9218f0e1e41a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560860661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.560860661
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.212292485
Short name T810
Test name
Test status
Simulation time 708882915 ps
CPU time 1.51 seconds
Started Jul 23 05:43:15 PM PDT 24
Finished Jul 23 05:43:18 PM PDT 24
Peak memory 201620 kb
Host smart-4b421fc0-a3fb-4f4a-91b7-a359199d4430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212292485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.212292485
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4170672352
Short name T349
Test name
Test status
Simulation time 7997626920 ps
CPU time 5.09 seconds
Started Jul 23 05:43:16 PM PDT 24
Finished Jul 23 05:43:23 PM PDT 24
Peak memory 201756 kb
Host smart-7783a155-28db-4f1d-8745-6db2c5411f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170672352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.4170672352
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2098496030
Short name T909
Test name
Test status
Simulation time 844711106 ps
CPU time 0.9 seconds
Started Jul 23 05:43:13 PM PDT 24
Finished Jul 23 05:43:15 PM PDT 24
Peak memory 201556 kb
Host smart-de8f7559-1fe5-41cb-b84a-290a5df2fe9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098496030 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2098496030
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1890556499
Short name T105
Test name
Test status
Simulation time 405099420 ps
CPU time 0.93 seconds
Started Jul 23 05:43:17 PM PDT 24
Finished Jul 23 05:43:19 PM PDT 24
Peak memory 201460 kb
Host smart-77b91ac5-684a-4030-8181-f0ce6f0eff0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890556499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1890556499
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1668752140
Short name T802
Test name
Test status
Simulation time 336486950 ps
CPU time 1.34 seconds
Started Jul 23 05:43:19 PM PDT 24
Finished Jul 23 05:43:21 PM PDT 24
Peak memory 201404 kb
Host smart-f33b3e8c-c0a5-4dd9-b55c-cce9c455c468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668752140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1668752140
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2166688389
Short name T857
Test name
Test status
Simulation time 2280338827 ps
CPU time 2.06 seconds
Started Jul 23 05:43:15 PM PDT 24
Finished Jul 23 05:43:18 PM PDT 24
Peak memory 201520 kb
Host smart-46d4c47d-6905-433d-be62-957d379028d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166688389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2166688389
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.114451790
Short name T59
Test name
Test status
Simulation time 1261102099 ps
CPU time 1.47 seconds
Started Jul 23 05:43:15 PM PDT 24
Finished Jul 23 05:43:18 PM PDT 24
Peak memory 201748 kb
Host smart-bf55227f-a3e7-4f37-9364-4dd6937c88d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114451790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.114451790
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4134263570
Short name T841
Test name
Test status
Simulation time 5018788473 ps
CPU time 4.65 seconds
Started Jul 23 05:43:15 PM PDT 24
Finished Jul 23 05:43:22 PM PDT 24
Peak memory 201736 kb
Host smart-0d5c5e9e-af83-4414-abe1-1073a481c687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134263570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.4134263570
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.178577881
Short name T465
Test name
Test status
Simulation time 477748674 ps
CPU time 1.19 seconds
Started Jul 23 06:59:50 PM PDT 24
Finished Jul 23 06:59:59 PM PDT 24
Peak memory 200908 kb
Host smart-5279c90a-3bca-4644-a469-33769bf33b8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178577881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.178577881
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2069493060
Short name T311
Test name
Test status
Simulation time 488567327268 ps
CPU time 1150.19 seconds
Started Jul 23 06:59:52 PM PDT 24
Finished Jul 23 07:19:08 PM PDT 24
Peak memory 201288 kb
Host smart-7a1458fc-38bc-436f-95ab-da1b9d71cad7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069493060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2069493060
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1272179702
Short name T331
Test name
Test status
Simulation time 162983628146 ps
CPU time 40.94 seconds
Started Jul 23 06:59:51 PM PDT 24
Finished Jul 23 07:00:39 PM PDT 24
Peak memory 201312 kb
Host smart-2156b70f-5765-4c85-a3a2-18b1e819a622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272179702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1272179702
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1088218768
Short name T366
Test name
Test status
Simulation time 170024591420 ps
CPU time 187.11 seconds
Started Jul 23 06:59:45 PM PDT 24
Finished Jul 23 07:02:59 PM PDT 24
Peak memory 201120 kb
Host smart-787d0185-a24b-4bfe-959b-baed92557dc1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088218768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1088218768
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.4093372911
Short name T692
Test name
Test status
Simulation time 166026426665 ps
CPU time 104.05 seconds
Started Jul 23 06:59:44 PM PDT 24
Finished Jul 23 07:01:35 PM PDT 24
Peak memory 201312 kb
Host smart-6704efd4-990d-4b08-9aa9-c17e63195297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093372911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.4093372911
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3923596634
Short name T596
Test name
Test status
Simulation time 315166733629 ps
CPU time 371.73 seconds
Started Jul 23 06:59:47 PM PDT 24
Finished Jul 23 07:06:07 PM PDT 24
Peak memory 201240 kb
Host smart-b47e1a5f-04f8-458c-a3b2-b55b20d68bf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923596634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3923596634
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1695362683
Short name T472
Test name
Test status
Simulation time 178098504138 ps
CPU time 83.77 seconds
Started Jul 23 06:59:45 PM PDT 24
Finished Jul 23 07:01:16 PM PDT 24
Peak memory 201320 kb
Host smart-b25431eb-14b5-4f83-9efc-a5814497330f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695362683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1695362683
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.575037724
Short name T679
Test name
Test status
Simulation time 595138530590 ps
CPU time 1287.68 seconds
Started Jul 23 06:59:52 PM PDT 24
Finished Jul 23 07:21:26 PM PDT 24
Peak memory 201288 kb
Host smart-1aae5500-6b61-4e87-9bc5-1e239a681662
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575037724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.575037724
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3417524890
Short name T510
Test name
Test status
Simulation time 85092231932 ps
CPU time 458.67 seconds
Started Jul 23 06:59:54 PM PDT 24
Finished Jul 23 07:07:38 PM PDT 24
Peak memory 201692 kb
Host smart-bf3755ff-d195-45d4-8d38-3defb67e93fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417524890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3417524890
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2597251919
Short name T577
Test name
Test status
Simulation time 26030949410 ps
CPU time 47.01 seconds
Started Jul 23 06:59:51 PM PDT 24
Finished Jul 23 07:00:45 PM PDT 24
Peak memory 201080 kb
Host smart-1b3dd79b-0351-4b23-b40c-8e99c37820c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597251919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2597251919
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3348461849
Short name T552
Test name
Test status
Simulation time 4352772270 ps
CPU time 9.76 seconds
Started Jul 23 06:59:50 PM PDT 24
Finished Jul 23 07:00:07 PM PDT 24
Peak memory 201072 kb
Host smart-00ef5c1f-2595-4cf9-8222-a751d5e607c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348461849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3348461849
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.633655536
Short name T407
Test name
Test status
Simulation time 5633331181 ps
CPU time 5.91 seconds
Started Jul 23 06:59:45 PM PDT 24
Finished Jul 23 06:59:58 PM PDT 24
Peak memory 201028 kb
Host smart-fef0fcf9-1590-49f7-aef1-05a38f31ca3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633655536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.633655536
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1164232015
Short name T356
Test name
Test status
Simulation time 1462042825989 ps
CPU time 3791.61 seconds
Started Jul 23 06:59:54 PM PDT 24
Finished Jul 23 08:03:11 PM PDT 24
Peak memory 209936 kb
Host smart-1dbe5368-07e8-4de2-9b30-e9d1ea5c89ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164232015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1164232015
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2537408490
Short name T534
Test name
Test status
Simulation time 338111670 ps
CPU time 1.02 seconds
Started Jul 23 07:00:05 PM PDT 24
Finished Jul 23 07:00:07 PM PDT 24
Peak memory 200964 kb
Host smart-86849f36-2a6c-4514-b09f-76eb7371c34d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537408490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2537408490
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1529606881
Short name T785
Test name
Test status
Simulation time 485777081213 ps
CPU time 1079.45 seconds
Started Jul 23 06:59:50 PM PDT 24
Finished Jul 23 07:17:56 PM PDT 24
Peak memory 201248 kb
Host smart-ce3af485-c7ea-4879-a33e-52d7c47e0574
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529606881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1529606881
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1470468204
Short name T564
Test name
Test status
Simulation time 160438032263 ps
CPU time 186.7 seconds
Started Jul 23 06:59:56 PM PDT 24
Finished Jul 23 07:03:07 PM PDT 24
Peak memory 201228 kb
Host smart-21d01f32-e666-4481-bb39-1b50caa18ea3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470468204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1470468204
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3759159794
Short name T545
Test name
Test status
Simulation time 327362616941 ps
CPU time 376.16 seconds
Started Jul 23 06:59:51 PM PDT 24
Finished Jul 23 07:06:14 PM PDT 24
Peak memory 201284 kb
Host smart-1c76de0b-5b33-428e-9d56-3d84a1bead14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759159794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3759159794
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1884511913
Short name T166
Test name
Test status
Simulation time 324044667403 ps
CPU time 128.39 seconds
Started Jul 23 06:59:50 PM PDT 24
Finished Jul 23 07:02:05 PM PDT 24
Peak memory 201236 kb
Host smart-d82d3d84-5969-4c71-9e6e-5565d5d6b323
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884511913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1884511913
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.396141566
Short name T130
Test name
Test status
Simulation time 383106741149 ps
CPU time 855.9 seconds
Started Jul 23 06:59:49 PM PDT 24
Finished Jul 23 07:14:12 PM PDT 24
Peak memory 201280 kb
Host smart-1704beba-8c2b-46bf-8132-ba42e66acc4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396141566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.396141566
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3819653560
Short name T493
Test name
Test status
Simulation time 382064137607 ps
CPU time 218.25 seconds
Started Jul 23 06:59:52 PM PDT 24
Finished Jul 23 07:03:37 PM PDT 24
Peak memory 201240 kb
Host smart-584db8fd-f835-4c7a-b7d1-3c194c3060b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819653560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3819653560
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3533277299
Short name T688
Test name
Test status
Simulation time 43168327023 ps
CPU time 27.27 seconds
Started Jul 23 06:59:50 PM PDT 24
Finished Jul 23 07:00:25 PM PDT 24
Peak memory 200936 kb
Host smart-ba9daf49-8fc7-4bb0-85b6-0b6853c349cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533277299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3533277299
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1653157687
Short name T185
Test name
Test status
Simulation time 2962359504 ps
CPU time 4.33 seconds
Started Jul 23 06:59:50 PM PDT 24
Finished Jul 23 07:00:02 PM PDT 24
Peak memory 201076 kb
Host smart-995f986e-320b-4f7e-b0ab-07d92f65dbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653157687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1653157687
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1231902725
Short name T55
Test name
Test status
Simulation time 8390794402 ps
CPU time 4.83 seconds
Started Jul 23 06:59:52 PM PDT 24
Finished Jul 23 07:00:03 PM PDT 24
Peak memory 218044 kb
Host smart-581ad75d-6022-40a3-8d37-0e30e227caff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231902725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1231902725
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.242220321
Short name T403
Test name
Test status
Simulation time 5966761532 ps
CPU time 15.13 seconds
Started Jul 23 06:59:52 PM PDT 24
Finished Jul 23 07:00:13 PM PDT 24
Peak memory 201100 kb
Host smart-a07921d8-f3fe-4878-ac3a-6d1dbec0e771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242220321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.242220321
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1846849063
Short name T217
Test name
Test status
Simulation time 157947695635 ps
CPU time 549.25 seconds
Started Jul 23 06:59:53 PM PDT 24
Finished Jul 23 07:09:08 PM PDT 24
Peak memory 209976 kb
Host smart-563b235e-a352-47c6-aa09-89502041641d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846849063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1846849063
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3166164593
Short name T171
Test name
Test status
Simulation time 164264520036 ps
CPU time 94.07 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:02:17 PM PDT 24
Peak memory 201212 kb
Host smart-2d6b9246-d160-4eec-8995-7a92189e5c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166164593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3166164593
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3964698344
Short name T301
Test name
Test status
Simulation time 486613775414 ps
CPU time 331.29 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:06:14 PM PDT 24
Peak memory 201144 kb
Host smart-1b7a19bd-7fdf-4741-91b6-d215af99e95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964698344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3964698344
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.119099014
Short name T554
Test name
Test status
Simulation time 491719440171 ps
CPU time 1044.4 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:18:07 PM PDT 24
Peak memory 201216 kb
Host smart-1207868e-0bd6-4e8c-9819-154f32a35474
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=119099014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.119099014
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.823898665
Short name T251
Test name
Test status
Simulation time 335396861001 ps
CPU time 59.98 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:01:41 PM PDT 24
Peak memory 201248 kb
Host smart-d784abc3-e6ae-4975-a8dc-1711bc2b8b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823898665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.823898665
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3885262712
Short name T372
Test name
Test status
Simulation time 163729311213 ps
CPU time 204.55 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:04:06 PM PDT 24
Peak memory 201240 kb
Host smart-d4a85e60-cef7-41c8-aafe-84a800c86a1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885262712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3885262712
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3260007349
Short name T630
Test name
Test status
Simulation time 557538581492 ps
CPU time 199.59 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:04:03 PM PDT 24
Peak memory 201208 kb
Host smart-ab971179-ded2-405b-bf48-f2631dec7661
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260007349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3260007349
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3551894724
Short name T450
Test name
Test status
Simulation time 599811569829 ps
CPU time 1260.29 seconds
Started Jul 23 07:00:35 PM PDT 24
Finished Jul 23 07:21:37 PM PDT 24
Peak memory 201192 kb
Host smart-52d93975-37eb-4a18-b4ba-5075a1368c5b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551894724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3551894724
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1881695114
Short name T655
Test name
Test status
Simulation time 66563642531 ps
CPU time 373.88 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:06:56 PM PDT 24
Peak memory 201592 kb
Host smart-407a452c-263b-428d-8796-d8b3dd5a7ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881695114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1881695114
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.419185704
Short name T651
Test name
Test status
Simulation time 32562801386 ps
CPU time 71.16 seconds
Started Jul 23 07:00:35 PM PDT 24
Finished Jul 23 07:01:48 PM PDT 24
Peak memory 201064 kb
Host smart-643c8ee8-4e6f-4268-ae09-8b73ab8353c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419185704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.419185704
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.349453037
Short name T478
Test name
Test status
Simulation time 3316574678 ps
CPU time 2.54 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:00:46 PM PDT 24
Peak memory 200988 kb
Host smart-063f23b2-c1d0-4a30-87ff-4b2fe0f196e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349453037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.349453037
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.8511756
Short name T728
Test name
Test status
Simulation time 5898821561 ps
CPU time 14.69 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:00:58 PM PDT 24
Peak memory 200872 kb
Host smart-4ba1568e-f248-4f6c-a736-26ef595f1fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8511756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.8511756
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2059652721
Short name T353
Test name
Test status
Simulation time 61061715429 ps
CPU time 252.9 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:04:56 PM PDT 24
Peak memory 209972 kb
Host smart-cb333da8-6c76-497d-8b56-e43f83635453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059652721 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2059652721
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3475396450
Short name T459
Test name
Test status
Simulation time 485585340 ps
CPU time 1.19 seconds
Started Jul 23 07:00:39 PM PDT 24
Finished Jul 23 07:00:41 PM PDT 24
Peak memory 201040 kb
Host smart-4fa38686-73a3-4d0f-acc6-99e736e06f84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475396450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3475396450
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1604072529
Short name T323
Test name
Test status
Simulation time 527969374493 ps
CPU time 547.98 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:09:51 PM PDT 24
Peak memory 201252 kb
Host smart-baf86a2e-2d53-4f1e-b261-103a00e3c499
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604072529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1604072529
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2454191696
Short name T343
Test name
Test status
Simulation time 357231834126 ps
CPU time 885.33 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:15:28 PM PDT 24
Peak memory 201224 kb
Host smart-a691fba0-69a3-4461-95ae-08b7b0d02302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454191696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2454191696
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.273537454
Short name T202
Test name
Test status
Simulation time 485959260227 ps
CPU time 322.45 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:06:03 PM PDT 24
Peak memory 201336 kb
Host smart-cadda11e-70b2-40d6-99f3-4d127840a996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273537454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.273537454
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1137164475
Short name T432
Test name
Test status
Simulation time 329069236299 ps
CPU time 198.92 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:04:01 PM PDT 24
Peak memory 201220 kb
Host smart-39b307ce-c732-4287-8c85-cfb977ca240c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137164475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1137164475
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.4060744046
Short name T229
Test name
Test status
Simulation time 330888399726 ps
CPU time 205.93 seconds
Started Jul 23 07:00:42 PM PDT 24
Finished Jul 23 07:04:10 PM PDT 24
Peak memory 201300 kb
Host smart-ea18791b-48c8-4a98-a830-20e147d894eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060744046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.4060744046
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3240595850
Short name T371
Test name
Test status
Simulation time 157587277673 ps
CPU time 86.18 seconds
Started Jul 23 07:00:39 PM PDT 24
Finished Jul 23 07:02:06 PM PDT 24
Peak memory 201252 kb
Host smart-60471011-f24d-4830-aa8c-509bcc65de8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240595850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3240595850
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1369709021
Short name T88
Test name
Test status
Simulation time 465495200379 ps
CPU time 250.86 seconds
Started Jul 23 07:00:38 PM PDT 24
Finished Jul 23 07:04:50 PM PDT 24
Peak memory 201212 kb
Host smart-f695f2e3-18b3-4347-ab78-9c3f1435e60f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369709021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1369709021
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2461811958
Short name T766
Test name
Test status
Simulation time 611109782797 ps
CPU time 122.61 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:02:45 PM PDT 24
Peak memory 201232 kb
Host smart-77990608-e8d8-4e77-a9b8-d9c21d9fcf75
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461811958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2461811958
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1081772252
Short name T355
Test name
Test status
Simulation time 72913525035 ps
CPU time 319.83 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:06:03 PM PDT 24
Peak memory 201672 kb
Host smart-5eb9801b-e961-495e-9361-b2f3cc1da2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081772252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1081772252
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1045406315
Short name T94
Test name
Test status
Simulation time 39198305354 ps
CPU time 29.99 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:01:13 PM PDT 24
Peak memory 201072 kb
Host smart-3aab782d-fc3d-4033-bddf-f1434bdc76f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045406315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1045406315
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2594057537
Short name T705
Test name
Test status
Simulation time 2691566881 ps
CPU time 2.46 seconds
Started Jul 23 07:00:37 PM PDT 24
Finished Jul 23 07:00:41 PM PDT 24
Peak memory 200996 kb
Host smart-26964142-e296-4132-b117-fbb1f1210de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594057537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2594057537
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2050922028
Short name T466
Test name
Test status
Simulation time 5708422956 ps
CPU time 1.69 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:00:44 PM PDT 24
Peak memory 201060 kb
Host smart-7856dc4a-09b7-4602-a2d3-5812831c35c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050922028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2050922028
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1792036477
Short name T209
Test name
Test status
Simulation time 72735830211 ps
CPU time 286.24 seconds
Started Jul 23 07:00:36 PM PDT 24
Finished Jul 23 07:05:24 PM PDT 24
Peak memory 201680 kb
Host smart-4f9c4cd6-b236-4f13-8495-5f142466b056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792036477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1792036477
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.892290085
Short name T13
Test name
Test status
Simulation time 79580761349 ps
CPU time 117.31 seconds
Started Jul 23 07:00:39 PM PDT 24
Finished Jul 23 07:02:37 PM PDT 24
Peak memory 210000 kb
Host smart-8c450aad-2e40-4960-96ab-d769d213f19a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892290085 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.892290085
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2641350067
Short name T779
Test name
Test status
Simulation time 426002166 ps
CPU time 1.54 seconds
Started Jul 23 07:00:55 PM PDT 24
Finished Jul 23 07:01:01 PM PDT 24
Peak memory 201000 kb
Host smart-ff26acc9-ad3d-43fc-8960-674c564d1b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641350067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2641350067
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.550675940
Short name T286
Test name
Test status
Simulation time 349940063912 ps
CPU time 715.87 seconds
Started Jul 23 07:00:36 PM PDT 24
Finished Jul 23 07:12:33 PM PDT 24
Peak memory 201500 kb
Host smart-dd545b73-bd45-47f8-a4cb-11933464ef8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550675940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.550675940
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2583254658
Short name T282
Test name
Test status
Simulation time 497831334603 ps
CPU time 329.82 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:06:11 PM PDT 24
Peak memory 201124 kb
Host smart-121732ab-fa92-4ece-a946-3fd56c95a958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583254658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2583254658
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.151239087
Short name T656
Test name
Test status
Simulation time 489205574413 ps
CPU time 319.96 seconds
Started Jul 23 07:00:36 PM PDT 24
Finished Jul 23 07:05:58 PM PDT 24
Peak memory 201260 kb
Host smart-a6150d6d-074c-4c76-a14e-9714db7638af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=151239087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.151239087
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2874500885
Short name T253
Test name
Test status
Simulation time 326755539904 ps
CPU time 723.79 seconds
Started Jul 23 07:00:38 PM PDT 24
Finished Jul 23 07:12:43 PM PDT 24
Peak memory 201196 kb
Host smart-102148c1-7949-45e1-aa0c-4f43b700e7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874500885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2874500885
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.426492219
Short name T391
Test name
Test status
Simulation time 483260059623 ps
CPU time 596.85 seconds
Started Jul 23 07:00:37 PM PDT 24
Finished Jul 23 07:10:35 PM PDT 24
Peak memory 201228 kb
Host smart-559dd278-3ace-494e-b2c0-bc8ed5d5f1f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=426492219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.426492219
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3795441100
Short name T780
Test name
Test status
Simulation time 356334347875 ps
CPU time 745.72 seconds
Started Jul 23 07:00:38 PM PDT 24
Finished Jul 23 07:13:05 PM PDT 24
Peak memory 201244 kb
Host smart-42734944-baf2-45a8-9169-55f9da20ba17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795441100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3795441100
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.4081300930
Short name T652
Test name
Test status
Simulation time 397867110166 ps
CPU time 227.13 seconds
Started Jul 23 07:00:38 PM PDT 24
Finished Jul 23 07:04:27 PM PDT 24
Peak memory 201276 kb
Host smart-1eb9c068-1f9e-416c-a87e-6a061f552039
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081300930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.4081300930
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.436164105
Short name T420
Test name
Test status
Simulation time 93964974879 ps
CPU time 545.33 seconds
Started Jul 23 07:00:38 PM PDT 24
Finished Jul 23 07:09:44 PM PDT 24
Peak memory 201668 kb
Host smart-6469e909-5abd-4809-b548-e59429b86f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436164105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.436164105
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3883338002
Short name T768
Test name
Test status
Simulation time 44735925563 ps
CPU time 107.45 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:02:30 PM PDT 24
Peak memory 200928 kb
Host smart-17b21e71-c36b-4c24-ac94-3f215a5713d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883338002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3883338002
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3140873011
Short name T506
Test name
Test status
Simulation time 4117286280 ps
CPU time 2.99 seconds
Started Jul 23 07:00:37 PM PDT 24
Finished Jul 23 07:00:42 PM PDT 24
Peak memory 200988 kb
Host smart-ba4a009b-6afd-4c27-a02d-1317c63d9e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140873011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3140873011
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2055359154
Short name T402
Test name
Test status
Simulation time 5685148043 ps
CPU time 4.03 seconds
Started Jul 23 07:00:36 PM PDT 24
Finished Jul 23 07:00:42 PM PDT 24
Peak memory 201068 kb
Host smart-31112dcb-4ec5-4b10-bc12-d0c9203b97f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055359154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2055359154
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.745608391
Short name T164
Test name
Test status
Simulation time 278430318004 ps
CPU time 143.39 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:03:20 PM PDT 24
Peak memory 201300 kb
Host smart-6bc0cb26-1af0-49ab-9fd4-a7beed649321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745608391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
745608391
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.336130220
Short name T681
Test name
Test status
Simulation time 460173864 ps
CPU time 0.97 seconds
Started Jul 23 07:00:50 PM PDT 24
Finished Jul 23 07:00:52 PM PDT 24
Peak memory 200996 kb
Host smart-2a6f9711-c4a3-462c-9547-f769e2901928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336130220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.336130220
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3343181577
Short name T154
Test name
Test status
Simulation time 331213593739 ps
CPU time 151.8 seconds
Started Jul 23 07:00:44 PM PDT 24
Finished Jul 23 07:03:17 PM PDT 24
Peak memory 201252 kb
Host smart-689252a4-942b-4680-b928-ff256455ff22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343181577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3343181577
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2425421179
Short name T457
Test name
Test status
Simulation time 495526483950 ps
CPU time 304.56 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:06:01 PM PDT 24
Peak memory 200744 kb
Host smart-15bb6887-f1de-4af3-a920-6bb67245b185
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425421179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2425421179
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2468816550
Short name T168
Test name
Test status
Simulation time 328052084812 ps
CPU time 185.69 seconds
Started Jul 23 07:00:55 PM PDT 24
Finished Jul 23 07:04:04 PM PDT 24
Peak memory 201280 kb
Host smart-e326858e-67e2-447f-a062-9770d77fc743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468816550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2468816550
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3040297464
Short name T712
Test name
Test status
Simulation time 333250894587 ps
CPU time 184.17 seconds
Started Jul 23 07:00:44 PM PDT 24
Finished Jul 23 07:03:49 PM PDT 24
Peak memory 201208 kb
Host smart-019eb0f4-46f1-4830-958b-06cd80eceb83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040297464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3040297464
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.846492276
Short name T591
Test name
Test status
Simulation time 398184342916 ps
CPU time 475.91 seconds
Started Jul 23 07:00:48 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 201220 kb
Host smart-569fe888-71cd-4f0e-b125-5a09807ec501
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846492276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.846492276
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2207703486
Short name T427
Test name
Test status
Simulation time 46912740718 ps
CPU time 114.3 seconds
Started Jul 23 07:00:43 PM PDT 24
Finished Jul 23 07:02:39 PM PDT 24
Peak memory 201068 kb
Host smart-c870f1fa-dc49-47ca-aa1b-236e9383b48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207703486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2207703486
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.828783419
Short name T567
Test name
Test status
Simulation time 5032683896 ps
CPU time 3.64 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:01:00 PM PDT 24
Peak memory 201072 kb
Host smart-4c7bc966-82a8-4dc8-8546-48c7ef4d8ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828783419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.828783419
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.601849690
Short name T765
Test name
Test status
Simulation time 5627843878 ps
CPU time 4.39 seconds
Started Jul 23 07:00:46 PM PDT 24
Finished Jul 23 07:00:51 PM PDT 24
Peak memory 201068 kb
Host smart-8b45a8b0-2757-476a-9eac-ae0963004faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601849690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.601849690
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2812879770
Short name T86
Test name
Test status
Simulation time 144080669864 ps
CPU time 248.19 seconds
Started Jul 23 07:00:43 PM PDT 24
Finished Jul 23 07:04:53 PM PDT 24
Peak memory 210112 kb
Host smart-07ec6e7b-f6e9-4b76-9f63-4fd56de8c9be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812879770 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2812879770
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.655941225
Short name T477
Test name
Test status
Simulation time 331722823 ps
CPU time 0.96 seconds
Started Jul 23 07:00:48 PM PDT 24
Finished Jul 23 07:00:50 PM PDT 24
Peak memory 201044 kb
Host smart-08f532a9-bf10-4a33-b07e-b58bc69839da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655941225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.655941225
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2664368675
Short name T165
Test name
Test status
Simulation time 601223020322 ps
CPU time 367.12 seconds
Started Jul 23 07:00:50 PM PDT 24
Finished Jul 23 07:06:58 PM PDT 24
Peak memory 201296 kb
Host smart-c846b968-7699-43e3-bcc4-c09d324af1da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664368675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2664368675
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3730903709
Short name T647
Test name
Test status
Simulation time 200845848101 ps
CPU time 433.84 seconds
Started Jul 23 07:00:42 PM PDT 24
Finished Jul 23 07:07:58 PM PDT 24
Peak memory 201236 kb
Host smart-35e0a682-8321-42c1-b00c-2417781aef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730903709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3730903709
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.903533554
Short name T78
Test name
Test status
Simulation time 326180355443 ps
CPU time 135.63 seconds
Started Jul 23 07:00:48 PM PDT 24
Finished Jul 23 07:03:04 PM PDT 24
Peak memory 201236 kb
Host smart-28da6eae-2091-4aea-b979-782bfb507214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903533554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.903533554
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3511692935
Short name T399
Test name
Test status
Simulation time 492156859412 ps
CPU time 1240.57 seconds
Started Jul 23 07:00:50 PM PDT 24
Finished Jul 23 07:21:32 PM PDT 24
Peak memory 201188 kb
Host smart-a1886190-06f6-4bcc-999f-f6f0ae24688d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511692935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3511692935
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.4054108044
Short name T6
Test name
Test status
Simulation time 158056511241 ps
CPU time 72.66 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:02:09 PM PDT 24
Peak memory 200916 kb
Host smart-c1e217cf-b3a1-4837-945a-2e8c06610ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054108044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.4054108044
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1449790826
Short name T542
Test name
Test status
Simulation time 492411585913 ps
CPU time 1074.03 seconds
Started Jul 23 07:00:44 PM PDT 24
Finished Jul 23 07:18:39 PM PDT 24
Peak memory 201244 kb
Host smart-8a04bb3f-68c0-4e0a-a0c1-0c570e471cfe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449790826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1449790826
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1178666758
Short name T246
Test name
Test status
Simulation time 636875172268 ps
CPU time 1482.2 seconds
Started Jul 23 07:00:50 PM PDT 24
Finished Jul 23 07:25:33 PM PDT 24
Peak memory 201248 kb
Host smart-b56dcea0-dd33-4762-b307-e81400c01458
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178666758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1178666758
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.382315499
Short name T445
Test name
Test status
Simulation time 192426594074 ps
CPU time 471.44 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:08:48 PM PDT 24
Peak memory 201240 kb
Host smart-267bf53d-574b-4fae-8def-55645fbccd62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382315499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.382315499
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.684092887
Short name T208
Test name
Test status
Simulation time 122757823051 ps
CPU time 390.33 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:07:24 PM PDT 24
Peak memory 201764 kb
Host smart-0fce094d-7587-4e47-9bd3-1c91a81aa425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684092887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.684092887
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.602134986
Short name T690
Test name
Test status
Simulation time 31764006570 ps
CPU time 20.19 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:01:17 PM PDT 24
Peak memory 201076 kb
Host smart-cc6f1175-6086-4841-9031-8fcd677f79e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602134986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.602134986
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1392389779
Short name T387
Test name
Test status
Simulation time 3713823996 ps
CPU time 1.14 seconds
Started Jul 23 07:00:44 PM PDT 24
Finished Jul 23 07:00:46 PM PDT 24
Peak memory 201056 kb
Host smart-f3351bce-eac1-4906-86b3-b79a8ecc2401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392389779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1392389779
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.423977721
Short name T433
Test name
Test status
Simulation time 5753575789 ps
CPU time 3.96 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:01:02 PM PDT 24
Peak memory 201040 kb
Host smart-6f5afd90-25f7-4e0b-a8df-4f0cd4f06945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423977721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.423977721
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3093158670
Short name T99
Test name
Test status
Simulation time 333168569464 ps
CPU time 201.78 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:04:20 PM PDT 24
Peak memory 201200 kb
Host smart-5dc69f8a-8f64-4ca7-823a-42d0d6ea7ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093158670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3093158670
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3370014447
Short name T400
Test name
Test status
Simulation time 336926654 ps
CPU time 0.9 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:00:55 PM PDT 24
Peak memory 201040 kb
Host smart-14b8de54-5724-4980-8cfd-970b036aa26e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370014447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3370014447
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2699906099
Short name T691
Test name
Test status
Simulation time 167430344093 ps
CPU time 90.87 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:02:28 PM PDT 24
Peak memory 201224 kb
Host smart-2aeab08b-cd14-4bac-b915-9aa77816eed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699906099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2699906099
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1281328996
Short name T232
Test name
Test status
Simulation time 490667870967 ps
CPU time 547.83 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:10:02 PM PDT 24
Peak memory 201228 kb
Host smart-fe3ae7b1-03cb-4011-b34d-8cd0d14c9939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281328996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1281328996
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1094780720
Short name T795
Test name
Test status
Simulation time 161401935393 ps
CPU time 102.88 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:02:38 PM PDT 24
Peak memory 201280 kb
Host smart-21b05a44-0191-41b1-96d3-2827fe3fded8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094780720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1094780720
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3332018623
Short name T599
Test name
Test status
Simulation time 498231132787 ps
CPU time 254.65 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:05:10 PM PDT 24
Peak memory 201260 kb
Host smart-e19c3dce-41c9-4e08-823a-5c7b36ba4fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332018623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3332018623
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2676088737
Short name T530
Test name
Test status
Simulation time 335144770441 ps
CPU time 744.46 seconds
Started Jul 23 07:00:49 PM PDT 24
Finished Jul 23 07:13:15 PM PDT 24
Peak memory 201188 kb
Host smart-6892dd68-8562-45e6-812a-e38b15ee14a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676088737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2676088737
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3542069783
Short name T211
Test name
Test status
Simulation time 128989857792 ps
CPU time 443.01 seconds
Started Jul 23 07:00:55 PM PDT 24
Finished Jul 23 07:08:21 PM PDT 24
Peak memory 201716 kb
Host smart-5e0fdfad-d5be-4004-ac36-d0cddcebb586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542069783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3542069783
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1371655472
Short name T748
Test name
Test status
Simulation time 39139361580 ps
CPU time 25.26 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:01:20 PM PDT 24
Peak memory 201076 kb
Host smart-9bd307ba-73ff-4d96-828d-e6f7dc722b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371655472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1371655472
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1984963709
Short name T548
Test name
Test status
Simulation time 5276746853 ps
CPU time 10.13 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:01:07 PM PDT 24
Peak memory 201072 kb
Host smart-d45c4cb9-636d-4fde-b48c-5072226a0b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984963709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1984963709
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2850031091
Short name T412
Test name
Test status
Simulation time 6117169597 ps
CPU time 7.8 seconds
Started Jul 23 07:00:44 PM PDT 24
Finished Jul 23 07:00:53 PM PDT 24
Peak memory 201132 kb
Host smart-785ddaf2-d364-4045-8a9d-741deac65aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850031091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2850031091
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2820512861
Short name T31
Test name
Test status
Simulation time 153587230158 ps
CPU time 146.4 seconds
Started Jul 23 07:00:42 PM PDT 24
Finished Jul 23 07:03:10 PM PDT 24
Peak memory 217532 kb
Host smart-a2266144-7213-45ff-8945-a5ecf70ba4fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820512861 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2820512861
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3731909107
Short name T619
Test name
Test status
Simulation time 497551923 ps
CPU time 0.97 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:00:59 PM PDT 24
Peak memory 201004 kb
Host smart-8db899ed-6e53-4980-bfb7-8f188dc2b1a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731909107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3731909107
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.4273779380
Short name T326
Test name
Test status
Simulation time 159610039584 ps
CPU time 59.4 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:01:57 PM PDT 24
Peak memory 201200 kb
Host smart-2664778a-8f2b-4713-a363-c7043de2dd75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273779380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.4273779380
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2573970859
Short name T303
Test name
Test status
Simulation time 165895965115 ps
CPU time 363.24 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:06:57 PM PDT 24
Peak memory 201232 kb
Host smart-03a9de97-5441-4a72-aa56-3b810e1aa1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573970859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2573970859
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1115250284
Short name T588
Test name
Test status
Simulation time 167048679111 ps
CPU time 363.11 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:07:00 PM PDT 24
Peak memory 201396 kb
Host smart-756e63fa-beb7-4cf8-8440-9e85db6ea0bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115250284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1115250284
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.230837323
Short name T7
Test name
Test status
Simulation time 504593277172 ps
CPU time 1138.66 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:19:55 PM PDT 24
Peak memory 201316 kb
Host smart-f8b36a41-852c-402b-939b-561cc3e83646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230837323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.230837323
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1710425370
Short name T394
Test name
Test status
Simulation time 490586853512 ps
CPU time 81.52 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:02:17 PM PDT 24
Peak memory 201228 kb
Host smart-bbf689b8-9533-48f5-986c-efd21cb1d2b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710425370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1710425370
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.968284659
Short name T197
Test name
Test status
Simulation time 199055732931 ps
CPU time 379.09 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:07:16 PM PDT 24
Peak memory 201232 kb
Host smart-cbff047d-5b04-4445-b128-d41cf010bc50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968284659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.968284659
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1394320266
Short name T378
Test name
Test status
Simulation time 402577492889 ps
CPU time 883.17 seconds
Started Jul 23 07:00:50 PM PDT 24
Finished Jul 23 07:15:34 PM PDT 24
Peak memory 201204 kb
Host smart-404d5d72-7ffc-40e7-9565-53a1da5fdf08
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394320266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1394320266
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.732428633
Short name T469
Test name
Test status
Simulation time 94161355201 ps
CPU time 310.5 seconds
Started Jul 23 07:00:55 PM PDT 24
Finished Jul 23 07:06:09 PM PDT 24
Peak memory 201484 kb
Host smart-d2fb015f-6fed-44eb-b0cf-0f8f1f6f7c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732428633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.732428633
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1142872745
Short name T756
Test name
Test status
Simulation time 32292502053 ps
CPU time 13.6 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:01:11 PM PDT 24
Peak memory 201012 kb
Host smart-e86f531f-db08-4aa1-a187-7c22efc4a7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142872745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1142872745
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2289680859
Short name T787
Test name
Test status
Simulation time 4700533554 ps
CPU time 3.67 seconds
Started Jul 23 07:00:48 PM PDT 24
Finished Jul 23 07:00:54 PM PDT 24
Peak memory 201072 kb
Host smart-5fa0d836-8e28-4fed-a86f-46b2d5b043cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289680859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2289680859
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2492554191
Short name T390
Test name
Test status
Simulation time 5865632822 ps
CPU time 3.97 seconds
Started Jul 23 07:00:49 PM PDT 24
Finished Jul 23 07:00:55 PM PDT 24
Peak memory 201056 kb
Host smart-c5a8b8b0-98a3-409e-9a56-1897d83ed367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492554191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2492554191
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2471948486
Short name T147
Test name
Test status
Simulation time 331583963144 ps
CPU time 805.82 seconds
Started Jul 23 07:00:55 PM PDT 24
Finished Jul 23 07:14:25 PM PDT 24
Peak memory 201152 kb
Host smart-293c3cb0-a38d-4dad-aed8-751f761ecca8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471948486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2471948486
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.821224104
Short name T700
Test name
Test status
Simulation time 28593532065 ps
CPU time 117.18 seconds
Started Jul 23 07:00:50 PM PDT 24
Finished Jul 23 07:02:49 PM PDT 24
Peak memory 209996 kb
Host smart-3e793def-8cf6-4051-a3e1-f9ad59d6a7e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821224104 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.821224104
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.145483134
Short name T608
Test name
Test status
Simulation time 538557540 ps
CPU time 0.88 seconds
Started Jul 23 07:00:57 PM PDT 24
Finished Jul 23 07:01:01 PM PDT 24
Peak memory 201104 kb
Host smart-98f7e6cf-7f48-4146-a946-7331471ee441
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145483134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.145483134
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.358664719
Short name T148
Test name
Test status
Simulation time 325787291497 ps
CPU time 792.68 seconds
Started Jul 23 07:00:57 PM PDT 24
Finished Jul 23 07:14:13 PM PDT 24
Peak memory 201332 kb
Host smart-ad6a1791-e25a-4a09-8f71-4c09362b0817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358664719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.358664719
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4050418245
Short name T137
Test name
Test status
Simulation time 165572326286 ps
CPU time 386.39 seconds
Started Jul 23 07:00:56 PM PDT 24
Finished Jul 23 07:07:25 PM PDT 24
Peak memory 201176 kb
Host smart-52a2d336-ea10-46d4-92c2-e0c1a810d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050418245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4050418245
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1734210891
Short name T600
Test name
Test status
Simulation time 497405788177 ps
CPU time 577.47 seconds
Started Jul 23 07:00:56 PM PDT 24
Finished Jul 23 07:10:37 PM PDT 24
Peak memory 201092 kb
Host smart-cdffa514-0765-4352-aa7c-9fbbfb39f756
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734210891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1734210891
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1511524678
Short name T695
Test name
Test status
Simulation time 164751698328 ps
CPU time 381.05 seconds
Started Jul 23 07:00:55 PM PDT 24
Finished Jul 23 07:07:20 PM PDT 24
Peak memory 201192 kb
Host smart-5d975dab-af59-4e23-9e74-12c6ba61bdb4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511524678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1511524678
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.363672089
Short name T190
Test name
Test status
Simulation time 639773190932 ps
CPU time 385.6 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:07:23 PM PDT 24
Peak memory 201212 kb
Host smart-0783ea6f-5f0a-433c-ad48-2c064d203cd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363672089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.363672089
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1963601991
Short name T566
Test name
Test status
Simulation time 580398747048 ps
CPU time 1206 seconds
Started Jul 23 07:00:56 PM PDT 24
Finished Jul 23 07:21:05 PM PDT 24
Peak memory 201088 kb
Host smart-ad6d0c4b-6fc2-48ae-8931-7766e5371c41
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963601991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1963601991
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4099988732
Short name T204
Test name
Test status
Simulation time 140668961229 ps
CPU time 715.11 seconds
Started Jul 23 07:00:58 PM PDT 24
Finished Jul 23 07:12:56 PM PDT 24
Peak memory 201772 kb
Host smart-f246e76d-dd2e-4afa-97cd-f927dc533f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099988732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4099988732
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.186196751
Short name T514
Test name
Test status
Simulation time 26553515196 ps
CPU time 16.69 seconds
Started Jul 23 07:00:57 PM PDT 24
Finished Jul 23 07:01:16 PM PDT 24
Peak memory 201164 kb
Host smart-cc9a29d0-0f71-4122-9f30-dbdc2ac836c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186196751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.186196751
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.281258785
Short name T549
Test name
Test status
Simulation time 5225732920 ps
CPU time 7.11 seconds
Started Jul 23 07:00:57 PM PDT 24
Finished Jul 23 07:01:07 PM PDT 24
Peak memory 201188 kb
Host smart-37ca134c-1442-4a0a-a889-8703cdd70a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281258785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.281258785
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.4094942952
Short name T632
Test name
Test status
Simulation time 6078426028 ps
CPU time 15.34 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:01:12 PM PDT 24
Peak memory 201068 kb
Host smart-aa251ba3-af26-4d60-a48e-6c03c27827b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094942952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.4094942952
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.4239090423
Short name T544
Test name
Test status
Simulation time 51356046046 ps
CPU time 13.3 seconds
Started Jul 23 07:00:55 PM PDT 24
Finished Jul 23 07:01:12 PM PDT 24
Peak memory 200936 kb
Host smart-9ae9d94f-1450-48d0-a511-70400945f7d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239090423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.4239090423
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2434857805
Short name T273
Test name
Test status
Simulation time 21443330247 ps
CPU time 57.43 seconds
Started Jul 23 07:00:57 PM PDT 24
Finished Jul 23 07:01:57 PM PDT 24
Peak memory 210040 kb
Host smart-0380069a-ff63-4870-9393-543c0281c9a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434857805 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2434857805
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2553087859
Short name T60
Test name
Test status
Simulation time 333632251 ps
CPU time 0.82 seconds
Started Jul 23 07:00:55 PM PDT 24
Finished Jul 23 07:01:00 PM PDT 24
Peak memory 201136 kb
Host smart-bcf60055-0687-44bc-ac2c-b16c81ff7e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553087859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2553087859
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1583333174
Short name T328
Test name
Test status
Simulation time 522459454683 ps
CPU time 251.65 seconds
Started Jul 23 07:00:47 PM PDT 24
Finished Jul 23 07:04:59 PM PDT 24
Peak memory 201296 kb
Host smart-c381c825-c163-494e-8877-97a9aa93a7ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583333174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1583333174
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1087203952
Short name T296
Test name
Test status
Simulation time 324011412312 ps
CPU time 194.42 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:04:11 PM PDT 24
Peak memory 201264 kb
Host smart-228cc96a-b681-4058-9d4b-040fd1b8b6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087203952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1087203952
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.335156315
Short name T306
Test name
Test status
Simulation time 331804345683 ps
CPU time 516.21 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:09:33 PM PDT 24
Peak memory 201244 kb
Host smart-dd43f9cf-c90f-447c-a554-b47ac06a3696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335156315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.335156315
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.981406680
Short name T393
Test name
Test status
Simulation time 332652689147 ps
CPU time 790.2 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:14:08 PM PDT 24
Peak memory 201240 kb
Host smart-e3b87610-fe4e-4a16-948b-3d68f7e00f44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=981406680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.981406680
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.108255220
Short name T265
Test name
Test status
Simulation time 331117335034 ps
CPU time 789.85 seconds
Started Jul 23 07:00:56 PM PDT 24
Finished Jul 23 07:14:09 PM PDT 24
Peak memory 201176 kb
Host smart-03f97b67-0416-4a2b-aab6-511ec690d2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108255220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.108255220
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2082303388
Short name T151
Test name
Test status
Simulation time 159822078588 ps
CPU time 370.41 seconds
Started Jul 23 07:00:51 PM PDT 24
Finished Jul 23 07:07:03 PM PDT 24
Peak memory 201244 kb
Host smart-cdb30b4e-7de2-4657-8c4a-51882a014d21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082303388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2082303388
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2963757581
Short name T297
Test name
Test status
Simulation time 178838354882 ps
CPU time 388.66 seconds
Started Jul 23 07:00:48 PM PDT 24
Finished Jul 23 07:07:17 PM PDT 24
Peak memory 201244 kb
Host smart-9b3ba29f-367d-4a16-9757-30c8cabf6d53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963757581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2963757581
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3183866661
Short name T152
Test name
Test status
Simulation time 396216490343 ps
CPU time 953.32 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:16:50 PM PDT 24
Peak memory 201252 kb
Host smart-28be1ecc-2e42-45bb-b55e-b4a317b41161
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183866661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3183866661
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4119386536
Short name T744
Test name
Test status
Simulation time 42191537398 ps
CPU time 21.97 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:01:18 PM PDT 24
Peak memory 201076 kb
Host smart-83251fa7-7e1a-460f-8139-c0641441b04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119386536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4119386536
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2393094036
Short name T722
Test name
Test status
Simulation time 5410323259 ps
CPU time 13 seconds
Started Jul 23 07:01:08 PM PDT 24
Finished Jul 23 07:01:23 PM PDT 24
Peak memory 201056 kb
Host smart-50f1069a-1249-4a8f-b618-d0d93d9ec141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393094036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2393094036
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3447962519
Short name T640
Test name
Test status
Simulation time 5812428602 ps
CPU time 3.54 seconds
Started Jul 23 07:00:57 PM PDT 24
Finished Jul 23 07:01:03 PM PDT 24
Peak memory 201140 kb
Host smart-a582668d-afed-4038-86ec-a127e0bddb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447962519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3447962519
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2618971110
Short name T593
Test name
Test status
Simulation time 196894068030 ps
CPU time 116.25 seconds
Started Jul 23 07:01:00 PM PDT 24
Finished Jul 23 07:02:58 PM PDT 24
Peak memory 201228 kb
Host smart-2a1cd0bb-15d8-4615-bbc3-8111ebeffd33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618971110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2618971110
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3909106709
Short name T726
Test name
Test status
Simulation time 322327693 ps
CPU time 0.77 seconds
Started Jul 23 07:01:03 PM PDT 24
Finished Jul 23 07:01:05 PM PDT 24
Peak memory 200896 kb
Host smart-4f52d2a4-eb44-49ec-9afe-f5c5f4326791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909106709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3909106709
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2900088575
Short name T255
Test name
Test status
Simulation time 184098624223 ps
CPU time 145.44 seconds
Started Jul 23 07:00:58 PM PDT 24
Finished Jul 23 07:03:26 PM PDT 24
Peak memory 201288 kb
Host smart-cf785de6-45b9-4e43-a8e7-c1d82fe65a60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900088575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2900088575
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.4260029678
Short name T295
Test name
Test status
Simulation time 501446647265 ps
CPU time 291.53 seconds
Started Jul 23 07:01:08 PM PDT 24
Finished Jul 23 07:06:02 PM PDT 24
Peak memory 201244 kb
Host smart-21ae2b8e-3387-4362-ba70-7349ee762e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260029678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.4260029678
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2830547668
Short name T243
Test name
Test status
Simulation time 161315082143 ps
CPU time 367.63 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:07:04 PM PDT 24
Peak memory 201300 kb
Host smart-c5c6bc28-5021-4b95-8f86-60d53cc02879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830547668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2830547668
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1182766494
Short name T363
Test name
Test status
Simulation time 169939304069 ps
CPU time 397.12 seconds
Started Jul 23 07:01:08 PM PDT 24
Finished Jul 23 07:07:47 PM PDT 24
Peak memory 201148 kb
Host smart-480d2ade-6154-4196-8b24-e522f764bdad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182766494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1182766494
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.88425781
Short name T770
Test name
Test status
Simulation time 162786567674 ps
CPU time 91.07 seconds
Started Jul 23 07:01:13 PM PDT 24
Finished Jul 23 07:02:46 PM PDT 24
Peak memory 201304 kb
Host smart-569f196e-7da7-4202-870d-7723c0d693e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88425781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.88425781
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1570536369
Short name T704
Test name
Test status
Simulation time 500506227376 ps
CPU time 580.95 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:10:38 PM PDT 24
Peak memory 201224 kb
Host smart-eb43d2ac-b09c-4e27-b20e-144dcaab7eeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570536369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1570536369
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2979870176
Short name T538
Test name
Test status
Simulation time 174030676103 ps
CPU time 104.55 seconds
Started Jul 23 07:00:51 PM PDT 24
Finished Jul 23 07:02:37 PM PDT 24
Peak memory 201228 kb
Host smart-45e04caf-62de-450c-800a-59abe10af7fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979870176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2979870176
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2620850428
Short name T701
Test name
Test status
Simulation time 614357835097 ps
CPU time 1416.8 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:24:31 PM PDT 24
Peak memory 201184 kb
Host smart-dd92b877-9571-41f7-810d-69edd13eb01d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620850428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2620850428
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2255308078
Short name T42
Test name
Test status
Simulation time 78003078620 ps
CPU time 307.32 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:06:03 PM PDT 24
Peak memory 201584 kb
Host smart-e161c55b-d50a-42f9-8a33-ca6adc44333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255308078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2255308078
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2672943809
Short name T357
Test name
Test status
Simulation time 44623478747 ps
CPU time 54.28 seconds
Started Jul 23 07:00:57 PM PDT 24
Finished Jul 23 07:01:54 PM PDT 24
Peak memory 201080 kb
Host smart-d5c540c8-88d2-49d1-bb12-5f0dff5761ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672943809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2672943809
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2463078689
Short name T381
Test name
Test status
Simulation time 4074249963 ps
CPU time 2.68 seconds
Started Jul 23 07:00:53 PM PDT 24
Finished Jul 23 07:00:59 PM PDT 24
Peak memory 201068 kb
Host smart-58b0faa7-3f4b-44b4-af05-5de3fed32e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463078689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2463078689
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2725497608
Short name T79
Test name
Test status
Simulation time 5783984161 ps
CPU time 14.2 seconds
Started Jul 23 07:01:08 PM PDT 24
Finished Jul 23 07:01:25 PM PDT 24
Peak memory 201064 kb
Host smart-52df2772-acb9-422a-9810-b1690b86dfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725497608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2725497608
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2525580044
Short name T696
Test name
Test status
Simulation time 181523682370 ps
CPU time 428.64 seconds
Started Jul 23 07:01:01 PM PDT 24
Finished Jul 23 07:08:10 PM PDT 24
Peak memory 201284 kb
Host smart-290d224c-2fc1-4985-9094-d06fa4a9f605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525580044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2525580044
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2719378322
Short name T17
Test name
Test status
Simulation time 129308344774 ps
CPU time 163.31 seconds
Started Jul 23 07:01:13 PM PDT 24
Finished Jul 23 07:03:58 PM PDT 24
Peak memory 210016 kb
Host smart-2195ed0e-52ed-45a6-9fbb-99970a45df74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719378322 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2719378322
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1515121429
Short name T441
Test name
Test status
Simulation time 441171867 ps
CPU time 1.6 seconds
Started Jul 23 06:59:57 PM PDT 24
Finished Jul 23 07:00:02 PM PDT 24
Peak memory 201024 kb
Host smart-3021bf45-aab2-491c-a60c-622244be3122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515121429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1515121429
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.12912374
Short name T767
Test name
Test status
Simulation time 177980765655 ps
CPU time 432.3 seconds
Started Jul 23 07:00:07 PM PDT 24
Finished Jul 23 07:07:20 PM PDT 24
Peak memory 201220 kb
Host smart-e603e2a1-a06b-4f67-8ee5-7b91527e10bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12912374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating
.12912374
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1747010430
Short name T268
Test name
Test status
Simulation time 340211443247 ps
CPU time 407.58 seconds
Started Jul 23 06:59:58 PM PDT 24
Finished Jul 23 07:06:48 PM PDT 24
Peak memory 201252 kb
Host smart-03a38b57-582d-4738-89d0-d1c54c3f02cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747010430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1747010430
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.185742886
Short name T160
Test name
Test status
Simulation time 494386108763 ps
CPU time 307.11 seconds
Started Jul 23 07:00:03 PM PDT 24
Finished Jul 23 07:05:11 PM PDT 24
Peak memory 201248 kb
Host smart-d6c05e8d-2da6-4ea3-91de-399870f876ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185742886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.185742886
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.655366566
Short name T499
Test name
Test status
Simulation time 499945084882 ps
CPU time 1227.58 seconds
Started Jul 23 06:59:56 PM PDT 24
Finished Jul 23 07:20:28 PM PDT 24
Peak memory 201172 kb
Host smart-32621f5d-cb33-474f-a14d-f81f311e15d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=655366566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.655366566
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3629818177
Short name T764
Test name
Test status
Simulation time 158384321122 ps
CPU time 177.5 seconds
Started Jul 23 06:59:56 PM PDT 24
Finished Jul 23 07:02:58 PM PDT 24
Peak memory 201196 kb
Host smart-a93c4266-b1f9-4e75-b629-a533cb2868af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629818177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3629818177
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.411659076
Short name T697
Test name
Test status
Simulation time 500727565348 ps
CPU time 1224.73 seconds
Started Jul 23 06:59:58 PM PDT 24
Finished Jul 23 07:20:26 PM PDT 24
Peak memory 201160 kb
Host smart-7d4d2ae6-d31f-4099-a8cb-98ddf8f0b293
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=411659076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.411659076
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.315164584
Short name T479
Test name
Test status
Simulation time 615490813842 ps
CPU time 333.46 seconds
Started Jul 23 07:00:05 PM PDT 24
Finished Jul 23 07:05:39 PM PDT 24
Peak memory 201232 kb
Host smart-2f55c284-13db-45ed-aae0-e25c5c036e3e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315164584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.315164584
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.846298249
Short name T351
Test name
Test status
Simulation time 98359523510 ps
CPU time 342.97 seconds
Started Jul 23 07:00:04 PM PDT 24
Finished Jul 23 07:05:48 PM PDT 24
Peak memory 201628 kb
Host smart-9f1e6a38-9dbc-413a-9612-3d6da6ddfa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846298249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.846298249
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3083446651
Short name T419
Test name
Test status
Simulation time 43854586391 ps
CPU time 101.33 seconds
Started Jul 23 06:59:56 PM PDT 24
Finished Jul 23 07:01:42 PM PDT 24
Peak memory 201008 kb
Host smart-92df5462-8fce-457d-8f33-a8c91a01a6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083446651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3083446651
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2040241058
Short name T753
Test name
Test status
Simulation time 4181131607 ps
CPU time 2.51 seconds
Started Jul 23 07:00:07 PM PDT 24
Finished Jul 23 07:00:11 PM PDT 24
Peak memory 201068 kb
Host smart-844e2adf-5e4e-4507-b687-3b246aec6290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040241058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2040241058
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.4011961433
Short name T56
Test name
Test status
Simulation time 7796958459 ps
CPU time 17.09 seconds
Started Jul 23 07:00:02 PM PDT 24
Finished Jul 23 07:00:20 PM PDT 24
Peak memory 218008 kb
Host smart-dcc5df1c-11bf-40a9-b7d2-dc602b447eff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011961433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.4011961433
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1537576591
Short name T578
Test name
Test status
Simulation time 5826183185 ps
CPU time 4.66 seconds
Started Jul 23 06:59:59 PM PDT 24
Finished Jul 23 07:00:06 PM PDT 24
Peak memory 200704 kb
Host smart-800c8dfa-0313-43bd-91ec-2b86db3c6d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537576591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1537576591
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.787450181
Short name T101
Test name
Test status
Simulation time 105227201477 ps
CPU time 221.59 seconds
Started Jul 23 06:59:59 PM PDT 24
Finished Jul 23 07:03:43 PM PDT 24
Peak memory 210824 kb
Host smart-56d4d49a-a0b3-48a6-bb15-77ad955161f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787450181 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.787450181
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1486771115
Short name T455
Test name
Test status
Simulation time 527591262 ps
CPU time 0.84 seconds
Started Jul 23 07:01:12 PM PDT 24
Finished Jul 23 07:01:14 PM PDT 24
Peak memory 201028 kb
Host smart-6e35fce7-1f4c-4339-a0ec-e71d99d55eaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486771115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1486771115
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2053350209
Short name T231
Test name
Test status
Simulation time 345470218699 ps
CPU time 721.76 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:12:56 PM PDT 24
Peak memory 201168 kb
Host smart-01dd3471-55ac-49a2-b1f5-8fbbba3967a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053350209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2053350209
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.503438775
Short name T93
Test name
Test status
Simulation time 168258322405 ps
CPU time 366.51 seconds
Started Jul 23 07:01:08 PM PDT 24
Finished Jul 23 07:07:17 PM PDT 24
Peak memory 201192 kb
Host smart-badd3c04-0e1a-4149-918a-b164549a7b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503438775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.503438775
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.518207177
Short name T396
Test name
Test status
Simulation time 164187399908 ps
CPU time 402.86 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:07:39 PM PDT 24
Peak memory 201292 kb
Host smart-9754b440-ee71-4e47-a7e7-c0fa69ae0dfa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=518207177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.518207177
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2200764570
Short name T431
Test name
Test status
Simulation time 162609722552 ps
CPU time 82.33 seconds
Started Jul 23 07:00:55 PM PDT 24
Finished Jul 23 07:02:21 PM PDT 24
Peak memory 201144 kb
Host smart-aa642266-e868-4587-b1ae-3c6327dd5148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200764570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2200764570
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2937613328
Short name T153
Test name
Test status
Simulation time 159020170827 ps
CPU time 209.9 seconds
Started Jul 23 07:00:54 PM PDT 24
Finished Jul 23 07:04:27 PM PDT 24
Peak memory 201208 kb
Host smart-50b1f871-d9e5-4696-87e1-46cc4961dba8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937613328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2937613328
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2531836010
Short name T187
Test name
Test status
Simulation time 409328965491 ps
CPU time 196.35 seconds
Started Jul 23 07:00:57 PM PDT 24
Finished Jul 23 07:04:16 PM PDT 24
Peak memory 201232 kb
Host smart-7080d097-cae3-4713-b42f-7669641871ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531836010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2531836010
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2505729367
Short name T638
Test name
Test status
Simulation time 127315000741 ps
CPU time 658.11 seconds
Started Jul 23 07:00:57 PM PDT 24
Finished Jul 23 07:11:58 PM PDT 24
Peak memory 201664 kb
Host smart-5361561b-a7ca-407e-bedc-4b9f5a93ba2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505729367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2505729367
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2236564303
Short name T470
Test name
Test status
Simulation time 48702920803 ps
CPU time 120.76 seconds
Started Jul 23 07:01:00 PM PDT 24
Finished Jul 23 07:03:02 PM PDT 24
Peak memory 201008 kb
Host smart-3be1ac80-9493-4b68-b8bf-6e006b9d6b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236564303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2236564303
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.232831550
Short name T500
Test name
Test status
Simulation time 4966486069 ps
CPU time 12.74 seconds
Started Jul 23 07:01:08 PM PDT 24
Finished Jul 23 07:01:23 PM PDT 24
Peak memory 201076 kb
Host smart-0a777e50-231a-4b32-9b0a-02378d615b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232831550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.232831550
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.395595074
Short name T755
Test name
Test status
Simulation time 5690741615 ps
CPU time 14.73 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:01:10 PM PDT 24
Peak memory 201072 kb
Host smart-780ba4ee-1326-46f8-8f67-f0e22e1e3763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395595074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.395595074
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3263416045
Short name T44
Test name
Test status
Simulation time 475196345806 ps
CPU time 1536.5 seconds
Started Jul 23 07:01:00 PM PDT 24
Finished Jul 23 07:26:38 PM PDT 24
Peak memory 209916 kb
Host smart-81810613-ad6a-419b-b75e-f1bd3e5c50b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263416045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3263416045
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1513887180
Short name T19
Test name
Test status
Simulation time 4405303397 ps
CPU time 10.95 seconds
Started Jul 23 07:00:59 PM PDT 24
Finished Jul 23 07:01:12 PM PDT 24
Peak memory 201220 kb
Host smart-965db6ef-784a-4ff5-bbf3-319b1212a089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513887180 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1513887180
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1570967791
Short name T451
Test name
Test status
Simulation time 537400242 ps
CPU time 1.22 seconds
Started Jul 23 07:01:06 PM PDT 24
Finished Jul 23 07:01:09 PM PDT 24
Peak memory 201036 kb
Host smart-663a663e-73f4-438f-b7f6-2e37a05430ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570967791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1570967791
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1548305426
Short name T292
Test name
Test status
Simulation time 447064339132 ps
CPU time 966.59 seconds
Started Jul 23 07:00:59 PM PDT 24
Finished Jul 23 07:17:07 PM PDT 24
Peak memory 201164 kb
Host smart-4f3a2ecd-e557-4c46-85b9-742521146a38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548305426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1548305426
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2271887559
Short name T139
Test name
Test status
Simulation time 494204329065 ps
CPU time 1165.77 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:20:43 PM PDT 24
Peak memory 201304 kb
Host smart-37fb7e4c-8c81-4029-9711-8deca7ac26e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271887559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2271887559
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1411254648
Short name T377
Test name
Test status
Simulation time 166378335614 ps
CPU time 179.27 seconds
Started Jul 23 07:01:02 PM PDT 24
Finished Jul 23 07:04:02 PM PDT 24
Peak memory 201196 kb
Host smart-4df522ea-4c92-4c14-a3be-4d12da3871b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411254648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1411254648
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2287612720
Short name T182
Test name
Test status
Simulation time 487942216796 ps
CPU time 183.86 seconds
Started Jul 23 07:00:52 PM PDT 24
Finished Jul 23 07:03:58 PM PDT 24
Peak memory 201244 kb
Host smart-499fc003-66d4-4b85-897c-a049e612641c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287612720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2287612720
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1697328561
Short name T439
Test name
Test status
Simulation time 324297203823 ps
CPU time 406.6 seconds
Started Jul 23 07:01:13 PM PDT 24
Finished Jul 23 07:08:01 PM PDT 24
Peak memory 201220 kb
Host smart-2b78bc75-4781-4649-a31a-a147a8c3da12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697328561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1697328561
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2537814518
Short name T505
Test name
Test status
Simulation time 298406709960 ps
CPU time 326.57 seconds
Started Jul 23 07:01:04 PM PDT 24
Finished Jul 23 07:06:31 PM PDT 24
Peak memory 201248 kb
Host smart-a4f91ca2-6e06-412b-a22b-57ea4b4a2f05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537814518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2537814518
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1549427742
Short name T572
Test name
Test status
Simulation time 594181944652 ps
CPU time 1442.28 seconds
Started Jul 23 07:01:00 PM PDT 24
Finished Jul 23 07:25:04 PM PDT 24
Peak memory 201240 kb
Host smart-2e05a7fb-f31d-4cc3-b740-0b1580886b6d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549427742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1549427742
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.672515084
Short name T546
Test name
Test status
Simulation time 32448020226 ps
CPU time 28.64 seconds
Started Jul 23 07:01:19 PM PDT 24
Finished Jul 23 07:01:49 PM PDT 24
Peak memory 201072 kb
Host smart-803084d6-b5da-4159-8077-a2215cdec233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672515084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.672515084
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.41907434
Short name T658
Test name
Test status
Simulation time 3973998804 ps
CPU time 9.59 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:01:27 PM PDT 24
Peak memory 201076 kb
Host smart-4aa97db1-f150-4a07-8e0c-ff97635eac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41907434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.41907434
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3430549819
Short name T440
Test name
Test status
Simulation time 5705116037 ps
CPU time 3.85 seconds
Started Jul 23 07:01:08 PM PDT 24
Finished Jul 23 07:01:14 PM PDT 24
Peak memory 201104 kb
Host smart-dca6295c-1ac4-4d13-98bc-080f05090bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430549819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3430549819
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.4028706469
Short name T571
Test name
Test status
Simulation time 6513869593 ps
CPU time 16.19 seconds
Started Jul 23 07:01:14 PM PDT 24
Finished Jul 23 07:01:32 PM PDT 24
Peak memory 201080 kb
Host smart-14173809-f24b-42dc-a439-b5afa0d67fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028706469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.4028706469
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3027668546
Short name T16
Test name
Test status
Simulation time 225283248093 ps
CPU time 467.92 seconds
Started Jul 23 07:01:08 PM PDT 24
Finished Jul 23 07:08:58 PM PDT 24
Peak memory 209960 kb
Host smart-180ac9ce-3671-413f-9c42-f54796bbc91c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027668546 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3027668546
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2307973734
Short name T769
Test name
Test status
Simulation time 385592198 ps
CPU time 1.02 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:01:18 PM PDT 24
Peak memory 201020 kb
Host smart-e2638197-f310-40f2-831f-fec726eaaab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307973734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2307973734
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3646262509
Short name T594
Test name
Test status
Simulation time 377124685364 ps
CPU time 437.08 seconds
Started Jul 23 07:01:17 PM PDT 24
Finished Jul 23 07:08:36 PM PDT 24
Peak memory 201212 kb
Host smart-e241f32f-292f-4520-992d-936509a21ed4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646262509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3646262509
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1781056892
Short name T667
Test name
Test status
Simulation time 516836809473 ps
CPU time 290.36 seconds
Started Jul 23 07:01:17 PM PDT 24
Finished Jul 23 07:06:09 PM PDT 24
Peak memory 201236 kb
Host smart-dc75f2e7-efe9-45e9-a727-657c3bd658ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781056892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1781056892
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.4273783699
Short name T747
Test name
Test status
Simulation time 333303794801 ps
CPU time 195.36 seconds
Started Jul 23 07:01:19 PM PDT 24
Finished Jul 23 07:04:35 PM PDT 24
Peak memory 201232 kb
Host smart-d5e62a96-029c-416a-9707-6a176aab3eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273783699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.4273783699
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1493245410
Short name T410
Test name
Test status
Simulation time 324931877650 ps
CPU time 749.82 seconds
Started Jul 23 07:01:11 PM PDT 24
Finished Jul 23 07:13:42 PM PDT 24
Peak memory 201288 kb
Host smart-73bfbea9-2958-4daf-873f-d6301ea92038
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493245410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1493245410
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.111073747
Short name T227
Test name
Test status
Simulation time 330397349791 ps
CPU time 745.72 seconds
Started Jul 23 07:01:05 PM PDT 24
Finished Jul 23 07:13:32 PM PDT 24
Peak memory 201252 kb
Host smart-dd3d4d76-c624-49ba-a51e-9726fbd122a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111073747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.111073747
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1359513510
Short name T661
Test name
Test status
Simulation time 326249740932 ps
CPU time 278.15 seconds
Started Jul 23 07:01:00 PM PDT 24
Finished Jul 23 07:05:40 PM PDT 24
Peak memory 201240 kb
Host smart-e846206b-4705-414b-b60a-4b3297817456
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359513510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1359513510
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1602837171
Short name T178
Test name
Test status
Simulation time 548147645962 ps
CPU time 225.08 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:05:02 PM PDT 24
Peak memory 201236 kb
Host smart-7f75a845-1788-4feb-a33b-f59d4f7f1fb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602837171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1602837171
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.317521605
Short name T557
Test name
Test status
Simulation time 581680736163 ps
CPU time 1337.14 seconds
Started Jul 23 07:01:06 PM PDT 24
Finished Jul 23 07:23:25 PM PDT 24
Peak memory 200556 kb
Host smart-11e1eea3-ce5e-4fdc-a2ed-59d5fcf77eb1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317521605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.317521605
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2424874519
Short name T502
Test name
Test status
Simulation time 134562476669 ps
CPU time 454.51 seconds
Started Jul 23 07:01:04 PM PDT 24
Finished Jul 23 07:08:39 PM PDT 24
Peak memory 201716 kb
Host smart-b5df3463-19d3-416e-9e21-7d134c1c9674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424874519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2424874519
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1751942161
Short name T682
Test name
Test status
Simulation time 29893481536 ps
CPU time 66.55 seconds
Started Jul 23 07:01:09 PM PDT 24
Finished Jul 23 07:02:17 PM PDT 24
Peak memory 201044 kb
Host smart-cd3baea9-f9b3-4c8b-80db-a60ba9da9bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751942161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1751942161
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2519439343
Short name T772
Test name
Test status
Simulation time 3192846445 ps
CPU time 2.31 seconds
Started Jul 23 07:01:17 PM PDT 24
Finished Jul 23 07:01:21 PM PDT 24
Peak memory 201052 kb
Host smart-e538608e-241a-4fad-9767-329966d79e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519439343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2519439343
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.4017929432
Short name T786
Test name
Test status
Simulation time 5660609879 ps
CPU time 4.12 seconds
Started Jul 23 07:01:06 PM PDT 24
Finished Jul 23 07:01:12 PM PDT 24
Peak memory 200428 kb
Host smart-659c3d5d-b99d-4abc-9b6a-d1420196b4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017929432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.4017929432
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.897994547
Short name T262
Test name
Test status
Simulation time 400389137289 ps
CPU time 988.89 seconds
Started Jul 23 07:01:02 PM PDT 24
Finished Jul 23 07:17:32 PM PDT 24
Peak memory 201328 kb
Host smart-ea599cc6-697b-4c2c-9371-1ec789dff0b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897994547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
897994547
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1213838891
Short name T34
Test name
Test status
Simulation time 25623721792 ps
CPU time 20.88 seconds
Started Jul 23 07:01:17 PM PDT 24
Finished Jul 23 07:01:40 PM PDT 24
Peak memory 210940 kb
Host smart-e10534a7-14cc-40e5-b4c0-18483a83467a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213838891 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1213838891
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.917423587
Short name T448
Test name
Test status
Simulation time 327122701 ps
CPU time 0.69 seconds
Started Jul 23 07:01:06 PM PDT 24
Finished Jul 23 07:01:07 PM PDT 24
Peak memory 201044 kb
Host smart-c6bee0ae-dd33-446f-86e9-a4086400f0b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917423587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.917423587
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2756787385
Short name T527
Test name
Test status
Simulation time 164517845821 ps
CPU time 339.25 seconds
Started Jul 23 07:01:17 PM PDT 24
Finished Jul 23 07:06:58 PM PDT 24
Peak memory 201288 kb
Host smart-13caf0f3-514e-41a0-adeb-abedca3f2e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756787385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2756787385
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3059714863
Short name T270
Test name
Test status
Simulation time 332592296041 ps
CPU time 722.55 seconds
Started Jul 23 07:00:59 PM PDT 24
Finished Jul 23 07:13:03 PM PDT 24
Peak memory 201300 kb
Host smart-d2e80d52-dd5a-4098-a6d0-e202413c806b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059714863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3059714863
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2597546472
Short name T80
Test name
Test status
Simulation time 322575007398 ps
CPU time 799.1 seconds
Started Jul 23 07:01:18 PM PDT 24
Finished Jul 23 07:14:39 PM PDT 24
Peak memory 201204 kb
Host smart-47ae763e-6936-4e87-bede-9e0c0bee00b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597546472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2597546472
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.746052724
Short name T397
Test name
Test status
Simulation time 325034761412 ps
CPU time 391.01 seconds
Started Jul 23 07:01:13 PM PDT 24
Finished Jul 23 07:07:45 PM PDT 24
Peak memory 201236 kb
Host smart-ca209e6e-3ac8-4261-b973-cf6218d20ebb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=746052724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.746052724
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2064687616
Short name T516
Test name
Test status
Simulation time 182216807798 ps
CPU time 222.36 seconds
Started Jul 23 07:01:14 PM PDT 24
Finished Jul 23 07:04:59 PM PDT 24
Peak memory 201304 kb
Host smart-3fa9ad27-ca7a-4c15-b2ff-a8550dc037e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064687616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2064687616
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3242371881
Short name T735
Test name
Test status
Simulation time 612173340055 ps
CPU time 274.36 seconds
Started Jul 23 07:01:17 PM PDT 24
Finished Jul 23 07:05:53 PM PDT 24
Peak memory 201224 kb
Host smart-ed6645cf-d7b3-414c-948f-f0fe8d1774d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242371881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3242371881
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2060640625
Short name T207
Test name
Test status
Simulation time 111652342593 ps
CPU time 610.94 seconds
Started Jul 23 07:01:14 PM PDT 24
Finished Jul 23 07:11:27 PM PDT 24
Peak memory 201736 kb
Host smart-75788441-575a-41a1-bbc0-10eff71f2cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060640625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2060640625
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1359160178
Short name T603
Test name
Test status
Simulation time 45157732974 ps
CPU time 97.29 seconds
Started Jul 23 07:01:05 PM PDT 24
Finished Jul 23 07:02:43 PM PDT 24
Peak memory 200992 kb
Host smart-4b7003aa-a66a-4371-ba1c-906f59733c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359160178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1359160178
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2961077998
Short name T730
Test name
Test status
Simulation time 4304805741 ps
CPU time 2.29 seconds
Started Jul 23 07:01:06 PM PDT 24
Finished Jul 23 07:01:09 PM PDT 24
Peak memory 201072 kb
Host smart-a96188d7-95a6-428f-85d2-6bc505f73f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961077998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2961077998
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3658509248
Short name T585
Test name
Test status
Simulation time 6048857636 ps
CPU time 14.52 seconds
Started Jul 23 07:01:14 PM PDT 24
Finished Jul 23 07:01:31 PM PDT 24
Peak memory 201076 kb
Host smart-77b2a318-1145-4847-b507-752def679d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658509248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3658509248
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.4218146235
Short name T75
Test name
Test status
Simulation time 172975662257 ps
CPU time 392.52 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:07:50 PM PDT 24
Peak memory 201212 kb
Host smart-d79e3bcc-2c19-4e62-a6e2-8e2422b724a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218146235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.4218146235
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1318030085
Short name T729
Test name
Test status
Simulation time 12018764941 ps
CPU time 27.99 seconds
Started Jul 23 07:01:07 PM PDT 24
Finished Jul 23 07:01:37 PM PDT 24
Peak memory 201340 kb
Host smart-9bfe2441-105e-45a2-9b8b-2d00ebed9686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318030085 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1318030085
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.601228247
Short name T458
Test name
Test status
Simulation time 480925257 ps
CPU time 1.66 seconds
Started Jul 23 07:01:18 PM PDT 24
Finished Jul 23 07:01:21 PM PDT 24
Peak memory 201020 kb
Host smart-1fda29df-1707-486b-883c-583a314c9a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601228247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.601228247
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1542000073
Short name T746
Test name
Test status
Simulation time 163286662355 ps
CPU time 368.4 seconds
Started Jul 23 07:01:06 PM PDT 24
Finished Jul 23 07:07:16 PM PDT 24
Peak memory 201216 kb
Host smart-e857ee15-d2e7-4a77-9152-b5e696f910bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542000073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1542000073
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.208170546
Short name T720
Test name
Test status
Simulation time 169744991587 ps
CPU time 92.54 seconds
Started Jul 23 07:01:05 PM PDT 24
Finished Jul 23 07:02:39 PM PDT 24
Peak memory 201196 kb
Host smart-75f84d3f-f020-43fd-a79a-e8c49f6e743f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208170546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.208170546
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.545467268
Short name T392
Test name
Test status
Simulation time 160587156244 ps
CPU time 201.1 seconds
Started Jul 23 07:01:07 PM PDT 24
Finished Jul 23 07:04:30 PM PDT 24
Peak memory 201280 kb
Host smart-17d74b00-31fd-4ba3-924a-623f48c5ccf2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=545467268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.545467268
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.612545062
Short name T236
Test name
Test status
Simulation time 486702319301 ps
CPU time 508.69 seconds
Started Jul 23 07:01:06 PM PDT 24
Finished Jul 23 07:09:37 PM PDT 24
Peak memory 201296 kb
Host smart-a2158c41-7b9a-4b00-8717-d9733cbd347c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612545062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.612545062
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.256975638
Short name T793
Test name
Test status
Simulation time 313143946974 ps
CPU time 710.68 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:13:08 PM PDT 24
Peak memory 201156 kb
Host smart-9f0de48f-5d10-4e86-806f-3c37b5ac2882
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=256975638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.256975638
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3367447515
Short name T314
Test name
Test status
Simulation time 186591522298 ps
CPU time 115.76 seconds
Started Jul 23 07:01:06 PM PDT 24
Finished Jul 23 07:03:03 PM PDT 24
Peak memory 201208 kb
Host smart-41ad7633-39f2-4b49-9a45-f7a5f5803a5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367447515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3367447515
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3701933076
Short name T639
Test name
Test status
Simulation time 601142877171 ps
CPU time 360.48 seconds
Started Jul 23 07:01:19 PM PDT 24
Finished Jul 23 07:07:20 PM PDT 24
Peak memory 201232 kb
Host smart-4f911b03-947c-4838-8cf5-2ac279d108d5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701933076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3701933076
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.159987347
Short name T791
Test name
Test status
Simulation time 80470833610 ps
CPU time 324.16 seconds
Started Jul 23 07:01:08 PM PDT 24
Finished Jul 23 07:06:34 PM PDT 24
Peak memory 201740 kb
Host smart-5e8c88a0-ae55-431a-ae08-938dc9f1970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159987347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.159987347
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2681156936
Short name T103
Test name
Test status
Simulation time 40001142427 ps
CPU time 50.59 seconds
Started Jul 23 07:01:18 PM PDT 24
Finished Jul 23 07:02:10 PM PDT 24
Peak memory 201080 kb
Host smart-e336acea-5f50-4e5c-8f40-00df4f61ac00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681156936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2681156936
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2202180011
Short name T609
Test name
Test status
Simulation time 4579712822 ps
CPU time 2.45 seconds
Started Jul 23 07:01:17 PM PDT 24
Finished Jul 23 07:01:21 PM PDT 24
Peak memory 201060 kb
Host smart-4926b134-2473-4d2d-846f-2a1bd565f65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202180011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2202180011
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3058328190
Short name T601
Test name
Test status
Simulation time 5828222454 ps
CPU time 8.33 seconds
Started Jul 23 07:01:08 PM PDT 24
Finished Jul 23 07:01:18 PM PDT 24
Peak memory 201108 kb
Host smart-8d281f02-d661-45e6-86b0-9a80fa41f2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058328190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3058328190
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2956648427
Short name T212
Test name
Test status
Simulation time 274861998726 ps
CPU time 933.13 seconds
Started Jul 23 07:01:06 PM PDT 24
Finished Jul 23 07:16:41 PM PDT 24
Peak memory 217984 kb
Host smart-d7f8f94a-8733-4fb2-9ad0-d73aaf55c71f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956648427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2956648427
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3042996102
Short name T61
Test name
Test status
Simulation time 288892675 ps
CPU time 1.3 seconds
Started Jul 23 07:01:28 PM PDT 24
Finished Jul 23 07:01:31 PM PDT 24
Peak memory 201020 kb
Host smart-65c5f9ac-c2bb-4d42-8fb1-3be79c7d74fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042996102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3042996102
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3518112690
Short name T511
Test name
Test status
Simulation time 400017891775 ps
CPU time 91.81 seconds
Started Jul 23 07:01:06 PM PDT 24
Finished Jul 23 07:02:39 PM PDT 24
Peak memory 201152 kb
Host smart-f68194cb-2959-4974-aef9-be22651d6344
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518112690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3518112690
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3765081774
Short name T734
Test name
Test status
Simulation time 491798163329 ps
CPU time 1078.13 seconds
Started Jul 23 07:01:06 PM PDT 24
Finished Jul 23 07:19:06 PM PDT 24
Peak memory 201116 kb
Host smart-ae2197a9-b537-4389-bab9-65c21871565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765081774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3765081774
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1595199556
Short name T673
Test name
Test status
Simulation time 494367475899 ps
CPU time 180.69 seconds
Started Jul 23 07:01:07 PM PDT 24
Finished Jul 23 07:04:10 PM PDT 24
Peak memory 201196 kb
Host smart-089165ce-a161-40cb-92e9-736f226948dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595199556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1595199556
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2818002669
Short name T198
Test name
Test status
Simulation time 328031338117 ps
CPU time 162.25 seconds
Started Jul 23 07:01:13 PM PDT 24
Finished Jul 23 07:03:56 PM PDT 24
Peak memory 201152 kb
Host smart-8c947ce8-f184-4cab-bbb1-ab5978dc38b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818002669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2818002669
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2842192483
Short name T383
Test name
Test status
Simulation time 324368096509 ps
CPU time 349.54 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:07:08 PM PDT 24
Peak memory 201212 kb
Host smart-f96e3192-171e-431f-bf79-ddae9f3646ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842192483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2842192483
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2248768891
Short name T605
Test name
Test status
Simulation time 456991691115 ps
CPU time 530.11 seconds
Started Jul 23 07:01:07 PM PDT 24
Finished Jul 23 07:09:59 PM PDT 24
Peak memory 201244 kb
Host smart-f6a91382-818b-45d8-99b5-326e5ca6ba3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248768891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2248768891
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.887659026
Short name T501
Test name
Test status
Simulation time 410426978358 ps
CPU time 246.65 seconds
Started Jul 23 07:01:07 PM PDT 24
Finished Jul 23 07:05:16 PM PDT 24
Peak memory 201260 kb
Host smart-9e372e00-45a4-44e7-9525-9da1721dc401
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887659026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.887659026
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1000339042
Short name T214
Test name
Test status
Simulation time 133756948088 ps
CPU time 615.91 seconds
Started Jul 23 07:01:14 PM PDT 24
Finished Jul 23 07:11:33 PM PDT 24
Peak memory 201596 kb
Host smart-3a485736-3281-4981-aa50-903c098fa670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000339042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1000339042
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.653076006
Short name T532
Test name
Test status
Simulation time 28099028961 ps
CPU time 10.79 seconds
Started Jul 23 07:01:13 PM PDT 24
Finished Jul 23 07:01:25 PM PDT 24
Peak memory 201088 kb
Host smart-c083834e-1951-4212-b989-e3b7692fe12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653076006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.653076006
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.938003760
Short name T358
Test name
Test status
Simulation time 4634105935 ps
CPU time 3.47 seconds
Started Jul 23 07:01:14 PM PDT 24
Finished Jul 23 07:01:19 PM PDT 24
Peak memory 201072 kb
Host smart-54b8b5d2-087e-40e7-a47f-709da16c7b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938003760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.938003760
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1146505573
Short name T582
Test name
Test status
Simulation time 5715304127 ps
CPU time 7.78 seconds
Started Jul 23 07:01:07 PM PDT 24
Finished Jul 23 07:01:16 PM PDT 24
Peak memory 201292 kb
Host smart-fc37e692-e9b0-4d81-999a-163314079154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146505573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1146505573
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3774673845
Short name T560
Test name
Test status
Simulation time 203142552408 ps
CPU time 479.37 seconds
Started Jul 23 07:01:17 PM PDT 24
Finished Jul 23 07:09:18 PM PDT 24
Peak memory 201256 kb
Host smart-dd527ebb-b69b-4331-8019-c8fc98649259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774673845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3774673845
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2848859510
Short name T22
Test name
Test status
Simulation time 54932673919 ps
CPU time 32.99 seconds
Started Jul 23 07:01:14 PM PDT 24
Finished Jul 23 07:01:49 PM PDT 24
Peak memory 201356 kb
Host smart-357f42c9-a402-4a20-b914-1df360fa57a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848859510 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2848859510
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3641843727
Short name T428
Test name
Test status
Simulation time 339723031 ps
CPU time 0.85 seconds
Started Jul 23 07:01:28 PM PDT 24
Finished Jul 23 07:01:30 PM PDT 24
Peak memory 201020 kb
Host smart-4b39da1b-20d2-445a-a2cc-2339b07dcd7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641843727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3641843727
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.4009750191
Short name T241
Test name
Test status
Simulation time 330076713728 ps
CPU time 197.82 seconds
Started Jul 23 07:01:12 PM PDT 24
Finished Jul 23 07:04:31 PM PDT 24
Peak memory 201212 kb
Host smart-442d5b93-f46d-4b3d-bf8a-30fb2f4724e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009750191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.4009750191
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.4192699008
Short name T453
Test name
Test status
Simulation time 334830028921 ps
CPU time 383.95 seconds
Started Jul 23 07:01:14 PM PDT 24
Finished Jul 23 07:07:40 PM PDT 24
Peak memory 201256 kb
Host smart-826c32c5-c531-4dc4-9220-c46efc9dc218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192699008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.4192699008
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3366604772
Short name T741
Test name
Test status
Simulation time 167745415493 ps
CPU time 190.98 seconds
Started Jul 23 07:01:29 PM PDT 24
Finished Jul 23 07:04:41 PM PDT 24
Peak memory 201196 kb
Host smart-11b407dc-fa03-4565-87f6-5c9b65401c2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366604772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3366604772
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.4048874159
Short name T143
Test name
Test status
Simulation time 492746708479 ps
CPU time 1010.33 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:18:07 PM PDT 24
Peak memory 201280 kb
Host smart-5a840587-2dba-4669-a060-71a885afcb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048874159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.4048874159
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1809836264
Short name T364
Test name
Test status
Simulation time 501602026993 ps
CPU time 96.48 seconds
Started Jul 23 07:01:29 PM PDT 24
Finished Jul 23 07:03:07 PM PDT 24
Peak memory 201224 kb
Host smart-daba4dba-5cf6-4e80-8ef4-3c5434c5859f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809836264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1809836264
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1492645882
Short name T195
Test name
Test status
Simulation time 589974980361 ps
CPU time 89.05 seconds
Started Jul 23 07:01:22 PM PDT 24
Finished Jul 23 07:02:52 PM PDT 24
Peak memory 201252 kb
Host smart-26b1b8db-e9a1-427d-bf1c-b4d73d723dd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492645882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1492645882
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.498815723
Short name T584
Test name
Test status
Simulation time 201536593829 ps
CPU time 481.47 seconds
Started Jul 23 07:01:14 PM PDT 24
Finished Jul 23 07:09:16 PM PDT 24
Peak memory 201168 kb
Host smart-f9213183-ee2e-4898-bb81-671e1428e822
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498815723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.498815723
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3453383714
Short name T205
Test name
Test status
Simulation time 94423955712 ps
CPU time 317.42 seconds
Started Jul 23 07:01:16 PM PDT 24
Finished Jul 23 07:06:36 PM PDT 24
Peak memory 201604 kb
Host smart-9adddeba-36c1-4040-87af-e85a3d1aa283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453383714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3453383714
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1088597700
Short name T369
Test name
Test status
Simulation time 31177213928 ps
CPU time 18.59 seconds
Started Jul 23 07:01:30 PM PDT 24
Finished Jul 23 07:01:49 PM PDT 24
Peak memory 201092 kb
Host smart-9483e91a-1ce0-419d-85a9-1b3a27b710b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088597700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1088597700
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1026289688
Short name T482
Test name
Test status
Simulation time 3169243708 ps
CPU time 2.53 seconds
Started Jul 23 07:01:28 PM PDT 24
Finished Jul 23 07:01:32 PM PDT 24
Peak memory 201080 kb
Host smart-9b8be97d-50fe-48ab-b62b-1b7021f1d78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026289688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1026289688
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.4100520427
Short name T659
Test name
Test status
Simulation time 6076354488 ps
CPU time 9.82 seconds
Started Jul 23 07:01:16 PM PDT 24
Finished Jul 23 07:01:28 PM PDT 24
Peak memory 201036 kb
Host smart-a2b78130-ba6e-46b2-865c-94db84448d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100520427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.4100520427
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.755835893
Short name T739
Test name
Test status
Simulation time 45970709106 ps
CPU time 30.35 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:01:47 PM PDT 24
Peak memory 201140 kb
Host smart-78bd1848-bb27-4c56-b4ff-56d71b4b3078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755835893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
755835893
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.766195896
Short name T617
Test name
Test status
Simulation time 439381413 ps
CPU time 1.07 seconds
Started Jul 23 07:01:29 PM PDT 24
Finished Jul 23 07:01:32 PM PDT 24
Peak memory 201028 kb
Host smart-7f947eda-ba06-42c6-ae7d-f0b6f0326905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766195896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.766195896
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.193121942
Short name T547
Test name
Test status
Simulation time 330701592805 ps
CPU time 758.24 seconds
Started Jul 23 07:01:29 PM PDT 24
Finished Jul 23 07:14:09 PM PDT 24
Peak memory 201228 kb
Host smart-9afd8fd9-9404-4a53-b57a-5a0d0ad63701
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193121942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.193121942
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3565765289
Short name T309
Test name
Test status
Simulation time 165236024875 ps
CPU time 355.67 seconds
Started Jul 23 07:01:30 PM PDT 24
Finished Jul 23 07:07:26 PM PDT 24
Peak memory 201304 kb
Host smart-c46fb210-d0db-4e2c-89a8-cba2b8c8b24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565765289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3565765289
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.63113229
Short name T524
Test name
Test status
Simulation time 163909498375 ps
CPU time 92.61 seconds
Started Jul 23 07:01:18 PM PDT 24
Finished Jul 23 07:02:52 PM PDT 24
Peak memory 201232 kb
Host smart-8f62c947-fae6-4ca8-8ece-c5658d98146b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=63113229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt
_fixed.63113229
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.762831430
Short name T325
Test name
Test status
Simulation time 494843888345 ps
CPU time 615.14 seconds
Started Jul 23 07:01:14 PM PDT 24
Finished Jul 23 07:11:31 PM PDT 24
Peak memory 201252 kb
Host smart-b9c6d716-7e5d-4ef0-bff3-898a14384631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762831430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.762831430
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1247182443
Short name T454
Test name
Test status
Simulation time 324757389201 ps
CPU time 92.25 seconds
Started Jul 23 07:01:18 PM PDT 24
Finished Jul 23 07:02:52 PM PDT 24
Peak memory 201236 kb
Host smart-7581e2cc-6f5e-4bb8-91b6-e184ea1fdac0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247182443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1247182443
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.842131052
Short name T244
Test name
Test status
Simulation time 171020237269 ps
CPU time 92.34 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:02:50 PM PDT 24
Peak memory 201212 kb
Host smart-1eb2434f-40f0-4597-88ca-dddc17599292
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842131052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.842131052
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3096951692
Short name T449
Test name
Test status
Simulation time 603882671702 ps
CPU time 1070.34 seconds
Started Jul 23 07:01:28 PM PDT 24
Finished Jul 23 07:19:19 PM PDT 24
Peak memory 201220 kb
Host smart-200125c4-ecd8-42f9-893d-8c33790405f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096951692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3096951692
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3145361756
Short name T583
Test name
Test status
Simulation time 106726211571 ps
CPU time 290.21 seconds
Started Jul 23 07:01:28 PM PDT 24
Finished Jul 23 07:06:19 PM PDT 24
Peak memory 201664 kb
Host smart-ba38b893-5087-4b34-8151-d29165a695f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145361756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3145361756
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1404127953
Short name T687
Test name
Test status
Simulation time 27200297872 ps
CPU time 14.91 seconds
Started Jul 23 07:01:28 PM PDT 24
Finished Jul 23 07:01:44 PM PDT 24
Peak memory 201060 kb
Host smart-e4a395af-85ae-4add-aae1-660184498691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404127953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1404127953
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3109578938
Short name T464
Test name
Test status
Simulation time 4934489437 ps
CPU time 3.65 seconds
Started Jul 23 07:01:18 PM PDT 24
Finished Jul 23 07:01:23 PM PDT 24
Peak memory 201088 kb
Host smart-d28f50ce-d429-4c47-876b-259d7d4e6e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109578938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3109578938
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2156393346
Short name T471
Test name
Test status
Simulation time 5789948517 ps
CPU time 7.11 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:01:25 PM PDT 24
Peak memory 201108 kb
Host smart-a8dab7fa-4573-4db1-8352-83a97b9468e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156393346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2156393346
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1475654309
Short name T553
Test name
Test status
Simulation time 50227658536 ps
CPU time 29.77 seconds
Started Jul 23 07:01:18 PM PDT 24
Finished Jul 23 07:01:49 PM PDT 24
Peak memory 201148 kb
Host smart-0939f218-a689-4ce6-a664-b402d86503fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475654309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1475654309
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.664340865
Short name T83
Test name
Test status
Simulation time 84118920420 ps
CPU time 82.54 seconds
Started Jul 23 07:01:15 PM PDT 24
Finished Jul 23 07:02:40 PM PDT 24
Peak memory 209636 kb
Host smart-e98108cb-b872-4569-aa97-77f990caaee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664340865 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.664340865
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2334038409
Short name T438
Test name
Test status
Simulation time 338380063 ps
CPU time 0.78 seconds
Started Jul 23 07:01:21 PM PDT 24
Finished Jul 23 07:01:22 PM PDT 24
Peak memory 201036 kb
Host smart-0656e1d2-777b-4b96-830d-13f00ac1a7e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334038409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2334038409
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2595922502
Short name T308
Test name
Test status
Simulation time 339581460859 ps
CPU time 429.48 seconds
Started Jul 23 07:01:24 PM PDT 24
Finished Jul 23 07:08:34 PM PDT 24
Peak memory 201184 kb
Host smart-c118cad4-058a-4af3-ad0f-8ce72644d428
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595922502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2595922502
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1573627041
Short name T745
Test name
Test status
Simulation time 489728603466 ps
CPU time 1144.95 seconds
Started Jul 23 07:01:30 PM PDT 24
Finished Jul 23 07:20:36 PM PDT 24
Peak memory 201224 kb
Host smart-e63690dd-a116-4de5-8def-867b6114d493
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573627041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1573627041
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2255183782
Short name T750
Test name
Test status
Simulation time 161136565222 ps
CPU time 94.08 seconds
Started Jul 23 07:01:28 PM PDT 24
Finished Jul 23 07:03:03 PM PDT 24
Peak memory 201308 kb
Host smart-d2b6563f-72df-43b8-a673-6cd25700078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255183782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2255183782
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1429541541
Short name T576
Test name
Test status
Simulation time 494819047490 ps
CPU time 1155.3 seconds
Started Jul 23 07:01:14 PM PDT 24
Finished Jul 23 07:20:32 PM PDT 24
Peak memory 201196 kb
Host smart-5fa6fef5-1820-4743-9230-6b96132c7282
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429541541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1429541541
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3696163828
Short name T36
Test name
Test status
Simulation time 270497246853 ps
CPU time 167.45 seconds
Started Jul 23 07:01:18 PM PDT 24
Finished Jul 23 07:04:07 PM PDT 24
Peak memory 201160 kb
Host smart-bf7f475f-2fd0-4df5-8767-6f058ae2fb28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696163828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3696163828
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3817575503
Short name T473
Test name
Test status
Simulation time 414539677100 ps
CPU time 262.47 seconds
Started Jul 23 07:01:22 PM PDT 24
Finished Jul 23 07:05:45 PM PDT 24
Peak memory 201232 kb
Host smart-fa8fe518-a6e8-40ee-89b8-3012f6fe46b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817575503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3817575503
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3745035755
Short name T40
Test name
Test status
Simulation time 89238935424 ps
CPU time 356.81 seconds
Started Jul 23 07:01:22 PM PDT 24
Finished Jul 23 07:07:20 PM PDT 24
Peak memory 201760 kb
Host smart-8db7c0ef-f0b5-4364-8f26-7cae73e724a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745035755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3745035755
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3315642064
Short name T676
Test name
Test status
Simulation time 45518868727 ps
CPU time 51.59 seconds
Started Jul 23 07:01:22 PM PDT 24
Finished Jul 23 07:02:14 PM PDT 24
Peak memory 201080 kb
Host smart-c2d0c814-5f24-44fa-a13c-cb5f1a4852ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315642064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3315642064
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.357874028
Short name T707
Test name
Test status
Simulation time 5286521657 ps
CPU time 12.97 seconds
Started Jul 23 07:01:22 PM PDT 24
Finished Jul 23 07:01:36 PM PDT 24
Peak memory 200996 kb
Host smart-909d782e-380b-44e0-bb3f-47855abaec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357874028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.357874028
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3566855049
Short name T522
Test name
Test status
Simulation time 6139490472 ps
CPU time 2.03 seconds
Started Jul 23 07:01:16 PM PDT 24
Finished Jul 23 07:01:20 PM PDT 24
Peak memory 200988 kb
Host smart-2f25ad5b-3e6c-426d-b60a-15d2572cba16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566855049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3566855049
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3886863049
Short name T484
Test name
Test status
Simulation time 349922676321 ps
CPU time 745.17 seconds
Started Jul 23 07:01:20 PM PDT 24
Finished Jul 23 07:13:46 PM PDT 24
Peak memory 201228 kb
Host smart-6338bcb7-9011-4753-b139-f8ee04ecf3ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886863049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3886863049
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2294561081
Short name T777
Test name
Test status
Simulation time 53323303749 ps
CPU time 111.88 seconds
Started Jul 23 07:01:24 PM PDT 24
Finished Jul 23 07:03:17 PM PDT 24
Peak memory 209540 kb
Host smart-856e4363-ceeb-4a2c-a02b-7839b66fb411
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294561081 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2294561081
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2622158
Short name T417
Test name
Test status
Simulation time 378514976 ps
CPU time 1.02 seconds
Started Jul 23 07:01:28 PM PDT 24
Finished Jul 23 07:01:30 PM PDT 24
Peak memory 200996 kb
Host smart-4a269774-dff7-4b6f-9439-25384a6c1d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2622158
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.888335124
Short name T316
Test name
Test status
Simulation time 558063957776 ps
CPU time 81.13 seconds
Started Jul 23 07:01:23 PM PDT 24
Finished Jul 23 07:02:45 PM PDT 24
Peak memory 201232 kb
Host smart-c56dbe66-7a9a-44c8-9ca6-c9dd40bbb951
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888335124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.888335124
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.116941319
Short name T184
Test name
Test status
Simulation time 165664772614 ps
CPU time 381.22 seconds
Started Jul 23 07:01:21 PM PDT 24
Finished Jul 23 07:07:43 PM PDT 24
Peak memory 201156 kb
Host smart-3b721b62-0a19-47db-b918-c700f64ca1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116941319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.116941319
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1919953178
Short name T338
Test name
Test status
Simulation time 324724553391 ps
CPU time 385.89 seconds
Started Jul 23 07:01:21 PM PDT 24
Finished Jul 23 07:07:48 PM PDT 24
Peak memory 201284 kb
Host smart-fe54c83e-7f63-45ab-b1ec-0b886f27f7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919953178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1919953178
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2391902741
Short name T413
Test name
Test status
Simulation time 335029552890 ps
CPU time 777.7 seconds
Started Jul 23 07:01:22 PM PDT 24
Finished Jul 23 07:14:21 PM PDT 24
Peak memory 201256 kb
Host smart-9e9391d6-722b-4d03-96e5-d9856a5f76cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391902741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2391902741
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3306234275
Short name T290
Test name
Test status
Simulation time 484938351840 ps
CPU time 283.25 seconds
Started Jul 23 07:01:21 PM PDT 24
Finished Jul 23 07:06:05 PM PDT 24
Peak memory 201232 kb
Host smart-4af20251-2757-47da-87d3-440984d2d16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306234275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3306234275
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3681207940
Short name T653
Test name
Test status
Simulation time 331235196724 ps
CPU time 181.53 seconds
Started Jul 23 07:01:20 PM PDT 24
Finished Jul 23 07:04:22 PM PDT 24
Peak memory 201236 kb
Host smart-2f02f11f-9655-4dfa-b290-08a322fb6827
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681207940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3681207940
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2463846710
Short name T634
Test name
Test status
Simulation time 179532417945 ps
CPU time 406.79 seconds
Started Jul 23 07:01:22 PM PDT 24
Finished Jul 23 07:08:09 PM PDT 24
Peak memory 201304 kb
Host smart-7e146eba-44a9-406a-8158-226382a5ab74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463846710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2463846710
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3103101797
Short name T698
Test name
Test status
Simulation time 198434136464 ps
CPU time 432.07 seconds
Started Jul 23 07:01:21 PM PDT 24
Finished Jul 23 07:08:34 PM PDT 24
Peak memory 201212 kb
Host smart-e6bda32e-c0f7-4cc7-ba3a-055636a98d8b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103101797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3103101797
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1910562538
Short name T784
Test name
Test status
Simulation time 68358877525 ps
CPU time 282.34 seconds
Started Jul 23 07:01:27 PM PDT 24
Finished Jul 23 07:06:10 PM PDT 24
Peak memory 201664 kb
Host smart-cd316ce1-41cc-4124-8212-e58c9201dad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910562538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1910562538
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1440244603
Short name T589
Test name
Test status
Simulation time 26240872289 ps
CPU time 61.49 seconds
Started Jul 23 07:01:30 PM PDT 24
Finished Jul 23 07:02:32 PM PDT 24
Peak memory 201052 kb
Host smart-acde948c-ce24-48d3-8135-d1e5d5d17a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440244603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1440244603
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1002966588
Short name T689
Test name
Test status
Simulation time 3940706939 ps
CPU time 2.65 seconds
Started Jul 23 07:01:21 PM PDT 24
Finished Jul 23 07:01:25 PM PDT 24
Peak memory 201060 kb
Host smart-ff5e2611-ecfb-4774-9b89-1603f401a833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002966588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1002966588
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3978790206
Short name T725
Test name
Test status
Simulation time 5738666558 ps
CPU time 7.53 seconds
Started Jul 23 07:01:20 PM PDT 24
Finished Jul 23 07:01:28 PM PDT 24
Peak memory 201068 kb
Host smart-174fde74-6213-41ca-8d94-32b1c0312d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978790206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3978790206
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.249495493
Short name T20
Test name
Test status
Simulation time 20103958475 ps
CPU time 37.07 seconds
Started Jul 23 07:01:34 PM PDT 24
Finished Jul 23 07:02:12 PM PDT 24
Peak memory 209980 kb
Host smart-a2657fc4-ce06-49fb-81a8-64d3f04d251e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249495493 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.249495493
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3909394461
Short name T526
Test name
Test status
Simulation time 527754320 ps
CPU time 0.96 seconds
Started Jul 23 07:00:03 PM PDT 24
Finished Jul 23 07:00:05 PM PDT 24
Peak memory 201048 kb
Host smart-39f74a3e-40d8-4952-94cf-f6e92c49a686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909394461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3909394461
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1782431266
Short name T686
Test name
Test status
Simulation time 518402189002 ps
CPU time 1233.83 seconds
Started Jul 23 07:00:05 PM PDT 24
Finished Jul 23 07:20:40 PM PDT 24
Peak memory 201168 kb
Host smart-52ed4a0f-b8b0-43f3-9cb9-3084430194c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782431266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1782431266
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3957360878
Short name T330
Test name
Test status
Simulation time 165302911686 ps
CPU time 358.95 seconds
Started Jul 23 07:00:07 PM PDT 24
Finished Jul 23 07:06:08 PM PDT 24
Peak memory 201220 kb
Host smart-47f66e16-4efe-4598-bc15-445ac8a1fe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957360878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3957360878
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.4246838229
Short name T173
Test name
Test status
Simulation time 475840226470 ps
CPU time 132.55 seconds
Started Jul 23 06:59:56 PM PDT 24
Finished Jul 23 07:02:13 PM PDT 24
Peak memory 201248 kb
Host smart-ab369f71-c67b-431f-83ab-c39b9a6c72d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246838229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.4246838229
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.423189195
Short name T437
Test name
Test status
Simulation time 162357517007 ps
CPU time 27.21 seconds
Started Jul 23 06:59:56 PM PDT 24
Finished Jul 23 07:00:27 PM PDT 24
Peak memory 201420 kb
Host smart-1500607d-e68a-4774-9329-77589f454cfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=423189195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.423189195
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3660600118
Short name T622
Test name
Test status
Simulation time 335114496858 ps
CPU time 742.16 seconds
Started Jul 23 07:00:07 PM PDT 24
Finished Jul 23 07:12:31 PM PDT 24
Peak memory 201196 kb
Host smart-1624a5fc-d3dd-4a47-9ee3-b59656d8e212
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660600118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3660600118
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.243592213
Short name T669
Test name
Test status
Simulation time 218706385126 ps
CPU time 141.23 seconds
Started Jul 23 06:59:58 PM PDT 24
Finished Jul 23 07:02:22 PM PDT 24
Peak memory 201172 kb
Host smart-391b458f-c4cb-44c0-a085-70a28ab6a0c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243592213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.243592213
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3009173018
Short name T754
Test name
Test status
Simulation time 192163010237 ps
CPU time 411.18 seconds
Started Jul 23 06:59:57 PM PDT 24
Finished Jul 23 07:06:52 PM PDT 24
Peak memory 201156 kb
Host smart-f7e2f2b3-d8f7-4aa1-aae1-bcf1d908348b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009173018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3009173018
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3221989195
Short name T533
Test name
Test status
Simulation time 74670761654 ps
CPU time 419.05 seconds
Started Jul 23 07:00:07 PM PDT 24
Finished Jul 23 07:07:06 PM PDT 24
Peak memory 201672 kb
Host smart-0419e9a8-a44c-410b-b184-2397da1a8f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221989195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3221989195
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.943252980
Short name T389
Test name
Test status
Simulation time 43128375317 ps
CPU time 41.12 seconds
Started Jul 23 06:59:58 PM PDT 24
Finished Jul 23 07:00:42 PM PDT 24
Peak memory 201072 kb
Host smart-287e0f7d-badd-4a5c-a6ac-46088002657e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943252980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.943252980
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.903891781
Short name T637
Test name
Test status
Simulation time 5156113430 ps
CPU time 13.54 seconds
Started Jul 23 06:59:59 PM PDT 24
Finished Jul 23 07:00:15 PM PDT 24
Peak memory 201080 kb
Host smart-e006401c-e377-4a0f-93ac-d70451c89087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903891781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.903891781
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3447330579
Short name T54
Test name
Test status
Simulation time 8390688844 ps
CPU time 5.32 seconds
Started Jul 23 07:00:05 PM PDT 24
Finished Jul 23 07:00:11 PM PDT 24
Peak memory 217892 kb
Host smart-2d522fd3-0a1a-43a6-8cf6-8a24a33c5113
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447330579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3447330579
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.812573460
Short name T97
Test name
Test status
Simulation time 5869699061 ps
CPU time 8.18 seconds
Started Jul 23 07:00:06 PM PDT 24
Finished Jul 23 07:00:15 PM PDT 24
Peak memory 201068 kb
Host smart-ed2475e4-944b-4d1f-90ff-c6547b43ab28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812573460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.812573460
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2285065990
Short name T604
Test name
Test status
Simulation time 327460274950 ps
CPU time 184.95 seconds
Started Jul 23 07:00:15 PM PDT 24
Finished Jul 23 07:03:20 PM PDT 24
Peak memory 201220 kb
Host smart-a0b2d4a2-cc2b-4610-9b54-efb84213a657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285065990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2285065990
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.972010888
Short name T32
Test name
Test status
Simulation time 660446840876 ps
CPU time 88.08 seconds
Started Jul 23 07:00:04 PM PDT 24
Finished Jul 23 07:01:34 PM PDT 24
Peak memory 209812 kb
Host smart-1556fdf7-00ff-4ef8-ac6e-a57753de5e21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972010888 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.972010888
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1045012889
Short name T495
Test name
Test status
Simulation time 482825337 ps
CPU time 1.6 seconds
Started Jul 23 07:01:33 PM PDT 24
Finished Jul 23 07:01:35 PM PDT 24
Peak memory 201040 kb
Host smart-a7fd8e4e-e633-4ddd-bd88-4a64f71a58e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045012889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1045012889
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3977936
Short name T334
Test name
Test status
Simulation time 173014518743 ps
CPU time 378.24 seconds
Started Jul 23 07:01:26 PM PDT 24
Finished Jul 23 07:07:45 PM PDT 24
Peak memory 201244 kb
Host smart-a2e6ecea-8b38-4397-90c2-976a17a61058
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.3977936
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2336838652
Short name T615
Test name
Test status
Simulation time 327056647712 ps
CPU time 104.44 seconds
Started Jul 23 07:01:28 PM PDT 24
Finished Jul 23 07:03:13 PM PDT 24
Peak memory 201232 kb
Host smart-3cd6fd9a-a07b-46f8-b7f3-bcaa948d9915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336838652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2336838652
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1935660316
Short name T783
Test name
Test status
Simulation time 338568638007 ps
CPU time 53.37 seconds
Started Jul 23 07:01:26 PM PDT 24
Finished Jul 23 07:02:20 PM PDT 24
Peak memory 201220 kb
Host smart-cda890ad-30d0-4ae0-9c2e-351541d20103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935660316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1935660316
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2306217416
Short name T233
Test name
Test status
Simulation time 164088500488 ps
CPU time 196.42 seconds
Started Jul 23 07:01:28 PM PDT 24
Finished Jul 23 07:04:45 PM PDT 24
Peak memory 201256 kb
Host smart-4084c707-25f8-48a6-bfc6-bebad9746370
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306217416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2306217416
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1141848207
Short name T312
Test name
Test status
Simulation time 480215537232 ps
CPU time 574.6 seconds
Started Jul 23 07:01:27 PM PDT 24
Finished Jul 23 07:11:02 PM PDT 24
Peak memory 201140 kb
Host smart-cb5f237a-ac69-43ec-8397-b288d58ab1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141848207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1141848207
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2223840314
Short name T384
Test name
Test status
Simulation time 501345230376 ps
CPU time 1176.7 seconds
Started Jul 23 07:01:27 PM PDT 24
Finished Jul 23 07:21:05 PM PDT 24
Peak memory 201148 kb
Host smart-e690dcb8-5cc5-4515-82d8-9e9d58f38824
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223840314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2223840314
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.4281572733
Short name T487
Test name
Test status
Simulation time 195696791619 ps
CPU time 468.16 seconds
Started Jul 23 07:01:30 PM PDT 24
Finished Jul 23 07:09:19 PM PDT 24
Peak memory 201272 kb
Host smart-35e8c101-7416-436f-af2e-c9bbc0bdc8f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281572733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.4281572733
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3440655600
Short name T635
Test name
Test status
Simulation time 604572864126 ps
CPU time 418.17 seconds
Started Jul 23 07:01:27 PM PDT 24
Finished Jul 23 07:08:25 PM PDT 24
Peak memory 201120 kb
Host smart-57629c32-b7f7-4238-9366-d023f3c5846d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440655600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3440655600
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1812715693
Short name T581
Test name
Test status
Simulation time 79550920828 ps
CPU time 305.25 seconds
Started Jul 23 07:01:30 PM PDT 24
Finished Jul 23 07:06:36 PM PDT 24
Peak memory 201752 kb
Host smart-0a9b83c0-2d8e-4a50-9719-a107fb16be1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812715693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1812715693
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.987397695
Short name T497
Test name
Test status
Simulation time 38654954635 ps
CPU time 23.09 seconds
Started Jul 23 07:01:27 PM PDT 24
Finished Jul 23 07:01:51 PM PDT 24
Peak memory 201076 kb
Host smart-7096c113-c4de-40bf-bfa8-3b1a8f939861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987397695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.987397695
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1765598635
Short name T408
Test name
Test status
Simulation time 5158383137 ps
CPU time 11.99 seconds
Started Jul 23 07:01:30 PM PDT 24
Finished Jul 23 07:01:43 PM PDT 24
Peak memory 201164 kb
Host smart-f596834d-21fd-4c43-a1b2-c4c82aceb074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765598635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1765598635
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2328666876
Short name T134
Test name
Test status
Simulation time 5815146515 ps
CPU time 15.04 seconds
Started Jul 23 07:01:27 PM PDT 24
Finished Jul 23 07:01:42 PM PDT 24
Peak memory 201004 kb
Host smart-066e7d41-1a55-4a18-9ad3-1b5adad7c4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328666876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2328666876
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3520947168
Short name T335
Test name
Test status
Simulation time 184150820683 ps
CPU time 406.23 seconds
Started Jul 23 07:01:29 PM PDT 24
Finished Jul 23 07:08:16 PM PDT 24
Peak memory 201300 kb
Host smart-a8ea94a7-1997-4d16-901a-2b6ccf1bb333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520947168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3520947168
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3756922019
Short name T339
Test name
Test status
Simulation time 173513491176 ps
CPU time 187.45 seconds
Started Jul 23 07:01:29 PM PDT 24
Finished Jul 23 07:04:38 PM PDT 24
Peak memory 210128 kb
Host smart-91f78215-78d8-417e-b156-6df00d3b7329
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756922019 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3756922019
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2305374847
Short name T398
Test name
Test status
Simulation time 530684520 ps
CPU time 1.24 seconds
Started Jul 23 07:01:40 PM PDT 24
Finished Jul 23 07:01:42 PM PDT 24
Peak memory 201048 kb
Host smart-4252a2fa-6ecb-405c-93f9-a2b482a27d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305374847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2305374847
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1727139857
Short name T337
Test name
Test status
Simulation time 172838642052 ps
CPU time 214.19 seconds
Started Jul 23 07:01:33 PM PDT 24
Finished Jul 23 07:05:08 PM PDT 24
Peak memory 201196 kb
Host smart-206ff91d-6246-4d40-b858-8b06f91204ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727139857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1727139857
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2003839321
Short name T192
Test name
Test status
Simulation time 517819024876 ps
CPU time 143.19 seconds
Started Jul 23 07:01:33 PM PDT 24
Finished Jul 23 07:03:56 PM PDT 24
Peak memory 201220 kb
Host smart-2a8ba0a7-ed03-4347-a35e-8c66e3ba3623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003839321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2003839321
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2086567575
Short name T319
Test name
Test status
Simulation time 486031770921 ps
CPU time 283.97 seconds
Started Jul 23 07:01:38 PM PDT 24
Finished Jul 23 07:06:22 PM PDT 24
Peak memory 201264 kb
Host smart-da17335d-c7cf-44db-8491-232f01d00e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086567575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2086567575
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2102499547
Short name T628
Test name
Test status
Simulation time 166907825042 ps
CPU time 96.85 seconds
Started Jul 23 07:01:33 PM PDT 24
Finished Jul 23 07:03:11 PM PDT 24
Peak memory 201172 kb
Host smart-ee656770-ee34-403d-bbd2-c8c7f5b2b906
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102499547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2102499547
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.487798584
Short name T434
Test name
Test status
Simulation time 166631476239 ps
CPU time 198.36 seconds
Started Jul 23 07:01:35 PM PDT 24
Finished Jul 23 07:04:54 PM PDT 24
Peak memory 201216 kb
Host smart-c4e140e0-3bcc-4ff1-9e22-42b9399cc390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487798584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.487798584
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4060987500
Short name T597
Test name
Test status
Simulation time 162345531136 ps
CPU time 346.63 seconds
Started Jul 23 07:01:35 PM PDT 24
Finished Jul 23 07:07:22 PM PDT 24
Peak memory 201312 kb
Host smart-6ee6ce70-16d9-4234-bb18-2f5ffcbc5c6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060987500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4060987500
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2051368460
Short name T274
Test name
Test status
Simulation time 672009060791 ps
CPU time 1509.44 seconds
Started Jul 23 07:01:34 PM PDT 24
Finished Jul 23 07:26:44 PM PDT 24
Peak memory 201216 kb
Host smart-ef48067a-c758-4338-bc34-333149fae624
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051368460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2051368460
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1436533192
Short name T421
Test name
Test status
Simulation time 611634110160 ps
CPU time 407.2 seconds
Started Jul 23 07:01:35 PM PDT 24
Finished Jul 23 07:08:23 PM PDT 24
Peak memory 201192 kb
Host smart-69351b3e-87bc-44b0-b23b-490765c971a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436533192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1436533192
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3065960548
Short name T426
Test name
Test status
Simulation time 96524873513 ps
CPU time 572.96 seconds
Started Jul 23 07:01:38 PM PDT 24
Finished Jul 23 07:11:12 PM PDT 24
Peak memory 201648 kb
Host smart-d83795d6-140e-48da-b032-8176cbe06a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065960548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3065960548
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1672874650
Short name T498
Test name
Test status
Simulation time 45495051519 ps
CPU time 26.73 seconds
Started Jul 23 07:01:34 PM PDT 24
Finished Jul 23 07:02:01 PM PDT 24
Peak memory 201100 kb
Host smart-b7cb1f0b-83c4-4608-b28a-c79acf590ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672874650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1672874650
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.775106299
Short name T483
Test name
Test status
Simulation time 3695684394 ps
CPU time 5.08 seconds
Started Jul 23 07:01:35 PM PDT 24
Finished Jul 23 07:01:40 PM PDT 24
Peak memory 201060 kb
Host smart-efa25e14-4413-42f5-a64c-337d100495c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775106299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.775106299
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.507379129
Short name T444
Test name
Test status
Simulation time 5853358967 ps
CPU time 12.5 seconds
Started Jul 23 07:01:38 PM PDT 24
Finished Jul 23 07:01:51 PM PDT 24
Peak memory 201044 kb
Host smart-37b2dd23-8f5f-4778-b0b8-b2b92620f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507379129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.507379129
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2369838132
Short name T23
Test name
Test status
Simulation time 264189037737 ps
CPU time 434.85 seconds
Started Jul 23 07:01:40 PM PDT 24
Finished Jul 23 07:08:56 PM PDT 24
Peak memory 209876 kb
Host smart-0730f11c-a707-4be1-9325-363453bdcf3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369838132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2369838132
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1312090234
Short name T82
Test name
Test status
Simulation time 267607467931 ps
CPU time 327.35 seconds
Started Jul 23 07:01:34 PM PDT 24
Finished Jul 23 07:07:02 PM PDT 24
Peak memory 210004 kb
Host smart-4f4069f4-845a-4050-8117-c35edc1cd45b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312090234 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1312090234
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1869873136
Short name T660
Test name
Test status
Simulation time 526296554 ps
CPU time 0.71 seconds
Started Jul 23 07:01:49 PM PDT 24
Finished Jul 23 07:01:51 PM PDT 24
Peak memory 201020 kb
Host smart-f08b4bd7-cd57-4646-baa9-0e252da9d3ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869873136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1869873136
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1836080307
Short name T239
Test name
Test status
Simulation time 164746841157 ps
CPU time 163.14 seconds
Started Jul 23 07:01:52 PM PDT 24
Finished Jul 23 07:04:36 PM PDT 24
Peak memory 201328 kb
Host smart-ede70da3-d9c5-425f-9eb8-ec59eaa463b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836080307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1836080307
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.227665265
Short name T738
Test name
Test status
Simulation time 320330836566 ps
CPU time 192 seconds
Started Jul 23 07:01:41 PM PDT 24
Finished Jul 23 07:04:53 PM PDT 24
Peak memory 201340 kb
Host smart-98425112-e30f-4ffc-a79f-975e1df08792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227665265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.227665265
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3892299556
Short name T386
Test name
Test status
Simulation time 325193263589 ps
CPU time 181.3 seconds
Started Jul 23 07:01:41 PM PDT 24
Finished Jul 23 07:04:43 PM PDT 24
Peak memory 201224 kb
Host smart-8981a0cc-37a4-4b29-9fb5-85c5c194655b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892299556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3892299556
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.4268608547
Short name T418
Test name
Test status
Simulation time 162928604684 ps
CPU time 31.82 seconds
Started Jul 23 07:01:40 PM PDT 24
Finished Jul 23 07:02:12 PM PDT 24
Peak memory 201268 kb
Host smart-bf7188b1-ad77-478e-a64d-4c60ca32891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268608547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.4268608547
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2913391029
Short name T5
Test name
Test status
Simulation time 493867575725 ps
CPU time 606.78 seconds
Started Jul 23 07:01:42 PM PDT 24
Finished Jul 23 07:11:50 PM PDT 24
Peak memory 201308 kb
Host smart-e9f0c8c9-3ca4-4d81-a4fd-0b299278c986
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913391029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2913391029
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2251696727
Short name T736
Test name
Test status
Simulation time 191927149134 ps
CPU time 401.69 seconds
Started Jul 23 07:01:40 PM PDT 24
Finished Jul 23 07:08:22 PM PDT 24
Peak memory 201316 kb
Host smart-80045581-2216-45a8-a232-f74b68eb89d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251696727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2251696727
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.80852131
Short name T452
Test name
Test status
Simulation time 607236797453 ps
CPU time 265.63 seconds
Started Jul 23 07:01:42 PM PDT 24
Finished Jul 23 07:06:08 PM PDT 24
Peak memory 201272 kb
Host smart-bd8ee66e-3074-4f7b-850b-3c96f7971806
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80852131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.a
dc_ctrl_filters_wakeup_fixed.80852131
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.153180655
Short name T352
Test name
Test status
Simulation time 114390348562 ps
CPU time 613.66 seconds
Started Jul 23 07:01:49 PM PDT 24
Finished Jul 23 07:12:04 PM PDT 24
Peak memory 201760 kb
Host smart-f8209476-817f-4f57-937b-54a35a7023c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153180655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.153180655
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1226947081
Short name T425
Test name
Test status
Simulation time 24364869445 ps
CPU time 58.7 seconds
Started Jul 23 07:01:47 PM PDT 24
Finished Jul 23 07:02:46 PM PDT 24
Peak memory 201068 kb
Host smart-d863cd7b-6953-44bd-92d0-5fff50f81266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226947081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1226947081
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.234320618
Short name T751
Test name
Test status
Simulation time 3807432590 ps
CPU time 4.87 seconds
Started Jul 23 07:01:49 PM PDT 24
Finished Jul 23 07:01:54 PM PDT 24
Peak memory 201084 kb
Host smart-8a27a4a4-fe56-474a-b795-5c85b6e7f355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234320618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.234320618
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2111466141
Short name T598
Test name
Test status
Simulation time 5862231975 ps
CPU time 7.33 seconds
Started Jul 23 07:01:39 PM PDT 24
Finished Jul 23 07:01:46 PM PDT 24
Peak memory 200948 kb
Host smart-df518378-1121-4c54-81ed-f697d2333cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111466141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2111466141
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2593481444
Short name T8
Test name
Test status
Simulation time 373001481841 ps
CPU time 424.12 seconds
Started Jul 23 07:01:46 PM PDT 24
Finished Jul 23 07:08:51 PM PDT 24
Peak memory 201284 kb
Host smart-411b4bfb-25be-46c4-8656-a5b9c217bd32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593481444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2593481444
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4200545812
Short name T663
Test name
Test status
Simulation time 69342574142 ps
CPU time 48.26 seconds
Started Jul 23 07:01:51 PM PDT 24
Finished Jul 23 07:02:40 PM PDT 24
Peak memory 209576 kb
Host smart-f8e40442-d8d3-4710-856f-394da6f6b415
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200545812 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.4200545812
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3713967486
Short name T422
Test name
Test status
Simulation time 299486381 ps
CPU time 0.99 seconds
Started Jul 23 07:02:06 PM PDT 24
Finished Jul 23 07:02:07 PM PDT 24
Peak memory 201040 kb
Host smart-77d692ae-37eb-4ca7-b7a8-f59b14644fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713967486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3713967486
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.453702687
Short name T644
Test name
Test status
Simulation time 535063214268 ps
CPU time 318.99 seconds
Started Jul 23 07:01:56 PM PDT 24
Finished Jul 23 07:07:16 PM PDT 24
Peak memory 201212 kb
Host smart-c4c5ad0a-82ca-4142-89de-859bc759f899
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453702687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.453702687
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2202274793
Short name T145
Test name
Test status
Simulation time 167484992532 ps
CPU time 25.49 seconds
Started Jul 23 07:01:52 PM PDT 24
Finished Jul 23 07:02:18 PM PDT 24
Peak memory 201240 kb
Host smart-228b37b9-fa5f-4549-85f1-ed1c9cbffbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202274793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2202274793
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1414804988
Short name T525
Test name
Test status
Simulation time 333398346215 ps
CPU time 203.82 seconds
Started Jul 23 07:01:52 PM PDT 24
Finished Jul 23 07:05:16 PM PDT 24
Peak memory 201292 kb
Host smart-04acccaa-5880-4518-906d-66e30b0c2d27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414804988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1414804988
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.4273540699
Short name T672
Test name
Test status
Simulation time 339727872730 ps
CPU time 784.85 seconds
Started Jul 23 07:01:47 PM PDT 24
Finished Jul 23 07:14:52 PM PDT 24
Peak memory 201272 kb
Host smart-b196b0b2-a9f9-4d1b-bcd9-0f663b110f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273540699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.4273540699
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2657919550
Short name T156
Test name
Test status
Simulation time 162150038668 ps
CPU time 59.51 seconds
Started Jul 23 07:01:51 PM PDT 24
Finished Jul 23 07:02:51 PM PDT 24
Peak memory 201240 kb
Host smart-6891be10-36f7-49cf-a28f-1c1da6d28a17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657919550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2657919550
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2747168480
Short name T475
Test name
Test status
Simulation time 180804857182 ps
CPU time 103.79 seconds
Started Jul 23 07:01:51 PM PDT 24
Finished Jul 23 07:03:35 PM PDT 24
Peak memory 201268 kb
Host smart-1c62e148-542c-4439-b406-485f68133d44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747168480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2747168480
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1345650037
Short name T367
Test name
Test status
Simulation time 194933780963 ps
CPU time 224.01 seconds
Started Jul 23 07:01:50 PM PDT 24
Finished Jul 23 07:05:35 PM PDT 24
Peak memory 201184 kb
Host smart-09e78ed9-dda3-4e2d-8311-1c243d6aebbb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345650037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1345650037
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.56877978
Short name T203
Test name
Test status
Simulation time 94210113015 ps
CPU time 408.67 seconds
Started Jul 23 07:02:06 PM PDT 24
Finished Jul 23 07:08:55 PM PDT 24
Peak memory 201540 kb
Host smart-e75be184-38c4-4e0f-80e4-f52956ce421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56877978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.56877978
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3753794516
Short name T595
Test name
Test status
Simulation time 26632698388 ps
CPU time 29.76 seconds
Started Jul 23 07:02:07 PM PDT 24
Finished Jul 23 07:02:38 PM PDT 24
Peak memory 201040 kb
Host smart-03c19264-f627-4539-89b9-851eaf2b734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753794516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3753794516
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3032114857
Short name T752
Test name
Test status
Simulation time 4707475421 ps
CPU time 8.19 seconds
Started Jul 23 07:01:55 PM PDT 24
Finished Jul 23 07:02:04 PM PDT 24
Peak memory 201016 kb
Host smart-f3ca1931-bf4d-4943-a221-e840abb2c4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032114857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3032114857
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1611577110
Short name T536
Test name
Test status
Simulation time 5693362179 ps
CPU time 4.73 seconds
Started Jul 23 07:01:50 PM PDT 24
Finished Jul 23 07:01:56 PM PDT 24
Peak memory 201072 kb
Host smart-dca927c0-b859-435b-a155-a27cd389fd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611577110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1611577110
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3134121853
Short name T587
Test name
Test status
Simulation time 138142719914 ps
CPU time 340.45 seconds
Started Jul 23 07:02:05 PM PDT 24
Finished Jul 23 07:07:46 PM PDT 24
Peak memory 209996 kb
Host smart-311d78dc-f178-45bf-9fe6-529630c23d43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134121853 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3134121853
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3933284829
Short name T699
Test name
Test status
Simulation time 386185285 ps
CPU time 1.45 seconds
Started Jul 23 07:02:10 PM PDT 24
Finished Jul 23 07:02:14 PM PDT 24
Peak memory 199896 kb
Host smart-cd393c78-f75c-489b-9d5c-a20e1274f10a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933284829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3933284829
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1744200706
Short name T257
Test name
Test status
Simulation time 187009671214 ps
CPU time 410.37 seconds
Started Jul 23 07:02:10 PM PDT 24
Finished Jul 23 07:09:03 PM PDT 24
Peak memory 200216 kb
Host smart-1f8c1449-be3a-4afb-9cb7-8eb4d234dd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744200706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1744200706
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3123502757
Short name T269
Test name
Test status
Simulation time 164236687331 ps
CPU time 209.87 seconds
Started Jul 23 07:02:06 PM PDT 24
Finished Jul 23 07:05:38 PM PDT 24
Peak memory 201320 kb
Host smart-0d60a1c1-2a19-41de-8811-6c10a6b78163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123502757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3123502757
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2395982676
Short name T414
Test name
Test status
Simulation time 494695059449 ps
CPU time 294.07 seconds
Started Jul 23 07:02:06 PM PDT 24
Finished Jul 23 07:07:01 PM PDT 24
Peak memory 201180 kb
Host smart-45410a2d-8626-455b-96e7-8351e681e700
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395982676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2395982676
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1098232750
Short name T664
Test name
Test status
Simulation time 331464184532 ps
CPU time 195.98 seconds
Started Jul 23 07:02:05 PM PDT 24
Finished Jul 23 07:05:22 PM PDT 24
Peak memory 201252 kb
Host smart-3ef2b7de-905b-46db-b3f4-c233cb3fafce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098232750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1098232750
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1707517357
Short name T710
Test name
Test status
Simulation time 332894816026 ps
CPU time 388.12 seconds
Started Jul 23 07:02:07 PM PDT 24
Finished Jul 23 07:08:36 PM PDT 24
Peak memory 201216 kb
Host smart-22eaf153-4d37-4e21-80c4-a94c305c869a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707517357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1707517357
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.469131922
Short name T794
Test name
Test status
Simulation time 605614459326 ps
CPU time 1382.87 seconds
Started Jul 23 07:02:08 PM PDT 24
Finished Jul 23 07:25:12 PM PDT 24
Peak memory 201168 kb
Host smart-433ab069-417f-4ae0-bafa-40657fbcaa1d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469131922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.469131922
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1242148346
Short name T711
Test name
Test status
Simulation time 143467051846 ps
CPU time 483.15 seconds
Started Jul 23 07:02:09 PM PDT 24
Finished Jul 23 07:10:14 PM PDT 24
Peak memory 201692 kb
Host smart-5fd47fd0-0a35-41f8-86ce-ab5ed927a253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242148346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1242148346
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2324376744
Short name T573
Test name
Test status
Simulation time 43868195995 ps
CPU time 49.18 seconds
Started Jul 23 07:02:07 PM PDT 24
Finished Jul 23 07:02:58 PM PDT 24
Peak memory 200936 kb
Host smart-757898ba-0b3d-460d-b3b6-087686eee16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324376744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2324376744
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3325090203
Short name T492
Test name
Test status
Simulation time 5039062124 ps
CPU time 3.64 seconds
Started Jul 23 07:02:09 PM PDT 24
Finished Jul 23 07:02:14 PM PDT 24
Peak memory 201072 kb
Host smart-735917ad-28dd-4b8d-8708-a366731d53c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325090203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3325090203
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1954146910
Short name T782
Test name
Test status
Simulation time 5727773118 ps
CPU time 3.95 seconds
Started Jul 23 07:02:07 PM PDT 24
Finished Jul 23 07:02:12 PM PDT 24
Peak memory 201004 kb
Host smart-9c78db04-ea89-40e5-ba4c-7982c0e2b0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954146910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1954146910
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.767308405
Short name T317
Test name
Test status
Simulation time 220052016910 ps
CPU time 134.64 seconds
Started Jul 23 07:02:07 PM PDT 24
Finished Jul 23 07:04:23 PM PDT 24
Peak memory 201296 kb
Host smart-763737dc-8775-43d2-905b-d2e4adb69dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767308405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
767308405
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.404638029
Short name T341
Test name
Test status
Simulation time 163012273758 ps
CPU time 165.06 seconds
Started Jul 23 07:02:07 PM PDT 24
Finished Jul 23 07:04:53 PM PDT 24
Peak memory 211020 kb
Host smart-ad97950c-4a5d-443a-bf1e-55518d21d0de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404638029 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.404638029
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1076430126
Short name T558
Test name
Test status
Simulation time 426213833 ps
CPU time 1.63 seconds
Started Jul 23 07:02:08 PM PDT 24
Finished Jul 23 07:02:11 PM PDT 24
Peak memory 201040 kb
Host smart-39c74158-fd3d-43f1-9141-6c0f90173bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076430126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1076430126
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3085190736
Short name T718
Test name
Test status
Simulation time 327843924492 ps
CPU time 59.89 seconds
Started Jul 23 07:02:11 PM PDT 24
Finished Jul 23 07:03:13 PM PDT 24
Peak memory 201244 kb
Host smart-69315420-0982-4fa2-8724-13b5065e4977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085190736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3085190736
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3244634285
Short name T172
Test name
Test status
Simulation time 497098843257 ps
CPU time 1035.39 seconds
Started Jul 23 07:02:09 PM PDT 24
Finished Jul 23 07:19:27 PM PDT 24
Peak memory 201312 kb
Host smart-8ea14141-5cd2-4163-8ab1-cdfb3a24c9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244634285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3244634285
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2647348729
Short name T590
Test name
Test status
Simulation time 325505796923 ps
CPU time 103.95 seconds
Started Jul 23 07:02:09 PM PDT 24
Finished Jul 23 07:03:54 PM PDT 24
Peak memory 201224 kb
Host smart-5613f3ab-9188-4d68-a8c8-2b1c8d377adc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647348729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2647348729
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.363316917
Short name T127
Test name
Test status
Simulation time 328786056058 ps
CPU time 375.29 seconds
Started Jul 23 07:02:08 PM PDT 24
Finished Jul 23 07:08:25 PM PDT 24
Peak memory 201296 kb
Host smart-9980f10e-cfeb-4b0f-99a2-18e844040976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363316917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.363316917
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3031572513
Short name T463
Test name
Test status
Simulation time 330821328424 ps
CPU time 355.61 seconds
Started Jul 23 07:02:07 PM PDT 24
Finished Jul 23 07:08:04 PM PDT 24
Peak memory 201256 kb
Host smart-e8c23f1e-7ae0-46c8-9408-83fea1094c94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031572513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3031572513
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1552981800
Short name T179
Test name
Test status
Simulation time 553249538276 ps
CPU time 98.65 seconds
Started Jul 23 07:02:07 PM PDT 24
Finished Jul 23 07:03:46 PM PDT 24
Peak memory 201176 kb
Host smart-295f063c-e1f8-4498-a1c4-ad60f045707d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552981800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1552981800
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.857553100
Short name T519
Test name
Test status
Simulation time 610694233766 ps
CPU time 468.72 seconds
Started Jul 23 07:02:08 PM PDT 24
Finished Jul 23 07:09:58 PM PDT 24
Peak memory 201132 kb
Host smart-cdebc4d1-c436-448e-9744-55a17345a0a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857553100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.857553100
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1494134422
Short name T762
Test name
Test status
Simulation time 37829454486 ps
CPU time 22.59 seconds
Started Jul 23 07:02:11 PM PDT 24
Finished Jul 23 07:02:36 PM PDT 24
Peak memory 201080 kb
Host smart-25cde306-4621-49bd-84a0-98d6c3e63377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494134422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1494134422
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1185449123
Short name T563
Test name
Test status
Simulation time 3245377619 ps
CPU time 2.22 seconds
Started Jul 23 07:02:08 PM PDT 24
Finished Jul 23 07:02:12 PM PDT 24
Peak memory 201076 kb
Host smart-91a426e5-0f66-4d96-9603-de7e61d3b26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185449123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1185449123
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3605332376
Short name T69
Test name
Test status
Simulation time 6021389365 ps
CPU time 2.2 seconds
Started Jul 23 07:02:08 PM PDT 24
Finished Jul 23 07:02:12 PM PDT 24
Peak memory 201076 kb
Host smart-532d52a3-b8ca-48c8-8641-90d92874c2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605332376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3605332376
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.107340378
Short name T25
Test name
Test status
Simulation time 499917936605 ps
CPU time 206.93 seconds
Started Jul 23 07:02:09 PM PDT 24
Finished Jul 23 07:05:38 PM PDT 24
Peak memory 201220 kb
Host smart-022b0f2d-3459-43f1-aa90-8ee1cfac56f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107340378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
107340378
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1293310910
Short name T183
Test name
Test status
Simulation time 326613078 ps
CPU time 0.88 seconds
Started Jul 23 07:02:14 PM PDT 24
Finished Jul 23 07:02:15 PM PDT 24
Peak memory 201004 kb
Host smart-860062b1-0fee-490a-903f-673121eb526a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293310910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1293310910
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3251678376
Short name T645
Test name
Test status
Simulation time 161207102119 ps
CPU time 392.11 seconds
Started Jul 23 07:02:11 PM PDT 24
Finished Jul 23 07:08:45 PM PDT 24
Peak memory 201252 kb
Host smart-1978d111-bd34-49d8-a414-f1df6a72f4fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251678376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3251678376
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1843762167
Short name T170
Test name
Test status
Simulation time 165764189088 ps
CPU time 399.3 seconds
Started Jul 23 07:02:19 PM PDT 24
Finished Jul 23 07:08:59 PM PDT 24
Peak memory 201208 kb
Host smart-2178f224-d7bb-4ce3-84d8-0f0d8386fc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843762167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1843762167
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4223615136
Short name T485
Test name
Test status
Simulation time 327146847858 ps
CPU time 182.6 seconds
Started Jul 23 07:02:09 PM PDT 24
Finished Jul 23 07:05:13 PM PDT 24
Peak memory 201164 kb
Host smart-de06241e-f949-4237-bd2e-ce777ed83c59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223615136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.4223615136
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.473261290
Short name T289
Test name
Test status
Simulation time 494111176501 ps
CPU time 266.81 seconds
Started Jul 23 07:02:11 PM PDT 24
Finished Jul 23 07:06:39 PM PDT 24
Peak memory 201376 kb
Host smart-ee3500c3-fe0d-4e81-bc14-af193174daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473261290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.473261290
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.4116327581
Short name T429
Test name
Test status
Simulation time 484925797436 ps
CPU time 309.72 seconds
Started Jul 23 07:02:09 PM PDT 24
Finished Jul 23 07:07:21 PM PDT 24
Peak memory 201112 kb
Host smart-345973f8-ac11-4cea-9426-a29b2e52c1c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116327581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.4116327581
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3353737776
Short name T245
Test name
Test status
Simulation time 364222097826 ps
CPU time 213.55 seconds
Started Jul 23 07:02:09 PM PDT 24
Finished Jul 23 07:05:44 PM PDT 24
Peak memory 201192 kb
Host smart-2d5011c2-4777-44c6-82ff-0dbc14031055
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353737776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3353737776
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2481205758
Short name T623
Test name
Test status
Simulation time 591651900826 ps
CPU time 371.37 seconds
Started Jul 23 07:02:10 PM PDT 24
Finished Jul 23 07:08:23 PM PDT 24
Peak memory 201228 kb
Host smart-c03a40ed-4a1f-4230-afab-7cb56bc6c52c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481205758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2481205758
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2493240060
Short name T556
Test name
Test status
Simulation time 62805764896 ps
CPU time 246.36 seconds
Started Jul 23 07:02:11 PM PDT 24
Finished Jul 23 07:06:19 PM PDT 24
Peak memory 201672 kb
Host smart-8c6cd238-b893-485f-b66a-015886c91559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493240060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2493240060
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3379876479
Short name T641
Test name
Test status
Simulation time 31084550488 ps
CPU time 37.28 seconds
Started Jul 23 07:02:12 PM PDT 24
Finished Jul 23 07:02:51 PM PDT 24
Peak memory 201064 kb
Host smart-a66a8a4b-eedf-414f-a173-c88859e5523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379876479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3379876479
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.9891041
Short name T778
Test name
Test status
Simulation time 5305307329 ps
CPU time 11.38 seconds
Started Jul 23 07:02:07 PM PDT 24
Finished Jul 23 07:02:20 PM PDT 24
Peak memory 201104 kb
Host smart-918e4f9f-8949-4c1d-baa9-fb998c4ecf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9891041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.9891041
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1278332588
Short name T719
Test name
Test status
Simulation time 5642150708 ps
CPU time 13.55 seconds
Started Jul 23 07:02:07 PM PDT 24
Finished Jul 23 07:02:22 PM PDT 24
Peak memory 201104 kb
Host smart-bbacacfe-7407-4b0e-b580-ac25cbf02247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278332588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1278332588
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2673760358
Short name T665
Test name
Test status
Simulation time 336801356743 ps
CPU time 582 seconds
Started Jul 23 07:02:14 PM PDT 24
Finished Jul 23 07:11:57 PM PDT 24
Peak memory 201696 kb
Host smart-7969cebb-44ec-46ef-afc4-df7aa0e46ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673760358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2673760358
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3852967170
Short name T30
Test name
Test status
Simulation time 34218842001 ps
CPU time 87.67 seconds
Started Jul 23 07:02:10 PM PDT 24
Finished Jul 23 07:03:39 PM PDT 24
Peak memory 210328 kb
Host smart-e23b18f8-e0df-49fc-8b66-4ed84ebc8891
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852967170 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3852967170
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2289917362
Short name T568
Test name
Test status
Simulation time 556434994 ps
CPU time 0.89 seconds
Started Jul 23 07:02:19 PM PDT 24
Finished Jul 23 07:02:21 PM PDT 24
Peak memory 201040 kb
Host smart-e6e0f438-070a-4199-bf43-b78a2cd7f031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289917362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2289917362
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1615444986
Short name T714
Test name
Test status
Simulation time 165426632349 ps
CPU time 382.21 seconds
Started Jul 23 07:02:19 PM PDT 24
Finished Jul 23 07:08:42 PM PDT 24
Peak memory 201300 kb
Host smart-d8ef0cba-c2c5-434e-8f8f-09bf8f4305ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615444986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1615444986
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3045055812
Short name T633
Test name
Test status
Simulation time 353216382431 ps
CPU time 97.64 seconds
Started Jul 23 07:02:15 PM PDT 24
Finished Jul 23 07:03:53 PM PDT 24
Peak memory 201220 kb
Host smart-b6c41a6e-96a7-46f6-9067-a63d115f9dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045055812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3045055812
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1564916082
Short name T81
Test name
Test status
Simulation time 499472864732 ps
CPU time 330.66 seconds
Started Jul 23 07:02:14 PM PDT 24
Finished Jul 23 07:07:45 PM PDT 24
Peak memory 201220 kb
Host smart-3e3e5870-2868-44c2-974b-7f33f76e0365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564916082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1564916082
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.909601648
Short name T616
Test name
Test status
Simulation time 166742781206 ps
CPU time 363.35 seconds
Started Jul 23 07:02:12 PM PDT 24
Finished Jul 23 07:08:17 PM PDT 24
Peak memory 201212 kb
Host smart-92f70e8c-eee8-46f6-acea-c7b9aa7e4420
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=909601648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.909601648
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1790009555
Short name T775
Test name
Test status
Simulation time 331426746313 ps
CPU time 204.48 seconds
Started Jul 23 07:02:10 PM PDT 24
Finished Jul 23 07:05:36 PM PDT 24
Peak memory 201236 kb
Host smart-e942b07b-84e1-41d4-ace5-480ebcf70f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790009555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1790009555
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.944371568
Short name T580
Test name
Test status
Simulation time 166479947289 ps
CPU time 99.71 seconds
Started Jul 23 07:02:16 PM PDT 24
Finished Jul 23 07:03:57 PM PDT 24
Peak memory 201192 kb
Host smart-0be135ca-46c9-466a-9b5f-85ad1126600f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=944371568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.944371568
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.798653714
Short name T796
Test name
Test status
Simulation time 340246208488 ps
CPU time 184.02 seconds
Started Jul 23 07:02:19 PM PDT 24
Finished Jul 23 07:05:24 PM PDT 24
Peak memory 201248 kb
Host smart-33a0f72a-0fd4-4082-92e1-e2fedb43cda3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798653714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.798653714
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3751715372
Short name T629
Test name
Test status
Simulation time 193227352133 ps
CPU time 44.84 seconds
Started Jul 23 07:02:17 PM PDT 24
Finished Jul 23 07:03:02 PM PDT 24
Peak memory 201236 kb
Host smart-c4cf91b9-b5db-4d32-b6ae-8f375f7fa42a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751715372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3751715372
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2072069736
Short name T648
Test name
Test status
Simulation time 115003001609 ps
CPU time 431.16 seconds
Started Jul 23 07:02:19 PM PDT 24
Finished Jul 23 07:09:31 PM PDT 24
Peak memory 201676 kb
Host smart-460f8995-87b1-4c2b-aafc-b0e6c5f84ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072069736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2072069736
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3685966884
Short name T10
Test name
Test status
Simulation time 44297746114 ps
CPU time 52.39 seconds
Started Jul 23 07:02:17 PM PDT 24
Finished Jul 23 07:03:10 PM PDT 24
Peak memory 201084 kb
Host smart-06e1d322-74a4-44ed-a1bf-acb272ae73e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685966884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3685966884
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3608212506
Short name T123
Test name
Test status
Simulation time 3952490526 ps
CPU time 9.09 seconds
Started Jul 23 07:02:17 PM PDT 24
Finished Jul 23 07:02:26 PM PDT 24
Peak memory 200988 kb
Host smart-bf12a26c-4637-407f-8349-89fd1ff38e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608212506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3608212506
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1437169491
Short name T713
Test name
Test status
Simulation time 6047500816 ps
CPU time 11.1 seconds
Started Jul 23 07:02:19 PM PDT 24
Finished Jul 23 07:02:30 PM PDT 24
Peak memory 201044 kb
Host smart-721270c4-f9e8-4da2-90d5-fe7c3383e126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437169491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1437169491
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.4218287472
Short name T416
Test name
Test status
Simulation time 92307073759 ps
CPU time 226.53 seconds
Started Jul 23 07:02:16 PM PDT 24
Finished Jul 23 07:06:04 PM PDT 24
Peak memory 201028 kb
Host smart-53342604-de89-4b2d-bc22-f4104bb1689c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218287472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.4218287472
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.457942606
Short name T774
Test name
Test status
Simulation time 248519794621 ps
CPU time 137.01 seconds
Started Jul 23 07:02:19 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 201356 kb
Host smart-fbcc2518-be2c-4528-b4ab-9690b7ad76c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457942606 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.457942606
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.4120867858
Short name T442
Test name
Test status
Simulation time 456918973 ps
CPU time 0.9 seconds
Started Jul 23 07:02:34 PM PDT 24
Finished Jul 23 07:02:35 PM PDT 24
Peak memory 200940 kb
Host smart-7f7e216f-dbe8-4172-864e-8f171b910f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120867858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.4120867858
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.103128287
Short name T159
Test name
Test status
Simulation time 352054287207 ps
CPU time 192.49 seconds
Started Jul 23 07:02:23 PM PDT 24
Finished Jul 23 07:05:37 PM PDT 24
Peak memory 201216 kb
Host smart-efca6fba-72b6-449e-aa28-c5345442e4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103128287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.103128287
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3054465724
Short name T742
Test name
Test status
Simulation time 485740160652 ps
CPU time 1048.49 seconds
Started Jul 23 07:02:17 PM PDT 24
Finished Jul 23 07:19:46 PM PDT 24
Peak memory 201216 kb
Host smart-4041a452-e491-4d66-a3d0-6875d1db5bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054465724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3054465724
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3691479799
Short name T740
Test name
Test status
Simulation time 486682024926 ps
CPU time 1217.64 seconds
Started Jul 23 07:02:16 PM PDT 24
Finished Jul 23 07:22:34 PM PDT 24
Peak memory 201224 kb
Host smart-5f576ae4-3c40-404a-a2de-8effab738cb1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691479799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3691479799
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.652727352
Short name T649
Test name
Test status
Simulation time 165250176741 ps
CPU time 60.19 seconds
Started Jul 23 07:02:15 PM PDT 24
Finished Jul 23 07:03:16 PM PDT 24
Peak memory 201232 kb
Host smart-e650265b-2b9c-449e-a5fb-cac802b947b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=652727352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.652727352
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.158276547
Short name T279
Test name
Test status
Simulation time 250085182939 ps
CPU time 303.98 seconds
Started Jul 23 07:02:17 PM PDT 24
Finished Jul 23 07:07:22 PM PDT 24
Peak memory 201248 kb
Host smart-b270720c-6931-460a-b638-33d5e6948402
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158276547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.158276547
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3569405483
Short name T404
Test name
Test status
Simulation time 599818122166 ps
CPU time 1353.88 seconds
Started Jul 23 07:02:23 PM PDT 24
Finished Jul 23 07:24:58 PM PDT 24
Peak memory 201236 kb
Host smart-759dc326-6d18-4f20-a9a5-e0269e3cacfe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569405483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3569405483
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1989155873
Short name T39
Test name
Test status
Simulation time 101450782304 ps
CPU time 423.78 seconds
Started Jul 23 07:02:25 PM PDT 24
Finished Jul 23 07:09:29 PM PDT 24
Peak memory 201624 kb
Host smart-39f9c900-ad6c-4548-a58e-2e3e78b4f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989155873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1989155873
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.174039306
Short name T723
Test name
Test status
Simulation time 29644151558 ps
CPU time 17.19 seconds
Started Jul 23 07:02:25 PM PDT 24
Finished Jul 23 07:02:43 PM PDT 24
Peak memory 200980 kb
Host smart-2b61601e-29dc-4adf-bcdc-005264d496be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174039306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.174039306
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1701415039
Short name T474
Test name
Test status
Simulation time 3536518972 ps
CPU time 8.46 seconds
Started Jul 23 07:02:23 PM PDT 24
Finished Jul 23 07:02:32 PM PDT 24
Peak memory 201128 kb
Host smart-4521deef-3ce7-4c8c-8abd-98dc211eee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701415039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1701415039
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3262766451
Short name T610
Test name
Test status
Simulation time 6309410989 ps
CPU time 1.86 seconds
Started Jul 23 07:02:16 PM PDT 24
Finished Jul 23 07:02:19 PM PDT 24
Peak memory 201080 kb
Host smart-f6a5483f-0416-41e8-8cd2-974be15db113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262766451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3262766451
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.4023961015
Short name T490
Test name
Test status
Simulation time 30121959237 ps
CPU time 128.64 seconds
Started Jul 23 07:02:23 PM PDT 24
Finished Jul 23 07:04:32 PM PDT 24
Peak memory 209964 kb
Host smart-6bfe7f60-191c-418a-b869-1f87d9bc4c29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023961015 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.4023961015
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1539964719
Short name T586
Test name
Test status
Simulation time 456416784 ps
CPU time 1.62 seconds
Started Jul 23 07:02:29 PM PDT 24
Finished Jul 23 07:02:31 PM PDT 24
Peak memory 200892 kb
Host smart-ccb7d25c-1e24-424f-8126-61b8f48ac383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539964719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1539964719
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2230894445
Short name T517
Test name
Test status
Simulation time 340603511844 ps
CPU time 141.37 seconds
Started Jul 23 07:02:29 PM PDT 24
Finished Jul 23 07:04:51 PM PDT 24
Peak memory 201204 kb
Host smart-0a6dec1f-8485-4959-964d-ecd7252fb4a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230894445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2230894445
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3320047343
Short name T503
Test name
Test status
Simulation time 166092158752 ps
CPU time 387.56 seconds
Started Jul 23 07:02:31 PM PDT 24
Finished Jul 23 07:09:00 PM PDT 24
Peak memory 201288 kb
Host smart-fb10b0bd-3e4a-4ef6-9ec0-a2901d1f6ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320047343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3320047343
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.4247005366
Short name T293
Test name
Test status
Simulation time 326700094447 ps
CPU time 198.34 seconds
Started Jul 23 07:02:28 PM PDT 24
Finished Jul 23 07:05:46 PM PDT 24
Peak memory 201296 kb
Host smart-880cfb04-7dad-457f-9c35-d47cda625a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247005366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.4247005366
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2573449851
Short name T447
Test name
Test status
Simulation time 329520141465 ps
CPU time 729.9 seconds
Started Jul 23 07:02:30 PM PDT 24
Finished Jul 23 07:14:41 PM PDT 24
Peak memory 201228 kb
Host smart-2566c686-9352-4ccb-9bd6-e78dfd7e383b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573449851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2573449851
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3084812457
Short name T535
Test name
Test status
Simulation time 162801618012 ps
CPU time 347.74 seconds
Started Jul 23 07:02:23 PM PDT 24
Finished Jul 23 07:08:11 PM PDT 24
Peak memory 201224 kb
Host smart-aec6f018-d476-4955-b595-c175c24a95ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084812457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3084812457
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.4007879671
Short name T631
Test name
Test status
Simulation time 495127890670 ps
CPU time 266.68 seconds
Started Jul 23 07:02:23 PM PDT 24
Finished Jul 23 07:06:50 PM PDT 24
Peak memory 201308 kb
Host smart-c8f774d2-b38a-41a4-9818-9f3d53874087
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007879671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.4007879671
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1528638654
Short name T95
Test name
Test status
Simulation time 403077561787 ps
CPU time 229.99 seconds
Started Jul 23 07:02:29 PM PDT 24
Finished Jul 23 07:06:20 PM PDT 24
Peak memory 201292 kb
Host smart-a9e90978-5e5b-48ab-8b56-f6be460db704
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528638654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1528638654
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3820292509
Short name T727
Test name
Test status
Simulation time 585836752317 ps
CPU time 392.18 seconds
Started Jul 23 07:02:29 PM PDT 24
Finished Jul 23 07:09:02 PM PDT 24
Peak memory 201252 kb
Host smart-085cb351-2c5c-4bee-9547-f74302695013
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820292509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3820292509
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3479318442
Short name T721
Test name
Test status
Simulation time 108486071244 ps
CPU time 259.11 seconds
Started Jul 23 07:02:29 PM PDT 24
Finished Jul 23 07:06:48 PM PDT 24
Peak memory 201684 kb
Host smart-c1418d52-a13c-4bb7-97fd-2cc663c26850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479318442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3479318442
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.4227704172
Short name T476
Test name
Test status
Simulation time 43770812625 ps
CPU time 34.22 seconds
Started Jul 23 07:02:28 PM PDT 24
Finished Jul 23 07:03:03 PM PDT 24
Peak memory 201072 kb
Host smart-ca892a01-1d3a-4148-b0fc-1a3c3262d54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227704172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.4227704172
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2440335944
Short name T76
Test name
Test status
Simulation time 5179841066 ps
CPU time 11.75 seconds
Started Jul 23 07:02:31 PM PDT 24
Finished Jul 23 07:02:44 PM PDT 24
Peak memory 201072 kb
Host smart-73a33ade-aada-485f-ad56-afa43b50251c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440335944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2440335944
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3113966604
Short name T606
Test name
Test status
Simulation time 6145170844 ps
CPU time 1.5 seconds
Started Jul 23 07:02:23 PM PDT 24
Finished Jul 23 07:02:26 PM PDT 24
Peak memory 201076 kb
Host smart-caeb5088-e3c5-4167-9261-9d95a932a6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113966604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3113966604
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1654798450
Short name T668
Test name
Test status
Simulation time 187635676160 ps
CPU time 387.44 seconds
Started Jul 23 07:02:31 PM PDT 24
Finished Jul 23 07:08:59 PM PDT 24
Peak memory 201244 kb
Host smart-72a0ccd5-317f-480e-8590-78b9fff7620d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654798450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1654798450
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2254380081
Short name T537
Test name
Test status
Simulation time 177540879340 ps
CPU time 334.46 seconds
Started Jul 23 07:02:30 PM PDT 24
Finished Jul 23 07:08:05 PM PDT 24
Peak memory 209996 kb
Host smart-e5263e8a-91ff-42d5-964a-8efeaa7f3c2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254380081 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2254380081
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.700469172
Short name T518
Test name
Test status
Simulation time 453758869 ps
CPU time 0.79 seconds
Started Jul 23 07:00:02 PM PDT 24
Finished Jul 23 07:00:04 PM PDT 24
Peak memory 201004 kb
Host smart-2598ef2c-a737-4b14-85be-a7c2ee159ab3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700469172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.700469172
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3617981455
Short name T38
Test name
Test status
Simulation time 185969757422 ps
CPU time 113.17 seconds
Started Jul 23 07:00:09 PM PDT 24
Finished Jul 23 07:02:03 PM PDT 24
Peak memory 201224 kb
Host smart-33a2f355-cacf-4da1-a532-ea425d0952bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617981455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3617981455
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.4186003409
Short name T521
Test name
Test status
Simulation time 541610425552 ps
CPU time 329.63 seconds
Started Jul 23 07:00:14 PM PDT 24
Finished Jul 23 07:05:45 PM PDT 24
Peak memory 201316 kb
Host smart-24e72e85-44c8-420b-9beb-17dbcdf8c5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186003409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.4186003409
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.4116350271
Short name T224
Test name
Test status
Simulation time 485149502127 ps
CPU time 401.07 seconds
Started Jul 23 07:00:03 PM PDT 24
Finished Jul 23 07:06:45 PM PDT 24
Peak memory 201292 kb
Host smart-10e71361-df17-43e6-ae0f-72e22406d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116350271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.4116350271
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1390662849
Short name T2
Test name
Test status
Simulation time 484152398099 ps
CPU time 570.77 seconds
Started Jul 23 07:00:15 PM PDT 24
Finished Jul 23 07:09:46 PM PDT 24
Peak memory 201212 kb
Host smart-85d7ebdb-778f-4a6f-9625-9576d0f2b59b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390662849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1390662849
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2141826897
Short name T252
Test name
Test status
Simulation time 328992293702 ps
CPU time 356.1 seconds
Started Jul 23 07:00:07 PM PDT 24
Finished Jul 23 07:06:05 PM PDT 24
Peak memory 201316 kb
Host smart-297c1f6b-5d77-47e5-b192-00c5e290f996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141826897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2141826897
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3778928484
Short name T625
Test name
Test status
Simulation time 164520435107 ps
CPU time 95.43 seconds
Started Jul 23 07:00:14 PM PDT 24
Finished Jul 23 07:01:50 PM PDT 24
Peak memory 201228 kb
Host smart-8d2e8b16-9450-43a4-bfc0-e244cfcaa66e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778928484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3778928484
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3546790797
Short name T620
Test name
Test status
Simulation time 186700267970 ps
CPU time 432.91 seconds
Started Jul 23 07:00:11 PM PDT 24
Finished Jul 23 07:07:25 PM PDT 24
Peak memory 201228 kb
Host smart-360d1d87-bd5b-4153-866b-41a469aa4e3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546790797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3546790797
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.544301747
Short name T574
Test name
Test status
Simulation time 194086252180 ps
CPU time 119.92 seconds
Started Jul 23 07:00:02 PM PDT 24
Finished Jul 23 07:02:04 PM PDT 24
Peak memory 201144 kb
Host smart-0b8d6944-c805-4eb9-af68-8244b1d79638
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544301747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.544301747
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.761950523
Short name T92
Test name
Test status
Simulation time 129366832759 ps
CPU time 651.45 seconds
Started Jul 23 07:00:15 PM PDT 24
Finished Jul 23 07:11:07 PM PDT 24
Peak memory 201684 kb
Host smart-dc338b5d-d053-4d62-b17e-3c6e6e586b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761950523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.761950523
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2008821930
Short name T529
Test name
Test status
Simulation time 32351338711 ps
CPU time 21.94 seconds
Started Jul 23 07:00:05 PM PDT 24
Finished Jul 23 07:00:28 PM PDT 24
Peak memory 201076 kb
Host smart-d5186b3e-5ac2-417a-afc1-38251987755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008821930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2008821930
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1818526970
Short name T611
Test name
Test status
Simulation time 5348488806 ps
CPU time 3.48 seconds
Started Jul 23 07:00:10 PM PDT 24
Finished Jul 23 07:00:14 PM PDT 24
Peak memory 201072 kb
Host smart-e7b74e2f-2e9a-4306-8ecd-a1de4d6a2979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818526970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1818526970
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2427884047
Short name T70
Test name
Test status
Simulation time 8160381106 ps
CPU time 5.46 seconds
Started Jul 23 07:00:14 PM PDT 24
Finished Jul 23 07:00:20 PM PDT 24
Peak memory 217952 kb
Host smart-da8d4d54-df21-4644-9fa5-b133c7ab66e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427884047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2427884047
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2048050615
Short name T520
Test name
Test status
Simulation time 5553052627 ps
CPU time 13.59 seconds
Started Jul 23 07:00:11 PM PDT 24
Finished Jul 23 07:00:25 PM PDT 24
Peak memory 201068 kb
Host smart-47bce895-e8d1-4735-a906-e8a677ae992c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048050615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2048050615
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4121779868
Short name T643
Test name
Test status
Simulation time 335859632889 ps
CPU time 749.24 seconds
Started Jul 23 07:00:02 PM PDT 24
Finished Jul 23 07:12:33 PM PDT 24
Peak memory 201144 kb
Host smart-6a28ac3f-d0a7-4efe-8379-6b8388536bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121779868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4121779868
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1037449857
Short name T18
Test name
Test status
Simulation time 9627976627 ps
CPU time 22.49 seconds
Started Jul 23 07:00:08 PM PDT 24
Finished Jul 23 07:00:32 PM PDT 24
Peak memory 201384 kb
Host smart-27570400-935b-4adb-88d8-af63746f4b6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037449857 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1037449857
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3682003816
Short name T776
Test name
Test status
Simulation time 464526516 ps
CPU time 1.72 seconds
Started Jul 23 07:02:35 PM PDT 24
Finished Jul 23 07:02:38 PM PDT 24
Peak memory 200928 kb
Host smart-3bf32902-8d50-4ab0-8982-971da7ad8b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682003816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3682003816
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.4264033705
Short name T247
Test name
Test status
Simulation time 179720574995 ps
CPU time 197.12 seconds
Started Jul 23 07:02:37 PM PDT 24
Finished Jul 23 07:05:54 PM PDT 24
Peak memory 201220 kb
Host smart-812a7af8-6203-4368-b2a1-1b5610843dfc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264033705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.4264033705
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.553873574
Short name T716
Test name
Test status
Simulation time 518194341665 ps
CPU time 279.76 seconds
Started Jul 23 07:02:35 PM PDT 24
Finished Jul 23 07:07:15 PM PDT 24
Peak memory 201256 kb
Host smart-657ab8a3-c5df-4e37-b278-85f264059602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553873574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.553873574
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1072018373
Short name T271
Test name
Test status
Simulation time 497618303662 ps
CPU time 1097.31 seconds
Started Jul 23 07:02:30 PM PDT 24
Finished Jul 23 07:20:48 PM PDT 24
Peak memory 201200 kb
Host smart-527fdf44-4938-4a54-ac5a-3464d096d63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072018373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1072018373
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1356204796
Short name T401
Test name
Test status
Simulation time 488961222387 ps
CPU time 612.29 seconds
Started Jul 23 07:02:29 PM PDT 24
Finished Jul 23 07:12:42 PM PDT 24
Peak memory 201204 kb
Host smart-bc2fba7e-b71b-485c-bf7a-e72de7b68f2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356204796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1356204796
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1567321222
Short name T181
Test name
Test status
Simulation time 497087981401 ps
CPU time 247.12 seconds
Started Jul 23 07:02:35 PM PDT 24
Finished Jul 23 07:06:43 PM PDT 24
Peak memory 201120 kb
Host smart-c6c52a03-9134-4276-8b0f-0fe79f8b7a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567321222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1567321222
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.340210171
Short name T362
Test name
Test status
Simulation time 160430599122 ps
CPU time 353.68 seconds
Started Jul 23 07:02:30 PM PDT 24
Finished Jul 23 07:08:24 PM PDT 24
Peak memory 201156 kb
Host smart-69b92207-5e7d-4f80-a461-7ac750130580
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=340210171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.340210171
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1648813478
Short name T790
Test name
Test status
Simulation time 198380881363 ps
CPU time 358.43 seconds
Started Jul 23 07:02:36 PM PDT 24
Finished Jul 23 07:08:35 PM PDT 24
Peak memory 201180 kb
Host smart-7fa809ba-e672-4b79-9be7-ddc55ef9a7b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648813478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1648813478
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2674469100
Short name T45
Test name
Test status
Simulation time 109847165464 ps
CPU time 612.2 seconds
Started Jul 23 07:02:36 PM PDT 24
Finished Jul 23 07:12:49 PM PDT 24
Peak memory 201644 kb
Host smart-7659a8e0-6ddc-4d1b-91f3-5165c6b17cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674469100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2674469100
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.4256495935
Short name T715
Test name
Test status
Simulation time 27004299980 ps
CPU time 15.97 seconds
Started Jul 23 07:02:36 PM PDT 24
Finished Jul 23 07:02:53 PM PDT 24
Peak memory 201076 kb
Host smart-ae6493d8-51b7-4ddf-9b73-33e52d2eb280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256495935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.4256495935
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1773273770
Short name T375
Test name
Test status
Simulation time 3939333022 ps
CPU time 2.77 seconds
Started Jul 23 07:02:37 PM PDT 24
Finished Jul 23 07:02:40 PM PDT 24
Peak memory 201020 kb
Host smart-9f8c40d9-529f-40c4-8082-14fc182ac270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773273770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1773273770
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.371711877
Short name T496
Test name
Test status
Simulation time 5884900365 ps
CPU time 11.48 seconds
Started Jul 23 07:02:35 PM PDT 24
Finished Jul 23 07:02:48 PM PDT 24
Peak memory 201012 kb
Host smart-464edd7d-9830-443f-a132-cc8b03fcf396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371711877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.371711877
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2414035080
Short name T210
Test name
Test status
Simulation time 77873163136 ps
CPU time 461.12 seconds
Started Jul 23 07:02:36 PM PDT 24
Finished Jul 23 07:10:18 PM PDT 24
Peak memory 211060 kb
Host smart-7dc832a9-ec77-47ba-9434-a6862f39b07d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414035080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2414035080
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.339974757
Short name T636
Test name
Test status
Simulation time 6090087216 ps
CPU time 11.88 seconds
Started Jul 23 07:02:36 PM PDT 24
Finished Jul 23 07:02:49 PM PDT 24
Peak memory 209624 kb
Host smart-8824ba54-1114-4a82-945a-796f15cdd3b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339974757 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.339974757
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3180818667
Short name T509
Test name
Test status
Simulation time 304236019 ps
CPU time 1.27 seconds
Started Jul 23 07:02:47 PM PDT 24
Finished Jul 23 07:02:49 PM PDT 24
Peak memory 201036 kb
Host smart-6b1d8305-9c3c-4bb5-9b29-4576f29090b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180818667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3180818667
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2847254781
Short name T234
Test name
Test status
Simulation time 259775988753 ps
CPU time 175.85 seconds
Started Jul 23 07:02:40 PM PDT 24
Finished Jul 23 07:05:36 PM PDT 24
Peak memory 201240 kb
Host smart-8493aefb-bf11-4b04-b182-e9994203001e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847254781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2847254781
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1663473692
Short name T627
Test name
Test status
Simulation time 328516815011 ps
CPU time 217.4 seconds
Started Jul 23 07:02:42 PM PDT 24
Finished Jul 23 07:06:20 PM PDT 24
Peak memory 201244 kb
Host smart-8abd54c9-1461-4a13-a076-5f86a965cf0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663473692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1663473692
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1607645471
Short name T671
Test name
Test status
Simulation time 162260437764 ps
CPU time 341.17 seconds
Started Jul 23 07:02:35 PM PDT 24
Finished Jul 23 07:08:17 PM PDT 24
Peak memory 201308 kb
Host smart-88f2d307-1243-455c-83d4-991aab008586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607645471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1607645471
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3870597810
Short name T150
Test name
Test status
Simulation time 486337922322 ps
CPU time 1002.66 seconds
Started Jul 23 07:02:42 PM PDT 24
Finished Jul 23 07:19:25 PM PDT 24
Peak memory 201216 kb
Host smart-42fefa13-fca0-4bd1-bb16-ff1ab554c913
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870597810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3870597810
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.411597180
Short name T98
Test name
Test status
Simulation time 361853101522 ps
CPU time 196.79 seconds
Started Jul 23 07:02:41 PM PDT 24
Finished Jul 23 07:05:58 PM PDT 24
Peak memory 201176 kb
Host smart-faf9b24a-010c-425d-b76c-64afd6289e6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411597180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.411597180
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2320437286
Short name T260
Test name
Test status
Simulation time 193965113047 ps
CPU time 108.84 seconds
Started Jul 23 07:02:42 PM PDT 24
Finished Jul 23 07:04:32 PM PDT 24
Peak memory 201204 kb
Host smart-bb2fb4a6-c4e5-4835-b50c-599e5aa90006
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320437286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2320437286
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2231680152
Short name T43
Test name
Test status
Simulation time 67665864021 ps
CPU time 223.3 seconds
Started Jul 23 07:02:41 PM PDT 24
Finished Jul 23 07:06:25 PM PDT 24
Peak memory 201696 kb
Host smart-ddb97708-ae45-45b5-93e2-99c28426294f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231680152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2231680152
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1894824822
Short name T380
Test name
Test status
Simulation time 29110509247 ps
CPU time 33.56 seconds
Started Jul 23 07:02:42 PM PDT 24
Finished Jul 23 07:03:16 PM PDT 24
Peak memory 201092 kb
Host smart-5e1a458e-a1c9-4dde-8989-e4d3be4f9cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894824822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1894824822
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.97612812
Short name T85
Test name
Test status
Simulation time 4944913721 ps
CPU time 1.51 seconds
Started Jul 23 07:02:42 PM PDT 24
Finished Jul 23 07:02:44 PM PDT 24
Peak memory 201008 kb
Host smart-f457b32a-a66e-4deb-94fd-1ebe07d8376a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97612812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.97612812
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3713094956
Short name T507
Test name
Test status
Simulation time 6041760577 ps
CPU time 4.34 seconds
Started Jul 23 07:02:35 PM PDT 24
Finished Jul 23 07:02:40 PM PDT 24
Peak memory 201200 kb
Host smart-d2308f4a-5511-4539-a439-cdb6e48d2956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713094956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3713094956
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2915309343
Short name T258
Test name
Test status
Simulation time 286264006134 ps
CPU time 575.69 seconds
Started Jul 23 07:02:49 PM PDT 24
Finished Jul 23 07:12:25 PM PDT 24
Peak memory 201732 kb
Host smart-1f992fee-7700-459f-9690-8e30bc78f0d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915309343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2915309343
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3622747485
Short name T670
Test name
Test status
Simulation time 54632249975 ps
CPU time 133.62 seconds
Started Jul 23 07:02:47 PM PDT 24
Finished Jul 23 07:05:02 PM PDT 24
Peak memory 210152 kb
Host smart-143f6002-8b33-4ba3-8f52-3c5e5cbfc0a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622747485 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3622747485
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.673977682
Short name T494
Test name
Test status
Simulation time 503851599 ps
CPU time 0.9 seconds
Started Jul 23 07:02:52 PM PDT 24
Finished Jul 23 07:02:54 PM PDT 24
Peak memory 201016 kb
Host smart-04e0f723-94ee-47ba-b5d3-2805722f7002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673977682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.673977682
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2673928166
Short name T559
Test name
Test status
Simulation time 166091309584 ps
CPU time 104.77 seconds
Started Jul 23 07:02:48 PM PDT 24
Finished Jul 23 07:04:34 PM PDT 24
Peak memory 201132 kb
Host smart-2a7656b4-f74e-4c9f-b041-83a7e92ac309
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673928166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2673928166
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1695116867
Short name T186
Test name
Test status
Simulation time 345058160287 ps
CPU time 646.49 seconds
Started Jul 23 07:02:46 PM PDT 24
Finished Jul 23 07:13:33 PM PDT 24
Peak memory 201260 kb
Host smart-dd11b1e0-00be-4048-9d17-0f5ef2114757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695116867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1695116867
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4264863276
Short name T11
Test name
Test status
Simulation time 492649772709 ps
CPU time 571 seconds
Started Jul 23 07:02:46 PM PDT 24
Finished Jul 23 07:12:18 PM PDT 24
Peak memory 201396 kb
Host smart-9db68af3-00f0-4032-a20a-c73d4d5f2ef4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264863276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4264863276
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.618268780
Short name T344
Test name
Test status
Simulation time 167559803067 ps
CPU time 95.13 seconds
Started Jul 23 07:02:49 PM PDT 24
Finished Jul 23 07:04:24 PM PDT 24
Peak memory 201256 kb
Host smart-3a39eebd-336d-43aa-bc9d-aca513fec0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618268780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.618268780
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2301671444
Short name T379
Test name
Test status
Simulation time 493645531580 ps
CPU time 291.86 seconds
Started Jul 23 07:02:49 PM PDT 24
Finished Jul 23 07:07:42 PM PDT 24
Peak memory 201172 kb
Host smart-3219a3d1-7d94-4898-a0c3-15651f5e4942
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301671444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2301671444
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2974203610
Short name T225
Test name
Test status
Simulation time 174555734270 ps
CPU time 377.97 seconds
Started Jul 23 07:02:48 PM PDT 24
Finished Jul 23 07:09:06 PM PDT 24
Peak memory 201244 kb
Host smart-8e73df74-a7f3-466e-bcb9-952c8a2d3c00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974203610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2974203610
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.736099679
Short name T650
Test name
Test status
Simulation time 399465441863 ps
CPU time 435.08 seconds
Started Jul 23 07:02:52 PM PDT 24
Finished Jul 23 07:10:08 PM PDT 24
Peak memory 201220 kb
Host smart-9c218a0d-3d12-46d0-8cf4-3898cffe9596
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736099679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.736099679
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3543599701
Short name T759
Test name
Test status
Simulation time 122093256146 ps
CPU time 426.35 seconds
Started Jul 23 07:02:49 PM PDT 24
Finished Jul 23 07:09:56 PM PDT 24
Peak memory 201676 kb
Host smart-56d04ba6-d52b-46fd-aeac-a85323aca83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543599701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3543599701
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.251347553
Short name T405
Test name
Test status
Simulation time 24485476838 ps
CPU time 5.49 seconds
Started Jul 23 07:02:52 PM PDT 24
Finished Jul 23 07:02:59 PM PDT 24
Peak memory 201064 kb
Host smart-424a0f2d-fba9-4bc2-b063-0ac87522c470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251347553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.251347553
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2450239668
Short name T374
Test name
Test status
Simulation time 4403554149 ps
CPU time 11.2 seconds
Started Jul 23 07:02:47 PM PDT 24
Finished Jul 23 07:02:59 PM PDT 24
Peak memory 201060 kb
Host smart-22b95705-1b75-4cfb-a15e-fc7cb1b96149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450239668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2450239668
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2993584403
Short name T411
Test name
Test status
Simulation time 6068009929 ps
CPU time 4.16 seconds
Started Jul 23 07:02:45 PM PDT 24
Finished Jul 23 07:02:50 PM PDT 24
Peak memory 201096 kb
Host smart-ed49f30a-ba45-424d-836e-e3384873b846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993584403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2993584403
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3590907256
Short name T100
Test name
Test status
Simulation time 93784711038 ps
CPU time 216.67 seconds
Started Jul 23 07:02:48 PM PDT 24
Finished Jul 23 07:06:25 PM PDT 24
Peak memory 217768 kb
Host smart-a5a82e5a-23f8-4b2a-af99-392e8f24b0f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590907256 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3590907256
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1971592598
Short name T513
Test name
Test status
Simulation time 403908186 ps
CPU time 1.43 seconds
Started Jul 23 07:02:58 PM PDT 24
Finished Jul 23 07:03:00 PM PDT 24
Peak memory 200960 kb
Host smart-8db2b3b5-1944-4d57-8253-a08aaa220ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971592598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1971592598
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.824163402
Short name T161
Test name
Test status
Simulation time 497710740891 ps
CPU time 1181.33 seconds
Started Jul 23 07:02:52 PM PDT 24
Finished Jul 23 07:22:34 PM PDT 24
Peak memory 201312 kb
Host smart-775732f4-2898-43fc-9f13-a4f8f817c404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824163402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.824163402
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2321030875
Short name T167
Test name
Test status
Simulation time 484228559456 ps
CPU time 295.7 seconds
Started Jul 23 07:02:53 PM PDT 24
Finished Jul 23 07:07:49 PM PDT 24
Peak memory 201256 kb
Host smart-e8c165cb-3341-4eac-8535-8ca2b8017008
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321030875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2321030875
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3260032889
Short name T128
Test name
Test status
Simulation time 183612842810 ps
CPU time 437.15 seconds
Started Jul 23 07:02:51 PM PDT 24
Finished Jul 23 07:10:09 PM PDT 24
Peak memory 201232 kb
Host smart-15c62880-faba-410f-a12a-2080a9a68d49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260032889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3260032889
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.57191131
Short name T612
Test name
Test status
Simulation time 408636836350 ps
CPU time 240.39 seconds
Started Jul 23 07:02:52 PM PDT 24
Finished Jul 23 07:06:54 PM PDT 24
Peak memory 201240 kb
Host smart-6adae35e-eda3-4e61-a6a5-c536764bd74c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57191131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.a
dc_ctrl_filters_wakeup_fixed.57191131
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1245551819
Short name T89
Test name
Test status
Simulation time 97170637265 ps
CPU time 416.49 seconds
Started Jul 23 07:02:57 PM PDT 24
Finished Jul 23 07:09:55 PM PDT 24
Peak memory 201648 kb
Host smart-7c14ff4f-fbb8-4c72-ab5c-c255788354d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245551819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1245551819
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.204300922
Short name T565
Test name
Test status
Simulation time 38910160618 ps
CPU time 25.07 seconds
Started Jul 23 07:02:52 PM PDT 24
Finished Jul 23 07:03:18 PM PDT 24
Peak memory 201044 kb
Host smart-264c7912-790f-467f-b864-4b00ca5fefaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204300922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.204300922
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1254732035
Short name T467
Test name
Test status
Simulation time 3614206349 ps
CPU time 2.75 seconds
Started Jul 23 07:02:51 PM PDT 24
Finished Jul 23 07:02:54 PM PDT 24
Peak memory 200976 kb
Host smart-b73feddf-ad1e-410c-b123-650a9baaad11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254732035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1254732035
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1288661888
Short name T443
Test name
Test status
Simulation time 5712345060 ps
CPU time 14.44 seconds
Started Jul 23 07:02:52 PM PDT 24
Finished Jul 23 07:03:06 PM PDT 24
Peak memory 201108 kb
Host smart-c50195d4-f7b5-4d79-bb16-c8c7928cc0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288661888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1288661888
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3165708594
Short name T294
Test name
Test status
Simulation time 368709181897 ps
CPU time 303.11 seconds
Started Jul 23 07:03:00 PM PDT 24
Finished Jul 23 07:08:03 PM PDT 24
Peak memory 201216 kb
Host smart-01f989aa-d59c-4f97-837e-03e4424f3205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165708594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3165708594
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2598308610
Short name T280
Test name
Test status
Simulation time 197895276510 ps
CPU time 213.67 seconds
Started Jul 23 07:03:01 PM PDT 24
Finished Jul 23 07:06:35 PM PDT 24
Peak memory 209916 kb
Host smart-870cdbe1-d1b1-471a-a475-bb0846ce5421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598308610 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2598308610
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3345965362
Short name T361
Test name
Test status
Simulation time 309073486 ps
CPU time 0.81 seconds
Started Jul 23 07:03:10 PM PDT 24
Finished Jul 23 07:03:12 PM PDT 24
Peak memory 201020 kb
Host smart-70670756-b369-4a6a-b50d-c2d5ab202eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345965362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3345965362
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.886215033
Short name T35
Test name
Test status
Simulation time 169559433393 ps
CPU time 209.93 seconds
Started Jul 23 07:03:05 PM PDT 24
Finished Jul 23 07:06:36 PM PDT 24
Peak memory 201232 kb
Host smart-c2e99f6a-16d2-45b7-a8bd-e60182870f2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886215033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.886215033
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2275381337
Short name T657
Test name
Test status
Simulation time 323276221853 ps
CPU time 708.58 seconds
Started Jul 23 07:02:59 PM PDT 24
Finished Jul 23 07:14:49 PM PDT 24
Peak memory 201228 kb
Host smart-a48e85f4-d1d2-470e-a7e4-57365f50e14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275381337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2275381337
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.4046919509
Short name T360
Test name
Test status
Simulation time 494401543757 ps
CPU time 164.36 seconds
Started Jul 23 07:03:01 PM PDT 24
Finished Jul 23 07:05:46 PM PDT 24
Peak memory 201188 kb
Host smart-32cd7fda-da74-41d2-bbb5-d08b5aafa885
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046919509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.4046919509
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2656366041
Short name T140
Test name
Test status
Simulation time 163266534802 ps
CPU time 343.46 seconds
Started Jul 23 07:02:58 PM PDT 24
Finished Jul 23 07:08:42 PM PDT 24
Peak memory 201236 kb
Host smart-f67f8a7e-b5fe-4adf-ba26-060dd49fe2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656366041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2656366041
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3201048260
Short name T468
Test name
Test status
Simulation time 168567256174 ps
CPU time 395.3 seconds
Started Jul 23 07:03:04 PM PDT 24
Finished Jul 23 07:09:40 PM PDT 24
Peak memory 201112 kb
Host smart-7bff0346-7165-48e1-a7f2-e9c2f71e6f45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201048260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3201048260
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1884537419
Short name T199
Test name
Test status
Simulation time 592859342014 ps
CPU time 91.11 seconds
Started Jul 23 07:03:05 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 201232 kb
Host smart-26b835b5-3e64-4762-aa74-b41edc17ddab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884537419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1884537419
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.593375112
Short name T693
Test name
Test status
Simulation time 126001788778 ps
CPU time 563.43 seconds
Started Jul 23 07:03:10 PM PDT 24
Finished Jul 23 07:12:34 PM PDT 24
Peak memory 201684 kb
Host smart-27bdc203-7129-4616-a891-83d59be8fc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593375112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.593375112
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2840667562
Short name T515
Test name
Test status
Simulation time 34803293765 ps
CPU time 19.08 seconds
Started Jul 23 07:03:05 PM PDT 24
Finished Jul 23 07:03:25 PM PDT 24
Peak memory 201128 kb
Host smart-78f736e7-150f-40fc-9c8c-054ffd40de8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840667562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2840667562
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.618089510
Short name T550
Test name
Test status
Simulation time 3328387027 ps
CPU time 8.51 seconds
Started Jul 23 07:03:05 PM PDT 24
Finished Jul 23 07:03:14 PM PDT 24
Peak memory 201264 kb
Host smart-cbd5ffeb-45d3-41d6-bad7-12d117e474d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618089510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.618089510
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2172237270
Short name T763
Test name
Test status
Simulation time 5964862465 ps
CPU time 14.9 seconds
Started Jul 23 07:03:04 PM PDT 24
Finished Jul 23 07:03:20 PM PDT 24
Peak memory 201088 kb
Host smart-01a4148e-5477-4e23-b06b-5e2d986c2f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172237270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2172237270
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2265104523
Short name T336
Test name
Test status
Simulation time 538817354210 ps
CPU time 1285.33 seconds
Started Jul 23 07:03:05 PM PDT 24
Finished Jul 23 07:24:31 PM PDT 24
Peak memory 201304 kb
Host smart-8d712f40-ff87-4b1d-a5b7-42f3ecfbaa76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265104523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2265104523
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3631709790
Short name T430
Test name
Test status
Simulation time 1283807118 ps
CPU time 3.66 seconds
Started Jul 23 07:03:04 PM PDT 24
Finished Jul 23 07:03:08 PM PDT 24
Peak memory 201148 kb
Host smart-ddc3ed52-970e-4738-bb67-87551c90f93b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631709790 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3631709790
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1568617414
Short name T732
Test name
Test status
Simulation time 360271676 ps
CPU time 0.88 seconds
Started Jul 23 07:03:11 PM PDT 24
Finished Jul 23 07:03:13 PM PDT 24
Peak memory 201004 kb
Host smart-e588929a-242f-471d-ba39-a3ef78c99672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568617414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1568617414
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.181672086
Short name T781
Test name
Test status
Simulation time 160366202213 ps
CPU time 97.13 seconds
Started Jul 23 07:03:11 PM PDT 24
Finished Jul 23 07:04:49 PM PDT 24
Peak memory 201196 kb
Host smart-654a5955-d84e-4129-8296-67d8f2681bbc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181672086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.181672086
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2931519914
Short name T158
Test name
Test status
Simulation time 485746367259 ps
CPU time 330.56 seconds
Started Jul 23 07:03:10 PM PDT 24
Finished Jul 23 07:08:42 PM PDT 24
Peak memory 201304 kb
Host smart-be7f4888-d9f3-4bb0-b5da-e5c0c7762be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931519914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2931519914
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.421892815
Short name T456
Test name
Test status
Simulation time 492010703471 ps
CPU time 1180.91 seconds
Started Jul 23 07:03:12 PM PDT 24
Finished Jul 23 07:22:54 PM PDT 24
Peak memory 201212 kb
Host smart-01db1f64-5a25-40a9-91de-05bc69c05674
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=421892815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.421892815
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3083219839
Short name T180
Test name
Test status
Simulation time 334454852087 ps
CPU time 180.95 seconds
Started Jul 23 07:03:12 PM PDT 24
Finished Jul 23 07:06:14 PM PDT 24
Peak memory 201308 kb
Host smart-f8c9eb63-57c9-4c16-9a41-5694eba475fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083219839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3083219839
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1764646186
Short name T654
Test name
Test status
Simulation time 490664351576 ps
CPU time 990.04 seconds
Started Jul 23 07:03:11 PM PDT 24
Finished Jul 23 07:19:42 PM PDT 24
Peak memory 201192 kb
Host smart-6c3a9af3-e2bc-43e0-a6bc-51a59ca3e049
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764646186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1764646186
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.6343689
Short name T230
Test name
Test status
Simulation time 182231367871 ps
CPU time 202.13 seconds
Started Jul 23 07:03:10 PM PDT 24
Finished Jul 23 07:06:33 PM PDT 24
Peak memory 201092 kb
Host smart-c69715b4-5d2c-4505-8ab4-f826b2a9c742
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6343689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wa
keup.6343689
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.72206826
Short name T562
Test name
Test status
Simulation time 204095491502 ps
CPU time 171.25 seconds
Started Jul 23 07:03:10 PM PDT 24
Finished Jul 23 07:06:03 PM PDT 24
Peak memory 201212 kb
Host smart-9477f072-a0f4-455f-b628-f6df3650738c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72206826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.a
dc_ctrl_filters_wakeup_fixed.72206826
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1314887720
Short name T359
Test name
Test status
Simulation time 36753482814 ps
CPU time 20.07 seconds
Started Jul 23 07:03:09 PM PDT 24
Finished Jul 23 07:03:30 PM PDT 24
Peak memory 201096 kb
Host smart-35ca01aa-4021-48d7-b570-61d0361ba36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314887720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1314887720
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2834434559
Short name T365
Test name
Test status
Simulation time 2867319530 ps
CPU time 4.8 seconds
Started Jul 23 07:03:10 PM PDT 24
Finished Jul 23 07:03:15 PM PDT 24
Peak memory 201084 kb
Host smart-e7ea6b28-7911-4367-a860-46d61683c4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834434559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2834434559
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.826820137
Short name T368
Test name
Test status
Simulation time 5921474808 ps
CPU time 11.48 seconds
Started Jul 23 07:03:05 PM PDT 24
Finished Jul 23 07:03:17 PM PDT 24
Peak memory 201100 kb
Host smart-87613dd1-5ed2-4834-b96a-96db41a03f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826820137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.826820137
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.473010684
Short name T26
Test name
Test status
Simulation time 370982524083 ps
CPU time 388.08 seconds
Started Jul 23 07:03:11 PM PDT 24
Finished Jul 23 07:09:40 PM PDT 24
Peak memory 201248 kb
Host smart-e359cba8-f713-43e6-8294-4b0118148c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473010684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
473010684
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2954518659
Short name T646
Test name
Test status
Simulation time 397277995 ps
CPU time 0.85 seconds
Started Jul 23 07:03:18 PM PDT 24
Finished Jul 23 07:03:21 PM PDT 24
Peak memory 201036 kb
Host smart-5d4dfd12-1fa1-464a-9dd4-25a534e27f39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954518659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2954518659
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.689155906
Short name T749
Test name
Test status
Simulation time 156346838323 ps
CPU time 370.2 seconds
Started Jul 23 07:03:17 PM PDT 24
Finished Jul 23 07:09:28 PM PDT 24
Peak memory 201248 kb
Host smart-24a8d793-7e9d-48f0-8465-a661e9d0dd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689155906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.689155906
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1972109508
Short name T157
Test name
Test status
Simulation time 163469061233 ps
CPU time 191.77 seconds
Started Jul 23 07:03:19 PM PDT 24
Finished Jul 23 07:06:32 PM PDT 24
Peak memory 201144 kb
Host smart-967163cf-a03e-4bc3-8301-a5ef6a88b6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972109508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1972109508
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3631489380
Short name T618
Test name
Test status
Simulation time 489609418541 ps
CPU time 160.17 seconds
Started Jul 23 07:03:18 PM PDT 24
Finished Jul 23 07:06:00 PM PDT 24
Peak memory 201192 kb
Host smart-ca86a4af-72d3-495a-8b4e-9444afb1de81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631489380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3631489380
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3989833919
Short name T624
Test name
Test status
Simulation time 167973107489 ps
CPU time 367.25 seconds
Started Jul 23 07:03:18 PM PDT 24
Finished Jul 23 07:09:27 PM PDT 24
Peak memory 201144 kb
Host smart-69041281-96f0-4b6c-9cf1-07a36f47fc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989833919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3989833919
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3367676293
Short name T789
Test name
Test status
Simulation time 174668460356 ps
CPU time 377.24 seconds
Started Jul 23 07:03:17 PM PDT 24
Finished Jul 23 07:09:36 PM PDT 24
Peak memory 201224 kb
Host smart-87b15f52-7df7-4fb5-acf8-babf7480ace0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367676293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3367676293
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.182702669
Short name T724
Test name
Test status
Simulation time 571706624564 ps
CPU time 1365.85 seconds
Started Jul 23 07:03:17 PM PDT 24
Finished Jul 23 07:26:04 PM PDT 24
Peak memory 201208 kb
Host smart-401a1481-a686-4a2c-a1c2-11265906fb21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182702669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.182702669
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.702084820
Short name T684
Test name
Test status
Simulation time 610004754610 ps
CPU time 1408.94 seconds
Started Jul 23 07:03:19 PM PDT 24
Finished Jul 23 07:26:49 PM PDT 24
Peak memory 201260 kb
Host smart-1015b2c1-aa1e-4130-9b84-dd82ea12a706
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702084820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.702084820
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2773717480
Short name T592
Test name
Test status
Simulation time 90056176799 ps
CPU time 348.13 seconds
Started Jul 23 07:03:17 PM PDT 24
Finished Jul 23 07:09:07 PM PDT 24
Peak memory 201804 kb
Host smart-44289adf-be2b-4cdc-8356-fb52bb15cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773717480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2773717480
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2102545489
Short name T642
Test name
Test status
Simulation time 35954521010 ps
CPU time 83.06 seconds
Started Jul 23 07:03:16 PM PDT 24
Finished Jul 23 07:04:41 PM PDT 24
Peak memory 201060 kb
Host smart-9bc2c64e-5a1f-4f70-b5c7-e4c40fa1110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102545489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2102545489
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.142706226
Short name T491
Test name
Test status
Simulation time 4378568583 ps
CPU time 10.22 seconds
Started Jul 23 07:03:15 PM PDT 24
Finished Jul 23 07:03:26 PM PDT 24
Peak memory 201072 kb
Host smart-4b9e14d0-df7b-411f-a301-5ae86cbcc9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142706226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.142706226
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3014046023
Short name T666
Test name
Test status
Simulation time 5988385427 ps
CPU time 13.95 seconds
Started Jul 23 07:03:18 PM PDT 24
Finished Jul 23 07:03:33 PM PDT 24
Peak memory 201004 kb
Host smart-7630254b-33a0-4d13-86c6-0e551745da20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014046023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3014046023
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1604338192
Short name T102
Test name
Test status
Simulation time 66428964249 ps
CPU time 236.33 seconds
Started Jul 23 07:03:16 PM PDT 24
Finished Jul 23 07:07:14 PM PDT 24
Peak memory 217296 kb
Host smart-dbd908d5-13cf-44f2-8316-811230c39ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604338192 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1604338192
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3219387703
Short name T149
Test name
Test status
Simulation time 395539547 ps
CPU time 1.47 seconds
Started Jul 23 07:03:24 PM PDT 24
Finished Jul 23 07:03:26 PM PDT 24
Peak memory 201136 kb
Host smart-387213b0-a435-4eab-a97c-dce19179f90e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219387703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3219387703
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.396450686
Short name T531
Test name
Test status
Simulation time 197175388958 ps
CPU time 166.94 seconds
Started Jul 23 07:03:23 PM PDT 24
Finished Jul 23 07:06:10 PM PDT 24
Peak memory 201224 kb
Host smart-8de4eae4-3047-4c3a-88d6-12926eb59e53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396450686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.396450686
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1234812885
Short name T737
Test name
Test status
Simulation time 329264350199 ps
CPU time 806.47 seconds
Started Jul 23 07:03:17 PM PDT 24
Finished Jul 23 07:16:45 PM PDT 24
Peak memory 201236 kb
Host smart-d6f01256-b8c2-40ee-a523-06ff1ca1d3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234812885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1234812885
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.858820167
Short name T91
Test name
Test status
Simulation time 165132540856 ps
CPU time 91.26 seconds
Started Jul 23 07:03:23 PM PDT 24
Finished Jul 23 07:04:55 PM PDT 24
Peak memory 201160 kb
Host smart-d2110430-c52c-4f0a-adea-b64f905921bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=858820167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.858820167
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.817495915
Short name T792
Test name
Test status
Simulation time 327347220948 ps
CPU time 338.96 seconds
Started Jul 23 07:03:19 PM PDT 24
Finished Jul 23 07:09:00 PM PDT 24
Peak memory 201308 kb
Host smart-ff038366-055c-41ac-89b7-e133a4cd6566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817495915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.817495915
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3062502232
Short name T480
Test name
Test status
Simulation time 164823582508 ps
CPU time 54.5 seconds
Started Jul 23 07:03:17 PM PDT 24
Finished Jul 23 07:04:13 PM PDT 24
Peak memory 201192 kb
Host smart-886877ba-a9b6-4cb7-976e-ad318e1bdb68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062502232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3062502232
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1175716261
Short name T226
Test name
Test status
Simulation time 197059857445 ps
CPU time 234.63 seconds
Started Jul 23 07:03:22 PM PDT 24
Finished Jul 23 07:07:18 PM PDT 24
Peak memory 201228 kb
Host smart-4b391750-d4b8-4581-8116-252c703b3b20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175716261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1175716261
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2277204702
Short name T680
Test name
Test status
Simulation time 192780501659 ps
CPU time 213.49 seconds
Started Jul 23 07:03:23 PM PDT 24
Finished Jul 23 07:06:58 PM PDT 24
Peak memory 201204 kb
Host smart-75b43694-a397-46d8-b66b-206b7604da17
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277204702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2277204702
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.4134747071
Short name T540
Test name
Test status
Simulation time 79567199740 ps
CPU time 300.44 seconds
Started Jul 23 07:03:24 PM PDT 24
Finished Jul 23 07:08:25 PM PDT 24
Peak memory 201580 kb
Host smart-9a15d16c-d81b-41d3-9bd6-32d74fdfc1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134747071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4134747071
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.220432470
Short name T406
Test name
Test status
Simulation time 30903001056 ps
CPU time 75.62 seconds
Started Jul 23 07:03:24 PM PDT 24
Finished Jul 23 07:04:40 PM PDT 24
Peak memory 200988 kb
Host smart-f6808b75-3c69-4464-82b8-cf72fc0a21b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220432470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.220432470
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2208827800
Short name T508
Test name
Test status
Simulation time 3934752043 ps
CPU time 2.61 seconds
Started Jul 23 07:03:25 PM PDT 24
Finished Jul 23 07:03:28 PM PDT 24
Peak memory 200976 kb
Host smart-9bc590af-ede8-423d-b529-7511d2d75a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208827800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2208827800
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.69878493
Short name T461
Test name
Test status
Simulation time 5780658154 ps
CPU time 7.17 seconds
Started Jul 23 07:03:17 PM PDT 24
Finished Jul 23 07:03:26 PM PDT 24
Peak memory 201052 kb
Host smart-eae5ff68-916f-4324-a985-204cb37bb8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69878493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.69878493
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1437326993
Short name T228
Test name
Test status
Simulation time 199645077240 ps
CPU time 243.95 seconds
Started Jul 23 07:03:24 PM PDT 24
Finished Jul 23 07:07:28 PM PDT 24
Peak memory 201228 kb
Host smart-ee8668e6-114f-417e-8f4c-f43d987a32d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437326993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1437326993
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3675159447
Short name T90
Test name
Test status
Simulation time 37986177968 ps
CPU time 124.76 seconds
Started Jul 23 07:03:24 PM PDT 24
Finished Jul 23 07:05:29 PM PDT 24
Peak memory 217224 kb
Host smart-82487866-4ac8-4153-a370-56a94778cb10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675159447 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3675159447
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.4073093920
Short name T435
Test name
Test status
Simulation time 379331662 ps
CPU time 1.39 seconds
Started Jul 23 07:03:29 PM PDT 24
Finished Jul 23 07:03:31 PM PDT 24
Peak memory 201000 kb
Host smart-82c5f5b8-2b50-46e4-9e1d-134330450b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073093920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.4073093920
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2759805991
Short name T327
Test name
Test status
Simulation time 163421291454 ps
CPU time 399.82 seconds
Started Jul 23 07:03:29 PM PDT 24
Finished Jul 23 07:10:09 PM PDT 24
Peak memory 201132 kb
Host smart-1afc0650-b38a-423c-a8ae-6b6f850a4b7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759805991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2759805991
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2122893255
Short name T189
Test name
Test status
Simulation time 167423880987 ps
CPU time 184.09 seconds
Started Jul 23 07:03:30 PM PDT 24
Finished Jul 23 07:06:34 PM PDT 24
Peak memory 201288 kb
Host smart-69b38dcd-abcb-4ca3-83e2-81c107aeb74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122893255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2122893255
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2139596213
Short name T462
Test name
Test status
Simulation time 323212378646 ps
CPU time 701.13 seconds
Started Jul 23 07:03:31 PM PDT 24
Finished Jul 23 07:15:13 PM PDT 24
Peak memory 201224 kb
Host smart-d9af4b86-1c9d-42cd-b0b7-e941ad6072d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139596213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2139596213
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.75933555
Short name T169
Test name
Test status
Simulation time 159598315792 ps
CPU time 69.67 seconds
Started Jul 23 07:03:23 PM PDT 24
Finished Jul 23 07:04:34 PM PDT 24
Peak memory 201244 kb
Host smart-8a58c27e-a63a-4173-86a0-e2bd0b25765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75933555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.75933555
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.106685773
Short name T77
Test name
Test status
Simulation time 327910408693 ps
CPU time 355.47 seconds
Started Jul 23 07:03:29 PM PDT 24
Finished Jul 23 07:09:25 PM PDT 24
Peak memory 201244 kb
Host smart-a6daf372-21ce-404a-b0f8-caef57ad3ccb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=106685773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.106685773
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.846288624
Short name T126
Test name
Test status
Simulation time 607153931532 ps
CPU time 1515.06 seconds
Started Jul 23 07:03:30 PM PDT 24
Finished Jul 23 07:28:46 PM PDT 24
Peak memory 201224 kb
Host smart-05ede861-c313-47ec-a6bb-cc8cfe5f5311
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846288624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.846288624
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.4252047577
Short name T486
Test name
Test status
Simulation time 134989632868 ps
CPU time 683.91 seconds
Started Jul 23 07:03:30 PM PDT 24
Finished Jul 23 07:14:55 PM PDT 24
Peak memory 201676 kb
Host smart-8faed307-4302-4750-b109-f1e615931bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252047577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.4252047577
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1250112338
Short name T569
Test name
Test status
Simulation time 43942060731 ps
CPU time 91.95 seconds
Started Jul 23 07:03:29 PM PDT 24
Finished Jul 23 07:05:01 PM PDT 24
Peak memory 201072 kb
Host smart-bbf151a4-0716-43f6-8c62-de5481c4597f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250112338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1250112338
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3680684613
Short name T446
Test name
Test status
Simulation time 3177561997 ps
CPU time 7.52 seconds
Started Jul 23 07:03:32 PM PDT 24
Finished Jul 23 07:03:40 PM PDT 24
Peak memory 201032 kb
Host smart-3bcf2772-2983-4083-b89c-cb1b9f6d71e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680684613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3680684613
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1839307228
Short name T771
Test name
Test status
Simulation time 5994395293 ps
CPU time 1.92 seconds
Started Jul 23 07:03:23 PM PDT 24
Finished Jul 23 07:03:26 PM PDT 24
Peak memory 201048 kb
Host smart-e4f048c7-b293-4448-8275-8bdbb4648507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839307228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1839307228
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.20517661
Short name T340
Test name
Test status
Simulation time 334155858855 ps
CPU time 560.01 seconds
Started Jul 23 07:03:29 PM PDT 24
Finished Jul 23 07:12:49 PM PDT 24
Peak memory 201284 kb
Host smart-d6f40116-dcbd-4c96-899f-2410573830c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20517661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.20517661
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.960701862
Short name T788
Test name
Test status
Simulation time 33817810038 ps
CPU time 72.3 seconds
Started Jul 23 07:03:30 PM PDT 24
Finished Jul 23 07:04:43 PM PDT 24
Peak memory 209560 kb
Host smart-62c45341-1448-4825-8146-77dec40ad82d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960701862 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.960701862
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.737010616
Short name T135
Test name
Test status
Simulation time 534270307 ps
CPU time 0.75 seconds
Started Jul 23 07:03:45 PM PDT 24
Finished Jul 23 07:03:46 PM PDT 24
Peak memory 201044 kb
Host smart-48735ab7-93f6-4b0d-b7a9-eaac7bb201e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737010616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.737010616
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.4005497033
Short name T561
Test name
Test status
Simulation time 477673128486 ps
CPU time 121.75 seconds
Started Jul 23 07:03:37 PM PDT 24
Finished Jul 23 07:05:39 PM PDT 24
Peak memory 201248 kb
Host smart-561918dc-bfcf-438f-bc05-fd5c6de7bdb9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005497033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.4005497033
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.148921085
Short name T276
Test name
Test status
Simulation time 158332325418 ps
CPU time 337.8 seconds
Started Jul 23 07:03:35 PM PDT 24
Finished Jul 23 07:09:13 PM PDT 24
Peak memory 201312 kb
Host smart-0df6d868-a460-4a06-8496-5edf1fd36055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148921085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.148921085
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3532157749
Short name T250
Test name
Test status
Simulation time 326390647738 ps
CPU time 190.28 seconds
Started Jul 23 07:03:35 PM PDT 24
Finished Jul 23 07:06:46 PM PDT 24
Peak memory 201224 kb
Host smart-143e6683-a9ae-4748-b171-24a9961b2502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532157749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3532157749
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.4046841857
Short name T409
Test name
Test status
Simulation time 166438868063 ps
CPU time 93.17 seconds
Started Jul 23 07:03:35 PM PDT 24
Finished Jul 23 07:05:09 PM PDT 24
Peak memory 201296 kb
Host smart-75cee440-79ee-4a6f-9423-80e0eead0cd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046841857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.4046841857
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3760604918
Short name T332
Test name
Test status
Simulation time 168817441536 ps
CPU time 346.62 seconds
Started Jul 23 07:03:36 PM PDT 24
Finished Jul 23 07:09:24 PM PDT 24
Peak memory 201336 kb
Host smart-4fa7eb35-66b9-44d0-ac88-0ee50366a4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760604918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3760604918
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2098439040
Short name T523
Test name
Test status
Simulation time 490025275057 ps
CPU time 266.08 seconds
Started Jul 23 07:03:36 PM PDT 24
Finished Jul 23 07:08:03 PM PDT 24
Peak memory 201144 kb
Host smart-fb674695-266e-4764-8ab5-a433be0c3472
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098439040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2098439040
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2890552778
Short name T607
Test name
Test status
Simulation time 207045727126 ps
CPU time 251.22 seconds
Started Jul 23 07:03:35 PM PDT 24
Finished Jul 23 07:07:47 PM PDT 24
Peak memory 201112 kb
Host smart-9744e7e4-7ffd-43cb-be21-573dbd9b41f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890552778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2890552778
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1407788156
Short name T512
Test name
Test status
Simulation time 203462133263 ps
CPU time 237.47 seconds
Started Jul 23 07:03:34 PM PDT 24
Finished Jul 23 07:07:32 PM PDT 24
Peak memory 201240 kb
Host smart-bdc69360-4e5a-41df-b3dd-25c44fa834cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407788156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1407788156
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2154290363
Short name T539
Test name
Test status
Simulation time 71879989783 ps
CPU time 248.57 seconds
Started Jul 23 07:03:45 PM PDT 24
Finished Jul 23 07:07:55 PM PDT 24
Peak memory 201684 kb
Host smart-888f436f-8123-4f90-b983-7316a335674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154290363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2154290363
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3937701877
Short name T773
Test name
Test status
Simulation time 42884591430 ps
CPU time 18.57 seconds
Started Jul 23 07:03:36 PM PDT 24
Finished Jul 23 07:03:55 PM PDT 24
Peak memory 201060 kb
Host smart-7b2d5614-3512-4a8b-b53a-47fc0b4864ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937701877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3937701877
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.32533847
Short name T743
Test name
Test status
Simulation time 3835834996 ps
CPU time 9.5 seconds
Started Jul 23 07:03:36 PM PDT 24
Finished Jul 23 07:03:47 PM PDT 24
Peak memory 201052 kb
Host smart-e4183e32-a234-4d6b-bbd4-473acc88ae43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32533847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.32533847
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.4011823892
Short name T575
Test name
Test status
Simulation time 5958618853 ps
CPU time 2.67 seconds
Started Jul 23 07:03:30 PM PDT 24
Finished Jul 23 07:03:34 PM PDT 24
Peak memory 201072 kb
Host smart-a392c221-db7b-4b12-a459-485e13d5d4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011823892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4011823892
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1098455654
Short name T541
Test name
Test status
Simulation time 179725836186 ps
CPU time 411.87 seconds
Started Jul 23 07:03:45 PM PDT 24
Finished Jul 23 07:10:38 PM PDT 24
Peak memory 201156 kb
Host smart-88ff4b59-e632-422d-a3e5-45fb0b76264c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098455654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1098455654
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.886460106
Short name T21
Test name
Test status
Simulation time 116646180625 ps
CPU time 140.09 seconds
Started Jul 23 07:03:45 PM PDT 24
Finished Jul 23 07:06:06 PM PDT 24
Peak memory 210004 kb
Host smart-9da95412-1274-4071-a705-8f4f8dfc6450
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886460106 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.886460106
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2738447485
Short name T373
Test name
Test status
Simulation time 377686195 ps
CPU time 0.85 seconds
Started Jul 23 07:00:21 PM PDT 24
Finished Jul 23 07:00:24 PM PDT 24
Peak memory 200960 kb
Host smart-cf98683e-f176-4798-9a73-68590739fa45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738447485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2738447485
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3118708970
Short name T283
Test name
Test status
Simulation time 170603028037 ps
CPU time 203.25 seconds
Started Jul 23 07:00:04 PM PDT 24
Finished Jul 23 07:03:28 PM PDT 24
Peak memory 201208 kb
Host smart-42cf2217-4682-41b3-89d4-ea7e27ae3e1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118708970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3118708970
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2384298104
Short name T333
Test name
Test status
Simulation time 164424707416 ps
CPU time 97.71 seconds
Started Jul 23 07:00:07 PM PDT 24
Finished Jul 23 07:01:46 PM PDT 24
Peak memory 201296 kb
Host smart-36dfb570-bf52-47a3-8f54-94bda59720ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384298104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2384298104
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.309573791
Short name T481
Test name
Test status
Simulation time 487839465670 ps
CPU time 1203.43 seconds
Started Jul 23 07:00:11 PM PDT 24
Finished Jul 23 07:20:15 PM PDT 24
Peak memory 201200 kb
Host smart-b2d05507-79b6-4801-a310-d44f4d8d7509
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=309573791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.309573791
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.197746811
Short name T702
Test name
Test status
Simulation time 493466867968 ps
CPU time 265.68 seconds
Started Jul 23 07:00:10 PM PDT 24
Finished Jul 23 07:04:37 PM PDT 24
Peak memory 201232 kb
Host smart-beeabcac-b4a1-4c0c-86a3-30435ba7e3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197746811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.197746811
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2240015942
Short name T543
Test name
Test status
Simulation time 499489720514 ps
CPU time 604.83 seconds
Started Jul 23 07:00:08 PM PDT 24
Finished Jul 23 07:10:14 PM PDT 24
Peak memory 201256 kb
Host smart-fa1a87d5-7142-4da4-ae8a-f6c981ccc032
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240015942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2240015942
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.519386865
Short name T761
Test name
Test status
Simulation time 521122844716 ps
CPU time 1125.77 seconds
Started Jul 23 07:00:11 PM PDT 24
Finished Jul 23 07:18:57 PM PDT 24
Peak memory 201224 kb
Host smart-812248c2-4c0d-45cd-81e9-33abd4c79769
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519386865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.519386865
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2998097311
Short name T74
Test name
Test status
Simulation time 199854964123 ps
CPU time 477.53 seconds
Started Jul 23 07:00:14 PM PDT 24
Finished Jul 23 07:08:13 PM PDT 24
Peak memory 201280 kb
Host smart-e5e95b74-3fe9-45b8-9292-b03b67f2c6ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998097311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2998097311
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2424236024
Short name T602
Test name
Test status
Simulation time 65632292483 ps
CPU time 263.22 seconds
Started Jul 23 07:00:14 PM PDT 24
Finished Jul 23 07:04:38 PM PDT 24
Peak memory 201684 kb
Host smart-4bc780c7-e8cc-4005-9cfc-ea48bcf36313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424236024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2424236024
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2183710489
Short name T614
Test name
Test status
Simulation time 42559063824 ps
CPU time 44.48 seconds
Started Jul 23 07:00:08 PM PDT 24
Finished Jul 23 07:00:54 PM PDT 24
Peak memory 201080 kb
Host smart-7acbc173-471e-4992-90f7-98da189a482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183710489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2183710489
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.967407681
Short name T674
Test name
Test status
Simulation time 3936028628 ps
CPU time 10.28 seconds
Started Jul 23 07:00:07 PM PDT 24
Finished Jul 23 07:00:19 PM PDT 24
Peak memory 201012 kb
Host smart-d3994a17-94af-484c-b3fd-095405c43602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967407681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.967407681
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2855197733
Short name T675
Test name
Test status
Simulation time 6084225080 ps
CPU time 14.91 seconds
Started Jul 23 07:00:05 PM PDT 24
Finished Jul 23 07:00:21 PM PDT 24
Peak memory 201028 kb
Host smart-163ff4fe-9293-4aa2-b00f-a1c45007fdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855197733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2855197733
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2519177652
Short name T320
Test name
Test status
Simulation time 211516670309 ps
CPU time 463.15 seconds
Started Jul 23 07:00:20 PM PDT 24
Finished Jul 23 07:08:05 PM PDT 24
Peak memory 201216 kb
Host smart-5f4c896e-6b9e-49fc-80ce-11a5bae87242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519177652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2519177652
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1378966493
Short name T87
Test name
Test status
Simulation time 272359809412 ps
CPU time 302.79 seconds
Started Jul 23 07:00:23 PM PDT 24
Finished Jul 23 07:05:28 PM PDT 24
Peak memory 209896 kb
Host smart-5819f3e4-22f0-4b50-8b93-9e9372b601e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378966493 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1378966493
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.454810026
Short name T621
Test name
Test status
Simulation time 536086144 ps
CPU time 0.69 seconds
Started Jul 23 07:00:21 PM PDT 24
Finished Jul 23 07:00:24 PM PDT 24
Peak memory 201048 kb
Host smart-28f9290e-0e8a-4b23-af33-222ae86fedb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454810026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.454810026
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.20535783
Short name T329
Test name
Test status
Simulation time 346769378209 ps
CPU time 100.24 seconds
Started Jul 23 07:00:26 PM PDT 24
Finished Jul 23 07:02:07 PM PDT 24
Peak memory 201216 kb
Host smart-090f7483-1eb5-41d7-941e-f87fc7257f64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20535783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating
.20535783
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1469900748
Short name T313
Test name
Test status
Simulation time 362428343719 ps
CPU time 440.06 seconds
Started Jul 23 07:00:23 PM PDT 24
Finished Jul 23 07:07:44 PM PDT 24
Peak memory 201264 kb
Host smart-09ae7229-6f51-4bba-bf65-600a50a23b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469900748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1469900748
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.247965851
Short name T504
Test name
Test status
Simulation time 164528579315 ps
CPU time 88.24 seconds
Started Jul 23 07:00:26 PM PDT 24
Finished Jul 23 07:01:55 PM PDT 24
Peak memory 201252 kb
Host smart-a016fbc2-d355-46b9-bdb4-7ecd0b6692ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247965851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.247965851
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2308540961
Short name T613
Test name
Test status
Simulation time 334954584376 ps
CPU time 740.66 seconds
Started Jul 23 07:00:27 PM PDT 24
Finished Jul 23 07:12:48 PM PDT 24
Peak memory 201204 kb
Host smart-015bcbac-2e3d-403d-a18e-13cf3baa1d52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308540961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2308540961
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3482928195
Short name T191
Test name
Test status
Simulation time 483118970631 ps
CPU time 242.76 seconds
Started Jul 23 07:00:21 PM PDT 24
Finished Jul 23 07:04:26 PM PDT 24
Peak memory 201252 kb
Host smart-c8ba76d4-604b-4649-97a4-fe6aa4facf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482928195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3482928195
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2845418060
Short name T626
Test name
Test status
Simulation time 163049792937 ps
CPU time 107.31 seconds
Started Jul 23 07:00:21 PM PDT 24
Finished Jul 23 07:02:11 PM PDT 24
Peak memory 201228 kb
Host smart-a6fa5b5d-5be2-4ad9-8b84-1d103f8ae0b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845418060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2845418060
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.200257106
Short name T72
Test name
Test status
Simulation time 200040341656 ps
CPU time 117.25 seconds
Started Jul 23 07:00:20 PM PDT 24
Finished Jul 23 07:02:19 PM PDT 24
Peak memory 201348 kb
Host smart-13345780-c5fc-40c7-b6f9-7db315727ea4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200257106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.200257106
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3894317826
Short name T206
Test name
Test status
Simulation time 106572449773 ps
CPU time 534.48 seconds
Started Jul 23 07:00:27 PM PDT 24
Finished Jul 23 07:09:23 PM PDT 24
Peak memory 201740 kb
Host smart-814f22ac-cfa3-4a02-b5c4-2c621b3e3d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894317826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3894317826
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2036340236
Short name T758
Test name
Test status
Simulation time 33873715575 ps
CPU time 76.14 seconds
Started Jul 23 07:00:22 PM PDT 24
Finished Jul 23 07:01:40 PM PDT 24
Peak memory 201068 kb
Host smart-dddf3c31-4a87-4b79-89df-c29ac7ed235b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036340236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2036340236
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.157678044
Short name T555
Test name
Test status
Simulation time 4594985851 ps
CPU time 10.19 seconds
Started Jul 23 07:00:22 PM PDT 24
Finished Jul 23 07:00:34 PM PDT 24
Peak memory 201084 kb
Host smart-53bb4382-041a-4a4a-ae66-aa4c137aa088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157678044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.157678044
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1411970679
Short name T382
Test name
Test status
Simulation time 5724276562 ps
CPU time 3.23 seconds
Started Jul 23 07:00:22 PM PDT 24
Finished Jul 23 07:00:27 PM PDT 24
Peak memory 201108 kb
Host smart-c4eaa907-a303-47cb-a0c7-3d43a9a78add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411970679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1411970679
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.337445356
Short name T299
Test name
Test status
Simulation time 593860378906 ps
CPU time 907.37 seconds
Started Jul 23 07:00:27 PM PDT 24
Finished Jul 23 07:15:35 PM PDT 24
Peak memory 201656 kb
Host smart-e2d020fa-5ccc-465a-a7b2-b878e489504b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337445356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.337445356
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2082186322
Short name T717
Test name
Test status
Simulation time 386602463853 ps
CPU time 133.75 seconds
Started Jul 23 07:00:26 PM PDT 24
Finished Jul 23 07:02:40 PM PDT 24
Peak memory 209988 kb
Host smart-eb674f90-f400-4578-8eb9-7ae1fedcc552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082186322 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2082186322
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1238503418
Short name T415
Test name
Test status
Simulation time 424493506 ps
CPU time 1.09 seconds
Started Jul 23 07:00:34 PM PDT 24
Finished Jul 23 07:00:36 PM PDT 24
Peak memory 201056 kb
Host smart-8d2d8d0a-32d9-43da-8fb9-c98008cd8350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238503418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1238503418
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1234485354
Short name T223
Test name
Test status
Simulation time 161531188927 ps
CPU time 198.18 seconds
Started Jul 23 07:00:23 PM PDT 24
Finished Jul 23 07:03:43 PM PDT 24
Peak memory 201308 kb
Host smart-dc693aa0-4149-4ac7-9367-7ca1738a36d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234485354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1234485354
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.101542772
Short name T528
Test name
Test status
Simulation time 327000900365 ps
CPU time 181.87 seconds
Started Jul 23 07:00:22 PM PDT 24
Finished Jul 23 07:03:26 PM PDT 24
Peak memory 201144 kb
Host smart-8154df6c-5504-491e-8e1e-a741ff0128dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=101542772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.101542772
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3017821226
Short name T133
Test name
Test status
Simulation time 491139442904 ps
CPU time 570.09 seconds
Started Jul 23 07:00:22 PM PDT 24
Finished Jul 23 07:09:54 PM PDT 24
Peak memory 201208 kb
Host smart-9774f9e9-076a-4562-889e-c1b466606911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017821226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3017821226
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3971961836
Short name T376
Test name
Test status
Simulation time 486433736171 ps
CPU time 501.62 seconds
Started Jul 23 07:00:27 PM PDT 24
Finished Jul 23 07:08:49 PM PDT 24
Peak memory 201244 kb
Host smart-d39a005f-f183-4b20-a739-af94e406df81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971961836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3971961836
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.72765937
Short name T29
Test name
Test status
Simulation time 201088623113 ps
CPU time 429.55 seconds
Started Jul 23 07:00:34 PM PDT 24
Finished Jul 23 07:07:44 PM PDT 24
Peak memory 201008 kb
Host smart-a66166a7-8b11-4d67-8344-54d8e5facb28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72765937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wa
keup.72765937
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2327771989
Short name T385
Test name
Test status
Simulation time 599045012951 ps
CPU time 1382.32 seconds
Started Jul 23 07:00:36 PM PDT 24
Finished Jul 23 07:23:40 PM PDT 24
Peak memory 201212 kb
Host smart-ac00d4d5-cfda-46ab-b858-bbcf813d8b7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327771989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2327771989
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.247957662
Short name T221
Test name
Test status
Simulation time 94016291293 ps
CPU time 284.4 seconds
Started Jul 23 07:00:34 PM PDT 24
Finished Jul 23 07:05:19 PM PDT 24
Peak memory 201680 kb
Host smart-3355f683-2953-4979-ac90-de35d6977c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247957662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.247957662
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1082315426
Short name T395
Test name
Test status
Simulation time 34939058470 ps
CPU time 82.28 seconds
Started Jul 23 07:00:33 PM PDT 24
Finished Jul 23 07:01:56 PM PDT 24
Peak memory 201088 kb
Host smart-da26b769-bf02-4814-b169-e9701be43f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082315426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1082315426
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.333101984
Short name T570
Test name
Test status
Simulation time 5041288532 ps
CPU time 3.35 seconds
Started Jul 23 07:00:47 PM PDT 24
Finished Jul 23 07:00:51 PM PDT 24
Peak memory 201028 kb
Host smart-641338b4-50ce-4f70-a258-bc214a78438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333101984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.333101984
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4238985708
Short name T731
Test name
Test status
Simulation time 5743609907 ps
CPU time 13.37 seconds
Started Jul 23 07:00:19 PM PDT 24
Finished Jul 23 07:00:34 PM PDT 24
Peak memory 201088 kb
Host smart-8595d3b7-23e5-4558-a0ec-983f7998277a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238985708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4238985708
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1780382394
Short name T424
Test name
Test status
Simulation time 366711862 ps
CPU time 0.84 seconds
Started Jul 23 07:00:35 PM PDT 24
Finished Jul 23 07:00:38 PM PDT 24
Peak memory 201060 kb
Host smart-187c01b0-052e-4181-aa15-f129e1a5a96e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780382394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1780382394
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.115552444
Short name T275
Test name
Test status
Simulation time 508168418668 ps
CPU time 1124.26 seconds
Started Jul 23 07:00:34 PM PDT 24
Finished Jul 23 07:19:19 PM PDT 24
Peak memory 201244 kb
Host smart-57443a2d-c75f-42da-8348-49f119fad64e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115552444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.115552444
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3281308361
Short name T703
Test name
Test status
Simulation time 159478645434 ps
CPU time 86.39 seconds
Started Jul 23 07:00:34 PM PDT 24
Finished Jul 23 07:02:01 PM PDT 24
Peak memory 200876 kb
Host smart-ce6bc662-1270-4288-8c65-c656890705b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281308361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3281308361
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1112955253
Short name T194
Test name
Test status
Simulation time 329645630987 ps
CPU time 164.11 seconds
Started Jul 23 07:00:33 PM PDT 24
Finished Jul 23 07:03:18 PM PDT 24
Peak memory 201236 kb
Host smart-70a8fa3a-7a57-467e-90ef-51ef82b966c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112955253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1112955253
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1023998221
Short name T708
Test name
Test status
Simulation time 161858670016 ps
CPU time 87.98 seconds
Started Jul 23 07:00:35 PM PDT 24
Finished Jul 23 07:02:04 PM PDT 24
Peak memory 201148 kb
Host smart-7416a870-7170-4f22-86fb-38d7dabcfdd4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023998221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1023998221
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.824551339
Short name T551
Test name
Test status
Simulation time 165138755806 ps
CPU time 367.31 seconds
Started Jul 23 07:00:34 PM PDT 24
Finished Jul 23 07:06:42 PM PDT 24
Peak memory 201252 kb
Host smart-7dd743f4-781b-49a0-a69f-0df170f17d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824551339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.824551339
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1563335955
Short name T706
Test name
Test status
Simulation time 480683877102 ps
CPU time 938.68 seconds
Started Jul 23 07:00:33 PM PDT 24
Finished Jul 23 07:16:13 PM PDT 24
Peak memory 201204 kb
Host smart-e40f8360-714c-4cc5-8cc1-fbdf9f487417
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563335955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1563335955
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3821507799
Short name T488
Test name
Test status
Simulation time 197603179556 ps
CPU time 118.54 seconds
Started Jul 23 07:00:34 PM PDT 24
Finished Jul 23 07:02:34 PM PDT 24
Peak memory 201248 kb
Host smart-890a5dc3-796b-4cbb-a331-262a9cb36b13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821507799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3821507799
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3269272932
Short name T460
Test name
Test status
Simulation time 69157214239 ps
CPU time 227.34 seconds
Started Jul 23 07:00:34 PM PDT 24
Finished Jul 23 07:04:22 PM PDT 24
Peak memory 201664 kb
Host smart-53889fec-dac6-4fc3-bac8-3f132d68658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269272932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3269272932
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.4227039246
Short name T423
Test name
Test status
Simulation time 35900814513 ps
CPU time 46.34 seconds
Started Jul 23 07:00:35 PM PDT 24
Finished Jul 23 07:01:22 PM PDT 24
Peak memory 201264 kb
Host smart-0db8536e-3455-4a27-b9b1-2f2c6959b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227039246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.4227039246
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1056172633
Short name T489
Test name
Test status
Simulation time 5001449077 ps
CPU time 3.69 seconds
Started Jul 23 07:00:36 PM PDT 24
Finished Jul 23 07:00:41 PM PDT 24
Peak memory 201076 kb
Host smart-ec0430b5-334d-447d-b4bc-4ccca5e9ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056172633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1056172633
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3707630660
Short name T388
Test name
Test status
Simulation time 5806243247 ps
CPU time 2.62 seconds
Started Jul 23 07:00:35 PM PDT 24
Finished Jul 23 07:00:39 PM PDT 24
Peak memory 201052 kb
Host smart-ed84e016-8181-47e7-88ec-1f4f7c881979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707630660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3707630660
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1781056940
Short name T138
Test name
Test status
Simulation time 205852046531 ps
CPU time 124.32 seconds
Started Jul 23 07:00:35 PM PDT 24
Finished Jul 23 07:02:41 PM PDT 24
Peak memory 201192 kb
Host smart-28422143-a2c5-4a87-8632-3850d97d570e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781056940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1781056940
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1789298617
Short name T305
Test name
Test status
Simulation time 317688116445 ps
CPU time 171.45 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:03:32 PM PDT 24
Peak memory 209400 kb
Host smart-0e9adc1e-930b-42d4-ae16-f9394d0e912b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789298617 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1789298617
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.920176533
Short name T694
Test name
Test status
Simulation time 379427037 ps
CPU time 1.08 seconds
Started Jul 23 07:00:35 PM PDT 24
Finished Jul 23 07:00:38 PM PDT 24
Peak memory 201056 kb
Host smart-4288969c-4acf-4b3a-9b35-4f2f1767c9ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920176533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.920176533
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1184886987
Short name T342
Test name
Test status
Simulation time 510866183571 ps
CPU time 181.09 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:03:43 PM PDT 24
Peak memory 201256 kb
Host smart-87920cb4-cbd1-451b-909a-293b7c214198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184886987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1184886987
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1799067517
Short name T188
Test name
Test status
Simulation time 487963057765 ps
CPU time 92.1 seconds
Started Jul 23 07:00:36 PM PDT 24
Finished Jul 23 07:02:10 PM PDT 24
Peak memory 201152 kb
Host smart-5acee3c0-3584-404f-b033-a9b6d18af1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799067517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1799067517
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2537162353
Short name T436
Test name
Test status
Simulation time 166450540088 ps
CPU time 103.72 seconds
Started Jul 23 07:00:34 PM PDT 24
Finished Jul 23 07:02:19 PM PDT 24
Peak memory 201232 kb
Host smart-9fa20f87-e254-4329-8413-1e5b5b690d77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537162353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2537162353
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.4113892417
Short name T757
Test name
Test status
Simulation time 332946799233 ps
CPU time 161.56 seconds
Started Jul 23 07:00:37 PM PDT 24
Finished Jul 23 07:03:20 PM PDT 24
Peak memory 201164 kb
Host smart-2298f387-7caf-4e9e-8c85-91290ef8a5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113892417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4113892417
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.672054597
Short name T760
Test name
Test status
Simulation time 328609200223 ps
CPU time 763.77 seconds
Started Jul 23 07:00:34 PM PDT 24
Finished Jul 23 07:13:19 PM PDT 24
Peak memory 201184 kb
Host smart-7558fea6-4361-45e1-a83e-ed7b45d1abe0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=672054597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.672054597
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3179918524
Short name T685
Test name
Test status
Simulation time 201318922786 ps
CPU time 489.51 seconds
Started Jul 23 07:00:38 PM PDT 24
Finished Jul 23 07:08:49 PM PDT 24
Peak memory 201244 kb
Host smart-98403e1e-4ab2-4925-9786-7f131cac5161
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179918524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3179918524
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.466376913
Short name T733
Test name
Test status
Simulation time 602942973498 ps
CPU time 1439.7 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:24:41 PM PDT 24
Peak memory 201128 kb
Host smart-7c527384-1647-4fbe-acdb-310e41c19e34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466376913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.466376913
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.4247133228
Short name T683
Test name
Test status
Simulation time 76579331428 ps
CPU time 293.3 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:05:37 PM PDT 24
Peak memory 201664 kb
Host smart-510d69d6-446f-478d-a4d5-5624115f44d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247133228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4247133228
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.741674453
Short name T579
Test name
Test status
Simulation time 37903055816 ps
CPU time 89.82 seconds
Started Jul 23 07:00:38 PM PDT 24
Finished Jul 23 07:02:09 PM PDT 24
Peak memory 200772 kb
Host smart-e5813f1d-08e8-4973-bb34-bac3e3704368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741674453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.741674453
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1577883987
Short name T124
Test name
Test status
Simulation time 4720666980 ps
CPU time 9.74 seconds
Started Jul 23 07:00:40 PM PDT 24
Finished Jul 23 07:00:51 PM PDT 24
Peak memory 201104 kb
Host smart-a3317d31-4fb6-418f-809a-a80631979ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577883987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1577883987
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.452847798
Short name T677
Test name
Test status
Simulation time 5821228387 ps
CPU time 3.96 seconds
Started Jul 23 07:00:33 PM PDT 24
Finished Jul 23 07:00:38 PM PDT 24
Peak memory 201028 kb
Host smart-16f6b62c-b2fc-4600-89aa-bb5ae924240b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452847798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.452847798
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3049878924
Short name T218
Test name
Test status
Simulation time 467263760019 ps
CPU time 631.85 seconds
Started Jul 23 07:00:41 PM PDT 24
Finished Jul 23 07:11:15 PM PDT 24
Peak memory 201348 kb
Host smart-a1cd125c-6b2c-4c41-8bba-41ed9748b56f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049878924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3049878924
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3169114784
Short name T678
Test name
Test status
Simulation time 189271055155 ps
CPU time 163.37 seconds
Started Jul 23 07:00:38 PM PDT 24
Finished Jul 23 07:03:22 PM PDT 24
Peak memory 209688 kb
Host smart-8eba076a-3cff-4280-8a02-5bc9aae4b721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169114784 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3169114784
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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