Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7414	1			T1	44		T10	3		T42	10
testmodes[AdcCtrlTestmodeNormal]	6097	1			T1	42		T2	1		T3	3
testmodes[AdcCtrlTestmodeLowpower]	6086	1			T1	52		T6	15		T7	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3859	1			T1	16		T10	1		T42	6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1969	1			T1	14		T10	2		T42	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1476	1			T1	14		T44	9		T45	24
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1958	1			T1	10		T10	2		T42	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2234	1			T1	17		T3	2		T4	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1562	1			T1	14		T7	1		T39	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1486	1			T1	18		T44	11		T45	28
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1562	1			T1	11		T7	1		T40	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2794	1			T1	23		T6	14		T13	12