Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24376

1

T1

138

T2

10

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3388

1

T3

1

T4

1

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21397

1

T1

138

T4

1

T5

1

auto[1]

6367

1

T2

10

T3

3

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T210	1		-	-		-	-
values[0]	5	1			T32	1		T211	1		T107	3
values[1]	420	1			T151	1		T32	1		T16	6
values[2]	3071	1			T2	10		T9	4		T11	3
values[3]	685	1			T9	7		T13	26		T67	1
values[4]	640	1			T5	1		T7	1		T139	5
values[5]	786	1			T5	1		T43	15		T131	2
values[6]	675	1			T4	1		T7	23		T9	10
values[7]	900	1			T3	3		T43	16		T148	12
values[8]	717	1			T4	1		T151	1		T142	17
values[9]	1226	1			T5	1		T8	11		T12	7
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	604	1			T9	4		T151	1		T32	3
values[1]	3077	1			T2	10		T9	7		T11	3
values[2]	497	1			T7	1		T67	1		T14	26
values[3]	811	1			T5	1		T43	15		T40	14
values[4]	653	1			T4	1		T5	1		T131	2
values[5]	798	1			T3	2		T7	21		T9	10
values[6]	817	1			T3	1		T7	2		T148	12
values[7]	835	1			T4	1		T8	11		T43	16
values[8]	771	1			T5	1		T131	11		T40	6
values[9]	232	1			T12	7		T40	15		T16	21
minimum	18669	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	1		T151	1		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T32	2		T52	11		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T2	1		T11	1		T38	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	1		T13	15		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	6		T150	1		T143	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	1		T67	1		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T5	1		T34	2		T142	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T43	1		T40	5		T139	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	1		T131	1		T15	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	1		T27	1		T133	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T39	8		T16	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T3	1		T7	11		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	1		T7	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T27	1		T149	1		T142	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T43	1		T39	9		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T4	1		T8	11		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	1		T131	1		T40	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T139	1		T29	1		T212	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T12	1		T150	1		T84	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T40	3		T16	10		T213	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18509	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T164	12		T214	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	3		T52	10		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T52	9		T36	5		T215	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1120	1			T2	9		T11	2		T131	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	6		T13	11		T216	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	20		T150	8		T143	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T217	6		T37	1		T218	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T34	1		T219	2		T143	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	14		T40	9		T139	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T131	1		T35	7		T132	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T133	4		T78	10		T220	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	5		T16	10		T78	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	10		T9	9		T18	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	1		T148	11		T221	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T222	19		T190	9		T191	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T43	15		T39	7		T223	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	11		T133	12		T79	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T131	10		T140	7		T195	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T139	11		T220	13		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T12	6		T150	14		T225	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T40	12		T16	11		T213	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T164	3		T214	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T210	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T211	1		T107	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T32	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T151	1		T32	1		T16	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T16	3		T36	8		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1595	1			T2	1		T9	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T27	1		T32	1		T52	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	6		T149	1		T221	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	1		T13	15		T67	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T150	1		T219	1		T143	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	1		T7	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	1		T131	1		T15	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T43	1		T40	5		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	1		T7	1		T39	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	11		T9	1		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	2		T43	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T3	1		T27	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T151	1		T223	10		T78	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T4	1		T142	17		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T5	1		T12	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T8	11		T40	3		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T107	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	1		T145	4		T226	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T36	5		T215	10		T227	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T2	9		T9	3		T11	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T52	9		T228	19		T189	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	20		T221	3		T216	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	6		T13	11		T217	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T150	8		T219	2		T143	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T139	4		T25	12		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T131	1		T34	1		T35	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	14		T40	9		T139	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	1		T39	5		T132	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	10		T9	9		T78	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T43	15		T148	11		T16	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T222	9		T190	9		T191	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T223	9		T78	12		T86	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T133	12		T79	11		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	6		T131	10		T39	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T40	12		T139	11		T16	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	4		T151	1		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T32	2		T52	10		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T2	10		T11	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	7		T13	12		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	23		T150	9		T143	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T7	1		T67	1		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	1		T34	3		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T43	15		T40	10		T139	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	1		T131	2		T15	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	1		T27	1		T133	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	1		T39	6		T16	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T7	11		T9	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	1		T7	2		T148	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T27	1		T149	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T43	16		T39	8		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	1		T8	1		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	1		T131	11		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T139	12		T29	1		T212	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T12	7		T150	15		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T40	13		T16	12		T213	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18639	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T164	4		T214	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T52	2		T16	1		T84	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T52	10		T36	3		T229	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T38	27		T41	26		T28	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	14		T216	7		T146	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	3		T143	7		T230	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T217	7		T37	1		T21	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T142	4		T143	2		T94	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T40	4		T25	11		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T35	6		T132	12		T84	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T133	2		T231	15		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T39	7		T16	9		T221	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	10		T18	2		T147	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T221	2		T228	2		T232	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T142	16		T133	7		T222	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T39	8		T223	9		T86	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	10		T16	2		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T40	5		T233	12		T82	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T212	18		T224	9		T234	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T84	4		T188	12		T235	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T40	2		T16	9		T213	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T164	11		T214	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T210	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T211	1		T107	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T32	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T151	1		T32	1		T16	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T16	3		T36	10		T215	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1468	1			T2	10		T9	4		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T27	1		T32	1		T52	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	23		T149	1		T221	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	7		T13	12		T67	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T150	9		T219	3		T143	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	1		T7	1		T139	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	1		T131	2		T15	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T43	15		T40	10		T139	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	1		T7	2		T39	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	11		T9	10		T78	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	2		T43	16		T148	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	1		T27	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T151	1		T223	10		T78	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	1		T142	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T5	1		T12	7		T131	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T8	1		T40	13		T139	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T16	1		T236	11		T226	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T36	3		T164	11		T208	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T38	27		T41	26		T28	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T52	10		T229	2		T188	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	3		T221	3		T216	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	14		T217	7		T216	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T143	7		T230	12		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T25	11		T224	13		T237	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T142	4		T35	6		T143	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T40	4		T15	2		T133	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	7		T132	12		T84	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	10		T18	2		T163	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	9		T234	7		T97	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T222	10		T190	2		T147	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T223	9		T86	12		T221	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T142	16		T133	16		T79	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T39	8		T40	5		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T8	10		T40	2		T16	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21782

1

T1

138

T3

2

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

5982

1

T2

10

T3

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21429

1

T1

138

T3

2

T4

1

auto[1]

6335

1

T2

10

T3

1

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T191	9		-	-		-	-
values[0]	86	1			T7	21		T238	16		T239	5
values[1]	717	1			T25	24		T32	1		T52	13
values[2]	815	1			T3	1		T43	15		T39	13
values[3]	845	1			T4	2		T9	11		T151	1
values[4]	695	1			T43	16		T131	3		T40	14
values[5]	707	1			T13	26		T139	12		T140	4
values[6]	688	1			T3	2		T5	1		T7	3
values[7]	584	1			T9	10		T39	16		T40	6
values[8]	741	1			T5	2		T8	11		T67	1
values[9]	3239	1			T2	10		T11	3		T12	7
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1095	1			T7	21		T43	15		T25	24
values[1]	3209	1			T2	10		T3	1		T9	4
values[2]	769	1			T4	2		T9	7		T40	14
values[3]	584	1			T43	16		T131	3		T151	1
values[4]	716	1			T13	26		T131	11		T139	12
values[5]	667	1			T3	1		T7	2		T131	2
values[6]	679	1			T3	1		T5	2		T7	1
values[7]	636	1			T5	1		T8	11		T12	7
values[8]	540	1			T148	12		T139	5		T151	1
values[9]	231	1			T32	1		T15	2		T185	1
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T7	11		T52	3		T15	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T43	1		T25	12		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	1		T39	8		T40	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1666	1			T2	1		T9	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	2		T9	1		T14	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T40	5		T32	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T151	1		T223	10		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T43	1		T131	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T131	1		T139	1		T78	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T13	15		T233	13		T212	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T79	12		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	1		T131	1		T40	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	1		T39	9		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T5	1		T7	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	11		T67	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	1		T12	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T148	1		T140	1		T84	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T139	1		T151	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T15	2		T19	1		T240	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T32	1		T185	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	10		T52	10		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T43	14		T25	12		T241	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T39	5		T40	12		T35	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1136	1			T2	9		T9	3		T11	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	6		T14	20		T221	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T40	9		T52	9		T195	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T223	9		T78	12		T216	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	15		T131	2		T140	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T131	10		T139	11		T78	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	11		T143	12		T231	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T79	11		T220	13		T242	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T7	1		T131	1		T220	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T39	7		T139	10		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	9		T82	12		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T34	1		T16	11		T133	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	6		T36	5		T221	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T148	11		T140	4		T219	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	4		T144	3		T222	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T19	1		T240	7		T208	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T144	11		T218	9		T243	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T191	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T7	11		T244	17		T245	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T238	9		T239	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T52	3		T16	7		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T25	12		T32	1		T133	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	1		T39	8		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T43	1		T27	1		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	2		T9	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T9	1		T32	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	6		T149	1		T223	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	1		T131	1		T40	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T139	1		T79	12		T85	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T13	15		T140	1		T233	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	1		T131	1		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	1		T5	1		T7	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T39	9		T139	1		T224	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	1		T40	6		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	1		T8	11		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T82	14		T36	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T148	1		T140	1		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1657	1			T2	1		T11	1		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T191	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T7	10		T244	13		T245	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T238	7		T239	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T52	10		T16	12		T240	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T25	12		T241	10		T247	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T39	5		T40	12		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T43	14		T133	4		T78	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	6		T217	6		T224	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	3		T52	9		T195	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	20		T223	9		T78	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T43	15		T131	2		T40	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T139	11		T79	11		T86	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	11		T140	3		T16	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T131	10		T78	10		T220	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	1		T131	1		T220	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T39	7		T139	10		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	9		T18	5		T222	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T34	1		T133	12		T86	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T82	12		T36	5		T221	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T148	11		T140	4		T16	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1206	1			T2	9		T11	2		T12	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1