Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24295

1

T1

138

T2

10

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3469

1

T3

1

T4

2

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21754

1

T1

138

T3

1

T4

1

auto[1]

6010

1

T2

10

T3

2

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	285	1			T7	2		T13	26		T131	2
values[0]	11	1			T149	1		T232	8		T165	1
values[1]	488	1			T3	1		T8	11		T29	1
values[2]	580	1			T9	4		T15	2		T84	3
values[3]	876	1			T4	1		T7	21		T131	3
values[4]	703	1			T40	15		T148	12		T139	12
values[5]	887	1			T9	7		T43	15		T67	1
values[6]	665	1			T5	1		T43	16		T39	13
values[7]	696	1			T4	1		T5	1		T7	1
values[8]	557	1			T5	1		T9	10		T131	11
values[9]	3378	1			T2	10		T3	2		T11	3
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	473	1			T3	1		T8	11		T29	1
values[1]	689	1			T7	21		T9	4		T40	14
values[2]	842	1			T131	3		T39	16		T40	15
values[3]	679	1			T4	1		T67	1		T148	12
values[4]	786	1			T5	1		T9	7		T43	15
values[5]	685	1			T4	1		T43	16		T35	1
values[6]	3176	1			T2	10		T5	1		T7	1
values[7]	489	1			T3	1		T5	1		T12	7
values[8]	990	1			T3	1		T7	2		T13	26
values[9]	150	1			T142	5		T220	14		T237	9
minimum	18805	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T8	11		T223	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T29	1		T308	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T40	5		T32	1		T52	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	11		T9	1		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T40	3		T151	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T131	1		T39	9		T25	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T148	1		T139	2		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	1		T67	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	1		T43	1		T39	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	1		T15	3		T16	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T43	1		T35	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	1		T16	3		T85	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T2	1		T5	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	1		T9	1		T14	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T5	1		T131	1		T27	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	1		T12	1		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T3	1		T7	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	15		T131	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T142	5		T292	1		T236	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T220	1		T237	9		T234	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18532	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T132	13		T222	11		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T223	9		T222	10		T218	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T160	10		T288	8		T315	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T40	9		T52	9		T224	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	10		T9	3		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	12		T140	3		T143	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T131	2		T39	7		T25	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T148	11		T139	21		T52	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T234	6		T248	11		T255	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	6		T43	14		T39	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	1		T16	12		T133	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T43	15		T150	8		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T221	5		T220	9		T137	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1132	1			T2	9		T11	2		T269	35
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	9		T14	20		T230	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T131	10		T79	11		T219	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T12	6		T218	5		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T7	1		T35	7		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	11		T131	1		T139	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T293	11		T295	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T220	13		T234	9		T215	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	1		T67	1		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T132	7		T222	9		T232	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T7	1		T144	1		T236	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T13	15		T131	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T149	1		T210	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T232	5		T165	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	1		T8	11		T223	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	1		T132	13		T222	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T85	1		T274	1		T224	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	1		T15	2		T84	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T40	5		T151	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T4	1		T7	11		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T40	3		T148	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T36	1		T212	19		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	1		T43	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T67	1		T16	12		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T43	1		T39	8		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	1		T15	3		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	1		T40	6		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	1		T7	1		T14	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	1		T131	1		T27	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	1		T32	1		T230	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1710	1			T2	1		T3	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	1		T12	1		T16	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T7	1		T144	11		T316	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T13	11		T131	1		T139	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T232	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T223	9		T17	1		T218	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T132	7		T222	9		T160	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T224	8		T222	10		T268	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T9	3		T226	16		T154	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T40	9		T140	3		T52	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	10		T131	2		T39	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T40	12		T148	11		T139	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T234	6		T255	5		T179	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	6		T43	14		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T16	12		T133	12		T78	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T43	15		T39	5		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T15	1		T86	25		T220	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T150	8		T133	4		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	20		T221	5		T18	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T131	10		T217	6		T19	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T9	9		T230	12		T218	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T2	9		T11	2		T269	35
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	6		T16	21		T78	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	1		T8	1		T223	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T29	1		T308	1		T160	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T40	10		T32	1		T52	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	11		T9	4		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T40	13		T151	1		T140	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T131	3		T39	8		T25	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T148	12		T139	23		T52	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	1		T67	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	7		T43	15		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T5	1		T15	2		T16	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T43	16		T35	1		T150	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	1		T16	3		T85	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1483	1			T2	10		T5	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	1		T9	10		T14	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	1		T131	11		T27	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	1		T12	7		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T3	1		T7	2		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T13	12		T131	2		T139	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T142	1		T292	1		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T220	14		T237	1		T234	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18664	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T132	8		T222	10		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T8	10		T223	9		T252	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T162	10		T288	6		T315	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	4		T52	10		T233	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	10		T84	2		T134	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T40	2		T143	7		T221	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T39	8		T25	11		T36	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T52	2		T82	13		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T234	7		T248	9		T255	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T39	7		T221	2		T168	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T15	2		T16	10		T133	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T143	2		T260	9		T208	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T221	6		T275	13		T267	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T38	27		T40	5		T41	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	3		T230	12		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T79	11		T262	12		T97	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T247	10		T147	16		T163	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T35	6		T84	4		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	14		T16	11		T216	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T142	4		T236	10		T298	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T237	8		T234	13		T235	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T84	4		T17	1		T263	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T132	12		T222	10		T232	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T7	2		T144	12		T236	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T13	12		T131	2		T139	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T149	1		T210	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T232	4		T165	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T3	1		T8	1		T223	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T29	1		T132	8		T222	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T85	1		T274	1		T224	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T9	4		T15	2		T84	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T40	10		T151	1		T140	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T4	1		T7	11		T131	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T40	13		T148	12		T139	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T36	1		T212	1		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	7		T43	15		T139	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T67	1		T16	14		T133	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T43	16		T39	6		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	1		T15	2		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	1		T40	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	1		T7	1		T14	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T131	11		T27	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	10		T32	1		T230	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1575	1			T2	10		T3	1		T11	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	1		T12	7		T16	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T236	10		T287	10		T316	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T13	14		T216	7		T237	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T232	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T8	10		T223	9		T84	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T132	12		T222	10		T288	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T224	1		T222	3		T228	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T84	2		T134	12		T226	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T40	4		T52	10		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	10		T39	8		T25	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T40	2		T82	13		T237	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T212	18		T234	7		T255	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T52	2		T221	2		T168	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T16	10		T133	9		T224	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T39	7		T143	2		T260	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	2		T86	23		T275	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T40	5		T142	16		T133	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T14	3		T221	6		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T133	7		T217	7		T262	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T230	12		T287	1		T147	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T38	27		T41	26		T28	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T16	11		T234	13		T247	22

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14