Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24463

1

T1

138

T2

10

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3301

1

T3

1

T4

1

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21525

1

T1

138

T3

1

T5

1

auto[1]

6239

1

T2

10

T3

2

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	330	1			T5	1		T40	15		T25	24
values[0]	24	1			T5	1		T150	10		T286	12
values[1]	596	1			T5	1		T7	2		T43	15
values[2]	726	1			T3	1		T7	21		T131	14
values[3]	564	1			T7	1		T39	13		T139	12
values[4]	3153	1			T2	10		T4	2		T11	3
values[5]	663	1			T40	6		T140	5		T149	1
values[6]	650	1			T3	2		T9	10		T131	2
values[7]	774	1			T9	4		T233	13		T150	9
values[8]	588	1			T9	7		T43	16		T151	1
values[9]	1058	1			T8	11		T13	26		T39	16
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	544	1			T43	15		T67	1		T131	3
values[1]	661	1			T3	1		T7	21		T131	11
values[2]	689	1			T4	1		T7	1		T39	13
values[3]	3048	1			T2	10		T4	1		T11	3
values[4]	645	1			T40	6		T14	26		T32	1
values[5]	642	1			T3	2		T9	10		T131	2
values[6]	836	1			T9	4		T150	9		T78	4
values[7]	563	1			T9	7		T43	16		T39	16
values[8]	1072	1			T8	11		T13	26		T148	12
values[9]	158	1			T5	1		T40	15		T25	24
minimum	18906	1			T1	138		T5	2		T6	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T43	1		T67	1		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T131	1		T142	5		T36	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	1		T151	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	11		T131	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	1		T39	8		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	1		T139	1		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T2	1		T4	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T34	2		T16	1		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T40	6		T32	1		T222	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	6		T149	1		T16	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T52	11		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	1		T9	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T150	1		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T144	1		T283	1		T216	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T39	9		T151	1		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	1		T43	1		T86	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T8	11		T13	15		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T149	1		T15	2		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T5	1		T40	3		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T25	12		T246	1		T262	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18607	1			T1	138		T5	1		T6	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T5	1		T7	1		T40	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T43	14		T16	11		T19	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T131	2		T36	5		T248	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T234	7		T145	14		T278	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	10		T131	10		T78	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T39	5		T140	3		T52	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T139	11		T218	5		T240	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1099	1			T2	9		T11	2		T12	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T34	1		T146	12		T189	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T222	10		T137	2		T56	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	20		T16	10		T133	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T52	9		T15	1		T78	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	9		T131	1		T132	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	3		T150	8		T78	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T144	11		T216	6		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	7		T195	4		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	6		T43	15		T86	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	11		T148	11		T139	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T150	14		T137	25		T177	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T40	12		T147	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T25	12		T262	6		T317	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	1		T67	1		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T7	1		T40	9		T150	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	1		T40	3		T143	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T25	12		T36	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T5	1		T318	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T150	1		T286	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T43	1		T67	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	1		T7	1		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T151	1		T234	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	11		T131	2		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T39	8		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T139	1		T149	1		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1636	1			T2	1		T4	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T4	1		T16	1		T185	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T40	6		T140	1		T142	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T149	1		T34	2		T16	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	1		T32	1		T52	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	1		T9	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	1		T233	13		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T221	4		T144	1		T283	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T151	1		T195	1		T230	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	1		T43	1		T86	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T8	11		T13	15		T39	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T149	1		T15	2		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T40	12		T143	4		T147	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T25	12		T137	11		T262	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T150	9		T286	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T43	14		T16	11		T82	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T7	1		T40	9		T36	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T234	7		T145	14		T191	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	10		T131	12		T78	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T39	5		T140	3		T52	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T139	11		T218	5		T240	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1100	1			T2	9		T11	2		T12	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T226	16		T21	7		T189	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T140	4		T143	12		T222	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T34	1		T16	10		T133	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T52	9		T15	1		T78	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T9	9		T131	1		T14	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	3		T150	8		T78	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T221	3		T144	11		T216	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T195	4		T230	12		T19	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	6		T43	15		T86	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T13	11		T39	7		T148	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T150	14		T137	14		T247	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T43	15		T67	1		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T131	3		T142	1		T36	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	1		T151	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	11		T131	11		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	1		T39	6		T140	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	1		T139	12		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T2	10		T4	1		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	3		T16	1		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T40	1		T32	1		T222	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	23		T149	1		T16	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T52	10		T15	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T9	10		T131	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T9	4		T150	9		T78	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T144	12		T283	1		T216	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	8		T151	1		T195	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	7		T43	16		T86	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T8	1		T13	12		T148	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T149	1		T15	2		T150	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T5	1		T40	13		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T25	13		T246	1		T262	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18707	1			T1	138		T5	1		T6	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T5	1		T7	2		T40	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	2		T237	7		T255	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T142	4		T36	3		T248	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T278	5		T161	12		T155	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	10		T275	13		T168	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	7		T52	2		T35	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T240	6		T226	13		T21	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T38	27		T41	26		T28	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T188	16		T146	13		T189	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T40	5		T222	3		T236	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	3		T16	9		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T52	10		T15	2		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T132	12		T84	4		T221	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T230	12		T303	19		T197	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T216	10		T231	15		T260	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T39	8		T224	12		T188	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T86	23		T221	8		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T8	10		T13	14		T84	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T177	1		T228	2		T190	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T40	2		T147	16		T319	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T25	11		T262	12		T235	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T82	13		T212	18		T224	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T40	4		T84	2		T222	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T5	1		T40	13		T143	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T25	13		T36	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T5	1		T318	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T150	10		T286	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T43	15		T67	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	1		T7	2		T40	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	1		T151	1		T234	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	11		T131	14		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T39	6		T140	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T139	12		T149	1		T218	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1455	1			T2	10		T4	1		T11	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	1		T16	1		T185	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T40	1		T140	5		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T149	1		T34	3		T16	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	1		T32	1		T52	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	1		T9	10		T131	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	4		T233	1		T150	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T221	4		T144	12		T283	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T151	1		T195	5		T230	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	7		T43	16		T86	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T8	1		T13	12		T39	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T149	1		T15	2		T150	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T40	2		T143	7		T147	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T25	11		T262	12		T235	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T286	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	2		T82	13		T212	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T40	4		T84	2		T36	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T161	12		T155	7		T280	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T7	10		T142	4		T267	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T39	7		T52	2		T35	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T240	6		T275	13		T168	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T38	27		T41	26		T28	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T226	13		T21	6		T189	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T40	5		T142	16		T143	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T16	9		T133	11		T79	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T52	10		T15	2		T133	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	3		T132	12		T84	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T233	12		T303	19		T197	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T221	3		T216	7		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T230	12		T188	8		T287	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T86	23		T221	8		T216	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T8	10		T13	14		T39	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T247	12		T177	1		T228	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14