Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24364

1

T1

138

T2

10

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3400

1

T3

1

T4

1

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21422

1

T1

138

T4

1

T5

1

auto[1]

6342

1

T2

10

T3

3

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	178	1			T12	7		T150	15		T220	14
values[0]	16	1			T164	15		T211	1		-	-
values[1]	444	1			T151	1		T32	3		T52	13
values[2]	3070	1			T2	10		T9	4		T11	3
values[3]	588	1			T9	7		T67	1		T14	26
values[4]	677	1			T5	1		T7	1		T25	24
values[5]	790	1			T4	1		T5	1		T43	15
values[6]	683	1			T7	21		T9	10		T39	13
values[7]	887	1			T3	3		T7	2		T43	16
values[8]	772	1			T4	1		T151	1		T142	17
values[9]	1021	1			T5	1		T8	11		T131	11
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	524	1			T9	4		T151	1		T32	2
values[1]	3075	1			T2	10		T9	7		T11	3
values[2]	551	1			T67	1		T14	26		T150	9
values[3]	712	1			T5	1		T7	1		T43	15
values[4]	750	1			T4	1		T5	1		T131	2
values[5]	782	1			T3	1		T7	21		T9	10
values[6]	823	1			T3	2		T7	2		T43	16
values[7]	779	1			T4	1		T8	11		T39	16
values[8]	894	1			T5	1		T12	7		T131	11
values[9]	129	1			T40	15		T150	15		T84	5
minimum	18745	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	1		T151	1		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T32	1		T52	11		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T2	1		T11	1		T38	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	1		T13	15		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	6		T150	1		T143	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T67	1		T85	1		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T34	2		T142	5		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	1		T7	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	1		T5	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T27	1		T133	3		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T39	8		T16	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T7	11		T9	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	1		T7	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	1		T27	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T39	9		T151	1		T223	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T4	1		T8	11		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T5	1		T12	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T139	1		T29	1		T16	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T150	1		T84	5		T283	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T40	3		T213	4		T320	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18523	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T32	1		T36	8		T164	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	3		T52	10		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T52	9		T215	10		T227	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T2	9		T11	2		T131	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	6		T13	11		T216	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	20		T150	8		T143	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T217	6		T230	12		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T34	1		T219	2		T268	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T43	14		T40	9		T139	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T131	1		T35	7		T132	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T133	4		T78	10		T220	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T39	5		T16	10		T78	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	10		T9	9		T18	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	1		T43	15		T148	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T222	19		T190	9		T191	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	7		T223	9		T78	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T16	11		T133	12		T79	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	6		T131	10		T140	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T139	11		T16	11		T220	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T150	14		T321	7		T107	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T40	12		T213	2		T320	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T67	1		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T36	5		T164	3		T208	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T12	1		T150	1		T283	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T220	1		T247	11		T177	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T211	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T164	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T151	1		T32	1		T52	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T32	2		T16	3		T36	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T2	1		T9	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	15		T27	1		T52	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	6		T149	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T9	1		T67	1		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T142	5		T219	1		T143	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	1		T7	1		T25	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	1		T5	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T43	1		T40	5		T139	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	8		T132	13		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	11		T9	1		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	2		T7	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	1		T27	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T151	1		T223	10		T78	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T4	1		T142	17		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T5	1		T131	1		T39	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T8	11		T40	3		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T12	6		T150	14		T242	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T220	13		T247	10		T177	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T164	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T52	10		T16	1		T145	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T36	5		T215	10		T227	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1114	1			T2	9		T9	3		T11	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	11		T52	9		T216	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	20		T150	8		T221	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T9	6		T37	1		T218	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T219	2		T143	4		T268	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T25	12		T15	1		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T131	1		T34	1		T35	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	14		T40	9		T139	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	5		T132	7		T78	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	10		T9	9		T78	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	1		T43	15		T148	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T222	9		T190	9		T191	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T223	9		T78	12		T86	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T133	12		T79	11		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T131	10		T39	7		T140	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T40	12		T139	11		T16	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	4		T151	1		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T32	1		T52	10		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T2	10		T11	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	7		T13	12		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	23		T150	9		T143	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T67	1		T85	1		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T34	3		T142	1		T219	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	1		T7	1		T43	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	1		T5	1		T131	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T27	1		T133	5		T78	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T39	6		T16	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	11		T9	10		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	1		T7	2		T43	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	1		T27	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T39	8		T151	1		T223	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	1		T8	1		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	1		T12	7		T131	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T139	12		T29	1		T16	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T150	15		T84	1		T283	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T40	13		T213	5		T320	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18665	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T32	1		T36	10		T164	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T52	2		T16	1		T84	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T52	10		T229	2		T188	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T38	27		T41	26		T28	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	14		T216	7		T146	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T14	3		T143	7		T253	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T217	7		T230	12		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T142	4		T94	10		T226	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T40	4		T25	11		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T35	6		T132	12		T84	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T133	2		T231	15		T248	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	7		T16	9		T221	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	10		T18	2		T147	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T228	2		T178	3		T249	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T142	16		T133	7		T222	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	8		T223	9		T86	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	10		T16	2		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T40	5		T233	12		T82	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	9		T212	18		T224	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T84	4		T321	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T40	2		T213	1		T320	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T255	2		T259	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T36	3		T164	11		T208	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T12	7		T150	15		T283	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T220	14		T247	11		T177	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T211	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T164	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T151	1		T32	1		T52	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T32	2		T16	3		T36	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T2	10		T9	4		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	12		T27	1		T52	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	23		T149	1		T150	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	7		T67	1		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T142	1		T219	3		T143	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	1		T7	1		T25	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	1		T5	1		T131	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T43	15		T40	10		T139	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T39	6		T132	8		T78	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	11		T9	10		T78	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T3	2		T7	2		T43	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	1		T27	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T151	1		T223	10		T78	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	1		T142	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T5	1		T131	11		T39	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T8	1		T40	13		T139	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T237	8		T266	2		T281	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T247	10		T177	1		T179	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T164	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T52	2		T16	1		T236	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T36	3		T189	1		T147	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T38	27		T41	26		T28	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	14		T52	10		T216	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T221	3		T216	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T37	1		T146	13		T307	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T142	4		T143	7		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T25	11		T15	2		T217	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T35	6		T143	2		T275	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T40	4		T133	2		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T39	7		T132	12		T84	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	10		T18	2		T162	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	9		T234	7		T97	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T222	10		T190	2		T147	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T223	9		T86	12		T221	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T142	16		T133	16		T79	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T39	8		T40	5		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	10		T40	2		T16	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14