Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24047

1

T1

138

T2

10

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3717

1

T3

3

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21609

1

T1

138

T3

2

T4

2

auto[1]

6155

1

T2

10

T3

1

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	296	1			T7	21		T9	7		T12	7
values[0]	30	1			T165	1		T265	11		T273	18
values[1]	655	1			T8	11		T67	1		T39	13
values[2]	639	1			T5	1		T7	1		T9	4
values[3]	597	1			T3	1		T9	10		T139	11
values[4]	704	1			T7	2		T39	16		T148	12
values[5]	3049	1			T2	10		T3	1		T11	3
values[6]	620	1			T151	2		T32	1		T16	4
values[7]	776	1			T3	1		T4	1		T40	14
values[8]	474	1			T5	1		T43	16		T52	13
values[9]	1286	1			T4	1		T5	1		T43	15
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	638	1			T5	1		T8	11		T131	11
values[1]	560	1			T3	1		T7	1		T9	4
values[2]	699	1			T9	10		T148	12		T139	11
values[3]	3067	1			T2	10		T7	2		T11	3
values[4]	645	1			T3	1		T13	26		T40	6
values[5]	648	1			T3	1		T151	2		T32	2
values[6]	684	1			T4	1		T5	1		T40	14
values[7]	634	1			T43	31		T27	1		T149	1
values[8]	1206	1			T4	1		T5	1		T7	21
values[9]	132	1			T224	20		T197	8		T267	25
minimum	18851	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T131	1		T32	1		T35	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	1		T8	11		T39	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	1		T15	3		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	1		T7	1		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T139	1		T52	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T148	1		T27	1		T84	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T2	1		T11	1		T38	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	1		T39	9		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T149	1		T85	1		T36	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	1		T13	15		T40	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T151	1		T32	2		T212	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	1		T151	1		T16	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T140	1		T16	2		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	1		T5	1		T40	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T43	1		T52	3		T233	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T43	1		T27	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T4	1		T5	1		T7	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T12	1		T131	1		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T267	13		T178	8		T271	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T224	10		T197	6		T178	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18550	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T40	3		T139	1		T27	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T131	10		T35	7		T224	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T39	5		T25	12		T150	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T9	3		T15	1		T133	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T82	12		T86	13		T268	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T9	9		T139	10		T52	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T148	11		T86	12		T143	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1114	1			T2	9		T11	2		T269	35
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	1		T39	7		T139	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T36	5		T221	3		T144	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	11		T234	7		T177	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T218	5		T262	6		T270	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T133	12		T231	12		T191	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T140	4		T16	1		T150	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	9		T16	11		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T43	14		T52	10		T78	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T43	15		T220	13		T19	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T7	10		T9	6		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	6		T131	1		T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T267	12		T271	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T224	10		T197	2		T322	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	1		T67	1		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T40	12		T139	11		T240	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	11		T9	1		T140	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T12	1		T15	2		T223	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T273	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T165	1		T265	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T67	1		T35	9		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	11		T39	8		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T131	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T7	1		T25	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	1		T139	1		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	1		T27	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	6		T52	11		T16	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	1		T39	9		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T2	1		T11	1		T38	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	1		T13	15		T40	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T151	1		T32	1		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T151	1		T16	1		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T140	1		T32	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	1		T4	1		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T52	3		T78	1		T20	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T43	1		T142	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T4	1		T5	1		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T131	1		T27	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T7	10		T9	6		T140	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T12	6		T223	9		T224	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T273	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T35	7		T241	10		T218	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T39	5		T40	12		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	3		T131	10		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T25	12		T82	12		T56	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T9	9		T139	10		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T86	13		T143	12		T221	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	20		T52	9		T16	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	1		T39	7		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1104	1			T2	9		T11	2		T269	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	11		T139	4		T234	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	1		T145	4		T94	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T133	12		T231	12		T177	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T140	4		T150	8		T234	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T40	9		T16	11		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T52	10		T78	12		T20	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T43	15		T19	2		T222	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T43	14		T131	2		T195	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T131	1		T220	22		T137	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T131	11		T32	1		T35	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	1		T8	1		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	4		T15	2		T133	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T7	1		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	10		T139	11		T52	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T148	12		T27	1		T84	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T2	10		T11	3		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	2		T39	8		T139	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T149	1		T85	1		T36	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	1		T13	12		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T151	1		T32	2		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	1		T151	1		T16	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T140	5		T16	2		T150	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T4	1		T5	1		T40	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	15		T52	11		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T43	16		T27	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T4	1		T5	1		T7	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	7		T131	2		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T267	13		T178	1		T271	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T224	11		T197	7		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18690	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T40	13		T139	12		T27	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T35	6		T224	1		T226	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	10		T39	7		T25	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	2		T133	2		T84	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T82	13		T86	12		T236	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T52	10		T79	11		T255	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T84	4		T86	11		T143	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T38	27		T41	26		T14	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	8		T16	9		T132	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T36	3		T221	3		T94	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	14		T40	5		T188	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T212	18		T262	12		T250	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T133	9		T231	15		T288	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T16	1		T252	2		T234	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T40	4		T142	16		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T52	2		T233	12		T251	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T133	7		T188	28		T146	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T7	10		T142	4		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T223	9		T228	19		T279	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T267	12		T178	7		T271	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T224	9		T197	1		T178	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T248	9		T323	13		T299	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T40	2		T240	2		T186	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T7	11		T9	7		T140	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T12	7		T15	2		T223	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T273	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T165	1		T265	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T67	1		T35	10		T241	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T8	1		T39	6		T40	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	4		T131	11		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T7	1		T25	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	10		T139	11		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T27	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	23		T52	10		T16	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	2		T39	8		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T2	10		T11	3		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	1		T13	12		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T151	1		T32	1		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T151	1		T16	1		T133	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T140	5		T32	1		T150	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	1		T4	1		T40	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T52	11		T78	13		T20	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	1		T43	16		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T4	1		T5	1		T43	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T131	2		T27	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T7	10		T234	7		T168	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T223	9		T224	9		T178	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T273	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T265	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T35	6		T248	9		T226	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	10		T39	7		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	2		T133	2		T84	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	11		T82	13		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T79	11		T84	4		T255	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T84	4		T86	12		T143	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T14	3		T52	10		T16	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T39	8		T16	9		T132	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T38	27		T41	26		T28	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	14		T40	5		T188	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T16	1		T212	18		T94	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T133	9		T231	15		T177	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T252	2		T234	13		T247	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	4		T16	2		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T52	2		T251	7		T186	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T142	16		T133	7		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T142	4		T233	12		T143	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T188	28		T146	13		T228	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14