Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24223

1

T1

138

T2

10

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3541

1

T3

3

T5

1

T7

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21217

1

T1

135

T3

1

T4

1

auto[1]

6547

1

T1

3

T2

10

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	543	1			T1	3		T44	1		T45	2
values[0]	88	1			T3	1		T139	11		T29	1
values[1]	834	1			T5	1		T8	11		T39	16
values[2]	3027	1			T2	10		T3	1		T7	21
values[3]	431	1			T5	1		T7	3		T43	16
values[4]	848	1			T9	7		T32	1		T149	1
values[5]	817	1			T4	1		T131	11		T40	15
values[6]	488	1			T5	1		T131	2		T140	4
values[7]	783	1			T4	1		T39	13		T14	26
values[8]	582	1			T131	3		T148	12		T151	1
values[9]	1197	1			T3	1		T9	10		T13	26
minimum	18126	1			T1	135		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1019	1			T3	1		T5	1		T7	21
values[1]	2940	1			T2	10		T7	2		T11	3
values[2]	544	1			T3	1		T5	1		T7	1
values[3]	785	1			T9	7		T32	1		T52	20
values[4]	804	1			T4	1		T131	11		T40	15
values[5]	592	1			T4	1		T5	1		T39	13
values[6]	715	1			T131	2		T14	26		T27	1
values[7]	709	1			T131	3		T148	12		T151	1
values[8]	793	1			T9	10		T43	15		T139	5
values[9]	156	1			T3	1		T13	26		T40	6
minimum	18707	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T39	9		T36	1		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	1		T5	1		T7	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T2	1		T7	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T43	1		T40	5		T36	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T67	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	1		T7	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T9	1		T35	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T32	1		T52	11		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	1		T15	2		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T131	1		T40	3		T52	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	1		T5	1		T39	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T133	8		T78	1		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T27	1		T34	2		T16	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T131	1		T14	6		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T148	1		T78	1		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T131	1		T151	1		T132	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	1		T43	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T25	12		T149	1		T142	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T13	15		T153	1		T324	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T3	1		T40	6		T86	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T188	13		T325	1		T309	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T39	7		T220	13		T224	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	10		T9	3		T139	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T2	9		T7	1		T11	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T43	15		T40	9		T36	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T133	4		T17	1		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T139	11		T16	11		T78	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	6		T150	9		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T52	9		T218	2		T93	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T247	10		T93	12		T147	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T131	10		T40	12		T52	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	5		T140	3		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T78	3		T242	12		T56	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	1		T16	11		T219	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T131	1		T14	20		T16	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T148	11		T78	10		T240	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T131	2		T132	7		T150	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	9		T43	14		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T25	12		T35	7		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T13	11		T324	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T86	13		T221	8		T164	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	1		T67	1		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T326	10		T310	10		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	523	1			T1	3		T44	1		T45	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T188	9		T23	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T327	12		T328	1		T329	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T3	1		T139	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T39	9		T224	10		T216	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	1		T8	11		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T2	1		T11	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	1		T7	11		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	1		T7	1		T67	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T7	1		T43	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	1		T35	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T32	1		T149	1		T52	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	1		T15	2		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T131	1		T40	3		T142	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T140	1		T16	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T131	1		T16	10		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T4	1		T39	8		T27	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	6		T133	8		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T148	1		T34	2		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T131	1		T151	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T9	1		T13	15		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	454	1			T3	1		T40	6		T25	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17996	1			T1	135		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T19	2		T330	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T23	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T327	10		T329	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T139	10		T310	10		T311	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T39	7		T224	10		T216	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T140	4		T15	1		T150	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T2	9		T11	2		T12	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	10		T9	3		T40	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T7	1		T133	4		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T43	15		T139	11		T78	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	6		T150	9		T133	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T52	19		T16	11		T303	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T247	10		T93	12		T250	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T131	10		T40	12		T230	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T140	3		T16	1		T247	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T131	1		T16	10		T78	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T39	5		T219	2		T143	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	20		T242	3		T262	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T148	11		T34	1		T16	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T131	2		T132	7		T221	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	9		T13	11		T43	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T25	12		T35	7		T150	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T39	8		T36	1		T220	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	1		T5	1		T7	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T2	10		T7	2		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T43	16		T40	10		T36	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	1		T67	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T7	1		T139	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T9	7		T35	1		T150	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T32	1		T52	10		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	1		T15	2		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T131	11		T40	13		T52	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	1		T5	1		T39	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T133	1		T78	4		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T27	1		T34	3		T16	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T131	2		T14	23		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T148	12		T78	11		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T131	3		T151	1		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	10		T43	15		T139	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T25	13		T149	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T13	12		T153	1		T324	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T3	1		T40	1		T86	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18649	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T188	1		T325	1		T309	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T39	8		T224	9		T216	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	10		T8	10		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T38	27		T41	26		T28	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T40	4		T36	3		T251	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T133	2		T17	1		T222	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T16	9		T234	13		T222	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T133	9		T84	6		T212	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T52	10		T303	19		T287	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T247	12		T147	16		T232	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T40	2		T52	2		T142	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T39	7		T16	1		T134	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T133	7		T228	19		T161	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T16	2		T217	7		T234	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	3		T16	9		T262	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T240	4		T21	6		T177	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T132	12		T221	6		T224	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T223	9		T216	7		T177	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T25	11		T142	16		T35	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T13	14		T156	5		T331	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T40	5		T86	12		T221	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T188	12		T326	10		T310	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	523	1			T1	3		T44	1		T45	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T188	1		T23	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T327	11		T328	1		T329	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T3	1		T139	11		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T39	8		T224	11		T216	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	1		T8	1		T140	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T2	10		T11	3		T12	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	1		T7	11		T9	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	1		T7	2		T67	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	1		T43	16		T139	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	7		T35	1		T150	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T32	1		T149	1		T52	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	1		T15	2		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T131	11		T40	13		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T140	4		T16	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T131	2		T16	11		T78	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	1		T39	6		T27	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	23		T133	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T148	12		T34	3		T16	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T131	3		T151	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T9	10		T13	12		T43	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T3	1		T40	1		T25	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18126	1			T1	135		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T330	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T188	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T327	11		T329	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T310	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T39	8		T224	9		T216	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	10		T15	2		T79	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T38	27		T41	26		T28	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	10		T40	4		T251	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T133	2		T84	4		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T234	13		T222	3		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T133	9		T84	6		T212	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T52	12		T16	9		T303	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T247	12		T232	4		T163	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T40	2		T142	4		T230	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T16	1		T134	12		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T16	9		T94	10		T97	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T39	7		T143	7		T221	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	3		T133	7		T262	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T16	2		T234	7		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T132	12		T221	6		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	14		T223	9		T216	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T40	5		T25	11		T142	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14