Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24124

1

T1

138

T2

10

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3640

1

T3

3

T5

2

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21811

1

T1

138

T3

1

T4

1

auto[1]

5953

1

T2

10

T3

2

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	151	1			T9	7		T35	17		T36	1
values[0]	58	1			T152	1		T161	22		T332	26
values[1]	694	1			T5	1		T8	11		T12	7
values[2]	714	1			T4	1		T9	10		T67	1
values[3]	751	1			T3	1		T43	16		T151	1
values[4]	692	1			T4	1		T5	1		T131	2
values[5]	2915	1			T2	10		T3	1		T7	2
values[6]	605	1			T3	1		T7	21		T40	6
values[7]	675	1			T39	16		T148	12		T139	12
values[8]	521	1			T5	1		T43	15		T132	20
values[9]	1350	1			T7	1		T13	26		T131	11
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	696	1			T8	11		T12	7		T27	1
values[1]	714	1			T4	1		T9	10		T67	1
values[2]	691	1			T3	1		T5	1		T43	16
values[3]	3085	1			T2	10		T3	1		T4	1
values[4]	476	1			T7	2		T9	4		T32	1
values[5]	694	1			T3	1		T7	21		T40	6
values[6]	584	1			T43	15		T39	16		T148	12
values[7]	710	1			T5	1		T40	29		T52	13
values[8]	1045	1			T7	1		T9	7		T13	26
values[9]	154	1			T35	16		T216	17		T56	10
minimum	18915	1			T1	138		T5	1		T6	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T27	1		T149	1		T15	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	11		T12	1		T142	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	1		T67	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	1		T139	1		T82	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T151	1		T140	1		T25	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	1		T5	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1586	1			T2	1		T4	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	1		T139	1		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	1		T9	1		T78	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T32	1		T15	2		T221	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	11		T40	6		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T16	1		T79	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T43	1		T142	5		T84	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T39	9		T148	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T40	5		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	3		T52	3		T132	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	15		T131	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T7	1		T9	1		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T56	2		T255	1		T263	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T35	9		T216	8		T197	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18594	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T5	1		T14	6		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T15	1		T16	10		T150	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	6		T219	2		T224	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T131	2		T78	12		T86	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	9		T139	10		T82	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T140	4		T25	12		T16	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	15		T224	21		T21	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T2	9		T11	2		T131	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T139	4		T34	1		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	1		T9	3		T78	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T221	8		T19	1		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	10		T139	11		T52	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T79	11		T234	9		T97	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T43	14		T143	12		T221	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T39	7		T148	11		T215	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T40	9		T220	13		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T40	12		T52	10		T132	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	11		T131	10		T140	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	6		T195	4		T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T56	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T35	7		T216	9		T197	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	1		T67	1		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T14	20		T168	4		T278	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T35	1		T36	1		T251	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T9	1		T35	9		T292	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T161	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T152	1		T332	13		T333	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T27	1		T149	1		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T8	11		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	1		T67	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	1		T139	1		T82	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T151	1		T25	12		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	1		T43	1		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	1		T131	1		T39	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	1		T139	1		T36	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T2	1		T7	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	1		T32	1		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	11		T40	6		T217	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	1		T15	2		T79	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T139	1		T52	11		T142	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T39	9		T148	1		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	1		T43	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T132	13		T150	1		T84	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T13	15		T131	1		T40	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	426	1			T7	1		T40	3		T52	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T251	2		T334	1		T107	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T9	6		T35	7		T197	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T161	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T332	13		T333	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	1		T16	10		T150	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	6		T14	20		T219	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T131	2		T86	25		T221	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	9		T139	10		T82	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T25	12		T16	11		T78	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	15		T224	21		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T131	1		T39	5		T140	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T139	4		T36	5		T220	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T2	9		T7	1		T9	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T34	1		T221	8		T19	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	10		T217	6		T241	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T79	11		T234	9		T163	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T139	11		T52	9		T143	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T39	7		T148	11		T97	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T43	14		T220	13		T231	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T132	7		T150	9		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T13	11		T131	10		T40	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T40	12		T52	10		T195	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T27	1		T149	1		T15	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T8	1		T12	7		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T4	1		T67	1		T131	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	10		T139	11		T82	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T151	1		T140	5		T25	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T5	1		T43	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T2	10		T4	1		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T139	5		T34	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	2		T9	4		T78	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T32	1		T15	2		T221	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	11		T40	1		T139	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T3	1		T16	1		T79	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T43	15		T142	1		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	8		T148	12		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	1		T40	10		T220	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T40	13		T52	11		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T13	12		T131	11		T140	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T7	1		T9	7		T195	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T56	10		T255	1		T263	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T35	10		T216	10		T197	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18719	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T5	1		T14	23		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T15	2		T16	9		T133	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	10		T142	16		T224	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T133	7		T84	4		T86	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T82	13		T143	7		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T25	11		T16	9		T240	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T224	21		T236	10		T21	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T38	27		T39	7		T41	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T36	3		T222	3		T177	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T303	19		T260	9		T258	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T221	2		T237	7		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	10		T40	5		T52	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T79	11		T234	13		T97	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T142	4		T84	4		T143	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	8		T84	2		T275	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T40	4		T229	2		T231	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T40	2		T52	2		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	14		T262	12		T251	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T223	9		T233	12		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T263	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T35	6		T216	7		T197	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T226	2		T253	11		T161	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T14	3		T168	2		T278	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T35	1		T36	1		T251	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T9	7		T35	10		T292	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T161	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T152	1		T332	14		T333	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T27	1		T149	1		T15	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	1		T8	1		T12	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	1		T67	1		T131	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	10		T139	11		T82	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T151	1		T25	13		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T43	16		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	1		T131	2		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T139	5		T36	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T2	10		T7	2		T9	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	1		T32	1		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	11		T40	1		T217	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	1		T15	2		T79	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T139	12		T52	10		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T39	8		T148	12		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T43	15		T220	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T132	8		T150	10		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T13	12		T131	11		T40	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	394	1			T7	1		T40	13		T52	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T251	7		T290	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T35	6		T197	1		T171	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T161	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T332	12		T333	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	2		T16	9		T133	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	10		T14	3		T142	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T133	7		T86	23		T221	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T82	13		T143	7		T248	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T25	11		T16	9		T84	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T224	21		T17	1		T236	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T39	7		T16	1		T177	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T36	3		T222	3		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T38	27		T41	26		T28	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T221	2		T237	7		T247	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T7	10		T40	5		T217	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T79	11		T234	13		T163	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T52	10		T142	4		T84	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	8		T275	13		T97	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T229	2		T231	15		T335	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T132	12		T84	2		T237	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T13	14		T40	4		T262	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T40	2		T52	2		T223	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14