Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21773

1

T1

138

T3

2

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

5991

1

T2

10

T3

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21408

1

T1

138

T3

2

T4

1

auto[1]

6356

1

T2

10

T3

1

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	171	1			T149	1		T242	13		T252	3
values[0]	54	1			T7	21		T133	8		T91	1
values[1]	758	1			T25	24		T32	1		T52	13
values[2]	843	1			T3	1		T43	15		T39	13
values[3]	813	1			T4	1		T9	11		T32	1
values[4]	684	1			T4	1		T43	16		T131	3
values[5]	663	1			T13	26		T131	11		T139	12
values[6]	678	1			T3	2		T7	3		T131	2
values[7]	693	1			T5	1		T9	10		T39	16
values[8]	675	1			T5	2		T8	11		T67	1
values[9]	3094	1			T2	10		T11	3		T12	7
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	838	1			T7	21		T43	15		T25	24
values[1]	3131	1			T2	10		T3	1		T4	1
values[2]	890	1			T4	1		T9	7		T40	14
values[3]	546	1			T43	16		T131	3		T151	1
values[4]	729	1			T7	2		T13	26		T131	11
values[5]	618	1			T3	2		T7	1		T131	2
values[6]	712	1			T5	2		T9	10		T39	16
values[7]	642	1			T5	1		T8	11		T12	7
values[8]	579	1			T148	12		T139	5		T140	5
values[9]	200	1			T15	2		T185	1		T252	3
minimum	18879	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	11		T52	3		T15	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T43	1		T25	12		T283	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	1		T4	1		T39	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1622	1			T2	1		T9	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	1		T9	1		T14	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T40	5		T32	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T151	1		T223	10		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	1		T131	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T131	1		T139	1		T78	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	1		T13	15		T233	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	1		T220	1		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	1		T7	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	1		T39	9		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T9	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	11		T67	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	1		T12	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T148	1		T140	1		T16	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T139	1		T32	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T15	2		T19	1		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T185	1		T252	3		T237	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18557	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T32	1		T133	8		T147	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	10		T52	10		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T43	14		T25	12		T241	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	5		T40	12		T35	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1115	1			T2	9		T9	3		T11	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	6		T14	20		T221	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	9		T52	9		T195	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T223	9		T78	12		T216	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T43	15		T131	2		T140	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T131	10		T139	11		T78	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	1		T13	11		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T220	13		T242	3		T230	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T131	1		T220	9		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T39	7		T139	10		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	9		T82	12		T18	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T34	1		T133	12		T86	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	6		T36	5		T221	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T148	11		T140	4		T16	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T139	4		T144	14		T222	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T19	1		T191	8		T336	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T218	9		T243	3		T272	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T67	1		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T147	5		T279	6		T258	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T242	1		T19	1		T56	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T149	1		T252	3		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T7	11		T91	1		T245	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T133	8		T239	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T52	3		T15	3		T16	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T25	12		T32	1		T283	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T39	8		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T43	1		T27	1		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	1		T9	1		T142	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T9	1		T32	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	1		T151	1		T14	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T43	1		T131	1		T40	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T131	1		T139	1		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	15		T233	13		T16	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	1		T220	1		T242	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	1		T7	2		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T39	9		T139	1		T224	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T9	1		T40	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	1		T8	11		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	1		T82	14		T36	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T148	1		T140	1		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1610	1			T2	1		T11	1		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T242	12		T19	1		T191	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T191	10		T160	14		T155	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T7	10		T245	6		T311	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T239	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T52	10		T15	1		T16	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T25	12		T241	10		T247	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T39	5		T40	12		T35	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T43	14		T133	4		T248	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	6		T217	6		T224	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	3		T52	9		T195	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	20		T223	9		T78	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T43	15		T131	2		T40	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T131	10		T139	11		T78	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	11		T16	10		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T220	13		T242	3		T230	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	1		T131	1		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	7		T139	10		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	9		T220	9		T18	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T34	1		T133	12		T86	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T82	12		T36	5		T221	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T148	11		T140	4		T16	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1136	1			T2	9		T11	2		T12	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	11		T52	11		T15	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T43	15		T25	13		T283	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	1		T4	1		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1453	1			T2	10		T9	4		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T4	1		T9	7		T14	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T40	10		T32	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T151	1		T223	10		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T43	16		T131	3		T140	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T131	11		T139	12		T78	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	2		T13	12		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	1		T220	14		T242	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	1		T7	1		T131	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	1		T39	8		T139	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	1		T9	10		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	1		T67	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	1		T12	7		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T148	12		T140	5		T16	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T139	5		T32	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T15	2		T19	2		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T185	1		T252	1		T237	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18710	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T32	1		T133	1		T147	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	10		T52	2		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T25	11		T248	9		T247	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	7		T40	2		T35	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1284	1			T38	27		T41	26		T28	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	3		T142	4		T221	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T40	4		T52	10		T216	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T223	9		T216	7		T229	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T142	16		T16	9		T247	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T79	11		T86	12		T143	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	14		T233	12		T134	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T230	12		T21	6		T250	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T40	5		T37	1		T190	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T39	8		T224	12		T288	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T82	13		T18	2		T222	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	10		T133	9		T86	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	3		T221	2		T251	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T16	9		T84	4		T221	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T222	10		T226	13		T189	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T171	11		T266	11		T337	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T252	2		T237	7		T162	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T16	2		T338	15		T261	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T133	7		T147	16		T279	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T242	13		T19	2		T56	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T149	1		T252	1		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T7	11		T91	1		T245	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T133	1		T239	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T52	11		T15	2		T16	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T25	13		T32	1		T283	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	1		T39	6		T40	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T43	15		T27	1		T133	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	1		T9	7		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T9	4		T32	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T4	1		T151	1		T14	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T43	16		T131	3		T40	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T131	11		T139	12		T78	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	12		T233	1		T16	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	1		T220	14		T242	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T7	3		T131	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T39	8		T139	11		T224	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T9	10		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T8	1		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	1		T82	13		T36	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T148	12		T140	5		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1495	1			T2	10		T11	3		T12	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T339	2		T337	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T252	2		T162	10		T155	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T7	10		T245	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T133	7		T239	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T52	2		T15	2		T16	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T25	11		T247	12		T188	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T39	7		T40	2		T35	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T133	2		T84	6		T248	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T142	4		T217	7		T224	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T52	10		T216	10		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	3		T223	9		T221	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T40	4		T142	16		T186	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T79	11		T86	12		T143	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	14		T233	12		T16	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T230	12		T164	2		T335	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T212	18		T231	15		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T39	8		T224	12		T21	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T40	5		T18	2		T222	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	10		T133	9		T86	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T82	13		T36	3		T221	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T16	9		T84	4		T221	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1251	1			T38	27		T41	26		T28	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14