Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T7	11		T52	11		T15	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T43	15		T25	13		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	1		T39	6		T40	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1476	1			T2	10		T9	4		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	2		T9	7		T14	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	10		T32	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T151	1		T223	10		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T43	16		T131	3		T140	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T131	11		T139	12		T78	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	12		T233	1		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	1		T79	12		T220	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	2		T131	2		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	1		T39	8		T139	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	1		T5	1		T7	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	1		T67	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	1		T12	7		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T148	12		T140	5		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T139	5		T151	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T15	2		T19	2		T240	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T32	1		T185	1		T144	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T7	10		T52	2		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T25	11		T133	7		T248	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	7		T40	2		T35	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1326	1			T38	27		T41	26		T28	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	3		T142	4		T221	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	4		T52	10		T84	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T223	9		T216	7		T249	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T142	16		T16	9		T134	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T86	12		T143	7		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	14		T233	12		T212	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T79	11		T230	12		T21	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T40	5		T18	2		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	8		T224	12		T250	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T82	13		T222	3		T177	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	10		T16	9		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T36	3		T221	2		T251	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T84	4		T221	3		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T222	10		T226	13		T189	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T240	4		T208	1		T171	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T252	2		T237	7		T162	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T191	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T7	11		T244	14		T245	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T238	8		T239	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T52	11		T16	16		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T25	13		T32	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	1		T39	6		T40	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T43	15		T27	1		T133	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	2		T9	7		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	4		T32	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T14	23		T149	1		T223	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T43	16		T131	3		T40	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T139	12		T79	12		T85	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	12		T140	4		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	1		T131	11		T78	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	1		T5	1		T7	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T39	8		T139	11		T224	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	10		T40	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	1		T8	1		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	1		T82	13		T36	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T148	12		T140	5		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1573	1			T2	10		T11	3		T12	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T7	10		T244	16		T245	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T238	8		T239	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T52	2		T16	3		T240	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T25	11		T133	7		T247	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T39	7		T40	2		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T133	2		T84	6		T248	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T142	4		T217	7		T224	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T52	10		T216	10		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	3		T223	9		T221	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T40	4		T142	16		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T79	11		T86	12		T143	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	14		T233	12		T16	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T230	12		T21	6		T190	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T231	15		T37	1		T155	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	8		T224	12		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T40	5		T18	2		T222	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	10		T133	9		T86	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T82	13		T36	3		T221	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	9		T84	4		T221	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1290	1			T38	27		T41	26		T28	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14