Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24079

1

T1

138

T2

10

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3685

1

T3

2

T5

1

T8

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21856

1

T1

138

T4

1

T5

1

auto[1]

5908

1

T2

10

T3

3

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T35	1		T254	1		T97	1
values[0]	67	1			T150	9		T152	1		T253	12
values[1]	710	1			T5	1		T8	11		T12	7
values[2]	717	1			T4	1		T9	10		T67	1
values[3]	745	1			T3	1		T43	16		T139	5
values[4]	688	1			T4	1		T5	1		T131	2
values[5]	2949	1			T2	10		T3	1		T7	2
values[6]	524	1			T3	1		T7	21		T40	6
values[7]	705	1			T39	16		T148	12		T139	12
values[8]	534	1			T5	1		T43	15		T132	20
values[9]	1484	1			T7	1		T9	7		T13	26
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	938	1			T5	1		T8	11		T12	7
values[1]	704	1			T4	1		T9	10		T67	1
values[2]	737	1			T3	1		T5	1		T139	5
values[3]	3052	1			T2	10		T3	1		T4	1
values[4]	445	1			T7	2		T9	4		T32	1
values[5]	760	1			T3	1		T7	21		T40	6
values[6]	576	1			T43	15		T39	16		T148	12
values[7]	711	1			T5	1		T40	29		T52	13
values[8]	988	1			T7	1		T9	7		T13	26
values[9]	205	1			T35	16		T56	10		T255	1
minimum	18648	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T151	1		T27	2		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	1		T8	11		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	1		T67	1		T133	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	1		T131	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T151	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	1		T139	1		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T2	1		T4	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	1		T43	1		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T7	1		T9	1		T78	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T32	1		T15	2		T221	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	1		T7	11		T40	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T139	1		T16	1		T79	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T43	1		T52	11		T142	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T39	9		T148	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	1		T40	5		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	3		T52	3		T195	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	1		T13	15		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T9	1		T223	10		T233	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T56	2		T255	1		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T35	9		T147	23		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18518	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	1		T16	10		T150	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	6		T14	20		T150	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T78	12		T86	25		T143	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	9		T131	2		T139	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T140	4		T25	12		T16	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T139	4		T224	21		T222	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T2	9		T11	2		T131	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T43	15		T34	1		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T7	1		T9	3		T78	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T221	8		T19	1		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	10		T217	6		T155	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T139	11		T79	11		T234	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T43	14		T52	9		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	7		T148	11		T221	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T40	9		T220	13		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T40	12		T52	10		T195	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	11		T131	10		T140	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	6		T223	9		T133	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T56	8		T163	14		T258	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T35	7		T147	22		T257	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T35	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T254	1		T97	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T253	12		T161	13		T259	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T150	1		T152	1		T186	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T27	1		T149	1		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	1		T8	11		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	1		T67	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	1		T131	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T151	1		T25	12		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	1		T43	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	1		T5	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T32	1		T36	8		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T2	1		T7	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T32	1		T15	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	1		T7	11		T40	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T79	12		T85	1		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T52	11		T142	5		T143	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T39	9		T148	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T43	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T132	13		T150	1		T144	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T7	1		T13	15		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	524	1			T9	1		T40	3		T52	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T161	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T150	8		T186	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	1		T16	10		T150	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	6		T14	20		T240	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T86	12		T143	4		T221	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	9		T131	2		T139	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T25	12		T16	11		T78	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	15		T139	4		T224	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T131	1		T39	5		T140	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T36	5		T220	9		T242	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T2	9		T7	1		T9	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T34	1		T221	8		T19	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	10		T217	6		T241	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T79	11		T234	9		T163	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T52	9		T143	12		T255	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	7		T148	11		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T43	14		T220	13		T231	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T132	7		T150	9		T144	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	11		T131	10		T40	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T9	6		T40	12		T52	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T151	1		T27	2		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T5	1		T8	1		T12	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T4	1		T67	1		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	10		T131	3		T139	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T151	1		T140	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	1		T139	5		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T2	10		T4	1		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	1		T43	16		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	2		T9	4		T78	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T32	1		T15	2		T221	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	1		T7	11		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T139	12		T16	1		T79	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	15		T52	10		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	8		T148	12		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	1		T40	10		T220	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T40	13		T52	11		T195	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	1		T13	12		T131	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T9	7		T223	10		T233	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T56	10		T255	1		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T35	10		T147	23		T257	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18639	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T15	2		T16	9		T133	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T8	10		T14	3		T142	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T133	7		T84	4		T86	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T82	13		T17	1		T248	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T25	11		T16	9		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T224	21		T222	3		T240	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T38	27		T39	7		T41	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T36	3		T228	2		T190	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T260	9		T258	2		T261	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T221	2		T237	7		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	10		T40	5		T217	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T79	11		T234	13		T97	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T52	10		T142	4		T84	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	8		T84	2		T221	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T40	4		T229	2		T231	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	2		T52	2		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	14		T16	2		T262	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T223	9		T233	12		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T163	16		T258	12		T263	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T35	6		T147	22		T264	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T265	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T35	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T254	1		T97	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T253	1		T161	10		T259	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T150	9		T152	1		T186	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T27	1		T149	1		T15	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	1		T8	1		T12	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	1		T67	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	10		T131	3		T139	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T151	1		T25	13		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	1		T43	16		T139	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	1		T5	1		T131	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T32	1		T36	10		T220	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T2	10		T7	2		T9	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T32	1		T15	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T7	11		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T79	12		T85	1		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T52	10		T142	1		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T39	8		T148	12		T139	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T43	15		T220	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T132	8		T150	10		T144	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T7	1		T13	12		T131	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	491	1			T9	7		T40	13		T52	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T253	11		T161	12		T259	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T186	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	2		T16	9		T133	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T8	10		T14	3		T142	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T133	7		T86	11		T143	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T82	13		T224	1		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T25	11		T16	9		T84	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T224	21		T188	8		T240	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T39	7		T16	1		T247	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T36	3		T222	3		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T38	27		T41	26		T28	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T221	2		T237	7		T247	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T7	10		T40	5		T84	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T79	11		T234	13		T163	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T52	10		T142	4		T143	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T39	8		T84	2		T221	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T229	2		T231	15		T237	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T132	12		T37	1		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	14		T40	4		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	416	1			T40	2		T52	2		T35	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14