Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24035

1

T1

138

T2

10

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3729

1

T3

3

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21592

1

T1

138

T3

2

T4

2

auto[1]

6172

1

T2

10

T3

1

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T223	19		T266	1		T245	14
values[0]	84	1			T27	1		T240	12		T265	11
values[1]	604	1			T8	11		T67	1		T39	13
values[2]	603	1			T5	1		T7	1		T9	4
values[3]	558	1			T3	1		T7	2		T9	10
values[4]	811	1			T3	1		T39	16		T40	6
values[5]	2941	1			T2	10		T11	3		T38	29
values[6]	703	1			T13	26		T40	14		T151	1
values[7]	768	1			T3	1		T4	1		T140	5
values[8]	432	1			T5	1		T43	16		T52	13
values[9]	1588	1			T4	1		T5	1		T7	21
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	760	1			T5	1		T67	1		T131	11
values[1]	656	1			T3	1		T7	1		T8	11
values[2]	705	1			T9	10		T148	12		T139	11
values[3]	3056	1			T2	10		T7	2		T11	3
values[4]	666	1			T3	1		T13	26		T40	6
values[5]	624	1			T3	1		T151	2		T32	2
values[6]	645	1			T4	1		T5	1		T40	14
values[7]	671	1			T43	15		T27	1		T149	1
values[8]	1175	1			T5	1		T7	21		T9	7
values[9]	168	1			T4	1		T224	20		T197	8
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T67	1		T131	1		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	1		T39	8		T40	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T15	3		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	1		T7	1		T8	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	1		T139	1		T52	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T148	1		T84	5		T86	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T2	1		T11	1		T38	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	1		T39	9		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T149	1		T85	1		T36	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	1		T13	15		T40	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T151	1		T32	2		T212	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	1		T151	1		T16	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T140	1		T16	2		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	1		T5	1		T40	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T43	1		T52	3		T233	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T27	1		T149	1		T142	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T5	1		T7	11		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T12	1		T43	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T4	1		T267	13		T235	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T224	10		T197	6		T178	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T131	10		T35	7		T224	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T39	5		T40	12		T139	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T9	3		T15	1		T133	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T82	12		T86	13		T268	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T9	9		T139	10		T52	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T148	11		T86	12		T143	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1114	1			T2	9		T11	2		T269	35
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	1		T39	7		T139	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T36	5		T221	3		T144	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	11		T177	4		T227	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T218	5		T262	6		T270	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T133	12		T231	12		T234	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T140	4		T16	1		T150	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	9		T16	11		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T43	14		T52	10		T78	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T220	13		T19	2		T137	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T7	10		T9	6		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	6		T43	15		T131	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T267	12		T271	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T224	10		T197	2		T272	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T266	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T223	10		T245	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T273	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T27	1		T240	5		T265	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T67	1		T35	9		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	11		T39	8		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	1		T131	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	1		T7	1		T25	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	1		T139	1		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	1		T7	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	6		T52	11		T16	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T3	1		T39	9		T40	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T2	1		T11	1		T38	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T139	1		T151	1		T274	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T151	1		T32	1		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	15		T40	5		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T140	1		T32	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	1		T4	1		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T52	3		T78	1		T275	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	1		T43	1		T142	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	462	1			T4	1		T5	1		T7	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	475	1			T12	1		T131	1		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T223	9		T245	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T273	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T240	7		T276	11		T277	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	7		T133	4		T241	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T39	5		T40	12		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	3		T131	10		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T25	12		T82	12		T221	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T9	9		T139	10		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T7	1		T86	13		T143	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	20		T52	9		T16	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T39	7		T148	11		T16	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1101	1			T2	9		T11	2		T269	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T139	4		T234	7		T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	1		T36	5		T144	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	11		T40	9		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T140	4		T150	8		T234	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T16	11		T150	9		T133	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T52	10		T78	12		T251	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T43	15		T19	2		T222	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T7	10		T9	6		T43	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T12	6		T131	1		T220	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T67	1		T131	11		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T5	1		T39	6		T40	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	4		T15	2		T133	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T7	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	10		T139	11		T52	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T148	12		T84	1		T86	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1473	1			T2	10		T11	3		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	2		T39	8		T139	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T149	1		T85	1		T36	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	1		T13	12		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T151	1		T32	2		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T151	1		T16	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T140	5		T16	2		T150	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T4	1		T5	1		T40	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	15		T52	11		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T27	1		T149	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T5	1		T7	11		T9	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T12	7		T43	16		T131	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T4	1		T267	13		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T224	11		T197	7		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T35	6		T224	1		T248	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T39	7		T40	2		T25	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	2		T133	2		T84	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	10		T82	13		T86	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T52	10		T79	11		T255	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T84	4		T86	11		T143	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T38	27		T41	26		T14	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T39	8		T16	9		T132	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T36	3		T221	3		T94	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	14		T40	5		T188	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T212	18		T262	12		T250	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T133	9		T231	15		T278	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T16	1		T252	2		T234	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T40	4		T16	2		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T52	2		T233	12		T275	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T142	16		T133	7		T188	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T7	10		T142	4		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T223	9		T228	19		T279	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T267	12		T235	2		T178	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T224	9		T197	1		T178	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T266	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T223	10		T245	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T273	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T27	1		T240	8		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T67	1		T35	10		T133	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	1		T39	6		T40	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	4		T131	11		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	1		T7	1		T25	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T9	10		T139	11		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	1		T7	2		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	23		T52	10		T16	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T3	1		T39	8		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T2	10		T11	3		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T139	5		T151	1		T274	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T151	1		T32	1		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	12		T40	10		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T140	5		T32	1		T150	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	1		T4	1		T16	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T52	11		T78	13		T275	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T5	1		T43	16		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	395	1			T4	1		T5	1		T7	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	413	1			T12	7		T131	2		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T223	9		T245	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T273	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T240	4		T265	10		T276	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T35	6		T133	2		T248	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	10		T39	7		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	2		T84	2		T221	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T25	11		T82	13		T221	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T79	11		T84	4		T255	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T86	12		T143	2		T217	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T14	3		T52	10		T16	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T39	8		T40	5		T16	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T38	27		T41	26		T28	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T188	8		T260	9		T280	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T16	1		T36	3		T212	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	14		T40	4		T231	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T252	2		T234	13		T247	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T16	2		T133	9		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T52	2		T275	13		T251	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T142	16		T222	10		T226	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T7	10		T142	4		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T133	7		T224	9		T188	28

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14