Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24436

1

T1

138

T2

10

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3328

1

T3

1

T4

1

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21552

1

T1

138

T3

1

T5

1

auto[1]

6212

1

T2

10

T3

2

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	33	1			T180	18		T281	3		T282	12
values[0]	51	1			T5	1		T150	10		T237	8
values[1]	638	1			T5	1		T7	2		T43	15
values[2]	657	1			T3	1		T7	21		T131	14
values[3]	610	1			T7	1		T39	13		T139	12
values[4]	3045	1			T2	10		T4	2		T11	3
values[5]	746	1			T131	2		T40	6		T140	5
values[6]	662	1			T3	2		T9	10		T14	26
values[7]	706	1			T9	4		T233	13		T150	9
values[8]	661	1			T9	7		T43	16		T151	1
values[9]	1317	1			T5	1		T8	11		T13	26
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	771	1			T5	2		T7	2		T43	15
values[1]	710	1			T3	1		T7	21		T131	14
values[2]	702	1			T4	1		T7	1		T39	13
values[3]	2993	1			T2	10		T4	1		T11	3
values[4]	764	1			T131	2		T40	6		T14	26
values[5]	571	1			T3	2		T9	10		T52	20
values[6]	812	1			T9	4		T150	9		T78	4
values[7]	571	1			T9	7		T43	16		T39	16
values[8]	957	1			T5	1		T13	26		T148	12
values[9]	275	1			T8	11		T40	15		T25	24
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T5	1		T43	1		T67	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	1		T7	1		T40	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	1		T151	1		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	11		T131	2		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	1		T39	8		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	1		T254	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T2	1		T4	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T34	2		T16	1		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T40	6		T32	1		T222	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T131	1		T14	6		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	1		T52	11		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T9	1		T16	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	1		T150	1		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T144	1		T283	1		T216	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	9		T151	1		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	1		T43	1		T86	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T5	1		T13	15		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T149	1		T150	1		T85	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T8	11		T40	3		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T25	12		T15	2		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T43	14		T16	11		T82	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	1		T40	9		T150	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T234	7		T145	14		T278	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	10		T131	12		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	5		T140	3		T52	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T218	5		T240	9		T226	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T2	9		T11	2		T12	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T34	1		T146	12		T189	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T222	10		T137	2		T56	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T131	1		T14	20		T133	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T52	9		T15	1		T78	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	9		T16	10		T132	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	3		T150	8		T78	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T144	11		T216	6		T18	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T39	7		T195	4		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	6		T43	15		T86	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	11		T148	11		T139	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T150	14		T137	25		T177	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T40	12		T147	5		T163	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T25	12		T262	6		T284	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T180	6		T281	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T282	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T5	1		T237	8		T285	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T150	1		T286	10		T239	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T43	1		T67	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	1		T7	1		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	1		T151	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T7	11		T131	2		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T39	8		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T139	1		T149	1		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T2	1		T4	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	1		T16	1		T185	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T40	6		T140	1		T142	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T131	1		T149	1		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	1		T32	1		T52	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	1		T9	1		T14	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	1		T233	13		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T221	4		T144	1		T283	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T151	1		T195	1		T230	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	1		T43	1		T86	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	444	1			T5	1		T8	11		T13	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T25	12		T149	1		T15	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T180	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T282	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T285	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T150	9		T286	2		T239	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T43	14		T16	11		T82	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	1		T40	9		T36	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T140	3		T234	7		T145	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	10		T131	12		T78	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	5		T52	10		T35	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T139	11		T218	5		T240	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T2	9		T11	2		T12	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T226	16		T21	7		T189	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T140	4		T143	12		T144	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T131	1		T34	1		T16	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T52	9		T15	1		T78	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T9	9		T14	20		T132	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	3		T150	8		T78	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T221	3		T144	11		T216	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T195	4		T230	12		T19	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	6		T43	15		T86	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T13	11		T39	7		T40	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T25	12		T150	14		T137	25
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T5	1		T43	15		T67	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	1		T7	2		T40	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T151	1		T234	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	11		T131	14		T139	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	1		T39	6		T140	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	1		T254	1		T218	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T2	10		T4	1		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T34	3		T16	1		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T40	1		T32	1		T222	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T131	2		T14	23		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	1		T52	10		T15	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T9	10		T16	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	4		T150	9		T78	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T144	12		T283	1		T216	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T39	8		T151	1		T195	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	7		T43	16		T86	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T5	1		T13	12		T148	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T149	1		T150	15		T85	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T8	1		T40	13		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T25	13		T15	2		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T16	2		T82	13		T212	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T40	4		T142	4		T84	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T278	5		T161	12		T280	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	10		T275	13		T168	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T39	7		T52	2		T35	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T240	6		T226	13		T21	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T38	27		T41	26		T28	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T188	16		T146	13		T189	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T40	5		T222	3		T236	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	3		T133	11		T79	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T52	10		T15	2		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T16	9		T132	12		T84	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T230	12		T197	1		T190	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T216	10		T18	2		T260	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	8		T224	12		T188	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T86	23		T221	8		T231	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T13	14		T84	4		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T177	1		T228	2		T190	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T8	10		T40	2		T147	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T25	11		T262	12		T235	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T180	13		T281	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T282	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T5	1		T237	1		T285	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T150	10		T286	6		T239	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	15		T67	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	1		T7	2		T40	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T3	1		T151	1		T140	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	11		T131	14		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	1		T39	6		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T139	12		T149	1		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T2	10		T4	1		T11	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	1		T16	1		T185	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T40	1		T140	5		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T131	2		T149	1		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	1		T32	1		T52	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	1		T9	10		T14	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	4		T233	1		T150	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T221	4		T144	12		T283	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T151	1		T195	5		T230	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	7		T43	16		T86	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T5	1		T8	1		T13	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T25	13		T149	1		T15	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T180	5		T281	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T237	7		T285	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T286	6		T239	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	2		T82	13		T212	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T40	4		T84	2		T36	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T161	12		T155	7		T280	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T7	10		T142	4		T170	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T39	7		T52	2		T35	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T240	6		T275	13		T168	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T38	27		T41	26		T28	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T226	13		T21	6		T189	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T40	5		T142	16		T143	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T16	9		T133	11		T79	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T52	10		T15	2		T133	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	3		T132	12		T84	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T233	12		T197	1		T190	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T221	3		T216	7		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T230	12		T287	10		T288	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T86	23		T221	8		T216	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T8	10		T13	14		T39	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T25	11		T247	12		T262	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14