Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24170

1

T1

138

T2

10

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3594

1

T3

2

T4

2

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21791

1

T1

138

T3

2

T4

1

auto[1]

5973

1

T2

10

T3

1

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	42	1			T16	20		T289	2		T290	19
values[0]	8	1			T165	1		T291	6		T210	1
values[1]	463	1			T3	1		T8	11		T29	1
values[2]	601	1			T9	4		T15	2		T84	3
values[3]	951	1			T4	1		T7	21		T131	3
values[4]	611	1			T40	15		T148	12		T139	12
values[5]	861	1			T9	7		T43	15		T67	1
values[6]	725	1			T5	1		T43	16		T39	13
values[7]	656	1			T4	1		T5	1		T7	1
values[8]	597	1			T3	1		T5	1		T9	10
values[9]	3611	1			T2	10		T3	1		T7	2
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	638	1			T3	1		T8	11		T29	1
values[1]	724	1			T7	21		T9	4		T40	14
values[2]	829	1			T4	1		T131	3		T39	16
values[3]	638	1			T67	1		T148	12		T139	23
values[4]	844	1			T5	1		T9	7		T43	15
values[5]	633	1			T4	1		T7	1		T43	16
values[6]	3137	1			T2	10		T5	1		T9	10
values[7]	537	1			T3	1		T5	1		T12	7
values[8]	961	1			T3	1		T7	2		T13	26
values[9]	178	1			T151	1		T142	5		T220	14
minimum	18645	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T149	1		T283	1		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	1		T8	11		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T40	5		T32	1		T52	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	11		T9	1		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T40	3		T151	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T4	1		T131	1		T39	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T148	1		T139	2		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T67	1		T36	1		T254	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	1		T43	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T5	1		T39	8		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T149	1		T35	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	1		T7	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T2	1		T5	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	1		T14	6		T230	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	1		T131	1		T27	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	1		T12	1		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T3	1		T7	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	15		T131	1		T16	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T151	1		T142	5		T292	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T220	1		T234	14		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18514	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T165	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T17	1		T222	10		T218	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T223	9		T132	7		T222	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T40	9		T52	9		T224	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T7	10		T9	3		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	12		T140	3		T143	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T131	2		T39	7		T25	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T148	11		T139	21		T52	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T231	12		T234	6		T248	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	6		T43	14		T140	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T39	5		T15	1		T16	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T150	8		T133	4		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T43	15		T221	5		T220	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T2	9		T11	2		T269	35
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	9		T14	20		T230	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T131	10		T79	11		T219	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T12	6		T218	5		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	1		T139	4		T35	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	11		T131	1		T16	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T293	11		T294	10		T295	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T220	13		T234	9		T137	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T289	1		T290	19		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T16	10		T296	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T291	1		T210	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T165	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T149	1		T84	5		T283	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	1		T8	11		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T85	1		T274	1		T224	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	1		T15	2		T84	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T40	5		T140	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T4	1		T7	11		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T40	3		T148	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T36	1		T212	19		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T43	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T67	1		T16	12		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T35	1		T150	1		T143	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	1		T43	1		T39	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T40	6		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	1		T7	1		T14	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	1		T131	1		T27	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	1		T9	1		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1743	1			T2	1		T3	1		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T12	1		T13	15		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T289	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T16	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T291	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T17	1		T218	2		T94	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T223	9		T132	7		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T224	8		T222	10		T240	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T9	3		T154	2		T288	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T40	9		T140	3		T52	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T7	10		T131	2		T39	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T40	12		T148	11		T139	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T255	5		T168	4		T297	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	6		T43	14		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T16	12		T133	12		T78	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T150	9		T143	12		T19	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T43	15		T39	5		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T150	8		T133	4		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	20		T221	5		T18	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T131	10		T217	6		T218	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	9		T230	12		T218	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T2	9		T7	1		T11	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T12	6		T13	11		T131	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T149	1		T283	1		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	1		T8	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T40	10		T32	1		T52	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	11		T9	4		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T40	13		T151	1		T140	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T4	1		T131	3		T39	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T148	12		T139	23		T52	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T67	1		T36	1		T254	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	7		T43	15		T140	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T5	1		T39	6		T15	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T149	1		T35	1		T150	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	1		T7	1		T43	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T2	10		T5	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T9	10		T14	23		T230	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T131	11		T27	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	1		T12	7		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T3	1		T7	2		T139	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T13	12		T131	2		T16	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T151	1		T142	1		T292	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T220	14		T234	10		T137	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18640	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T165	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T17	1		T252	2		T222	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	10		T223	9		T132	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T40	4		T52	10		T233	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	10		T84	2		T134	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	2		T143	7		T188	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T39	8		T25	11		T36	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T52	2		T82	13		T221	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T231	15		T234	7		T248	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T221	2		T168	19		T288	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T39	7		T15	2		T16	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T133	2		T143	2		T260	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T221	6		T275	13		T163	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T38	27		T40	5		T41	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	3		T230	12		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T79	11		T224	12		T262	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T133	7		T247	10		T147	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T35	6		T84	4		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	14		T16	11		T216	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T142	4		T236	10		T298	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T234	13		T235	14		T299	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T84	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T289	2		T290	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T16	11		T296	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T291	6		T210	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T165	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T149	1		T84	1		T283	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	1		T8	1		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T85	1		T274	1		T224	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T9	4		T15	2		T84	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T40	10		T140	4		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T4	1		T7	11		T131	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T40	13		T148	12		T139	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T36	1		T212	1		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	7		T43	15		T139	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T67	1		T16	14		T133	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T35	1		T150	10		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T43	16		T39	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T40	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T4	1		T7	1		T14	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T131	11		T27	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	1		T9	10		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1632	1			T2	10		T3	1		T7	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T12	7		T13	12		T131	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T290	18		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T16	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T84	4		T17	1		T252	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T8	10		T223	9		T132	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T224	1		T222	3		T240	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T84	2		T134	12		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	4		T52	10		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	10		T39	8		T25	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T40	2		T237	7		T300	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T212	18		T255	2		T168	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T52	2		T82	13		T221	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T16	10		T133	9		T224	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T143	2		T260	9		T208	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	7		T15	2		T86	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T40	5		T142	16		T133	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T14	3		T221	6		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T217	7		T262	12		T97	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T133	7		T230	12		T287	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T38	27		T41	26		T28	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T13	14		T16	2		T216	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14