Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24142

1

T1

138

T2

10

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3622

1

T4

2

T5

3

T7

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21843

1

T1

138

T3

2

T4

1

auto[1]

5921

1

T2

10

T3

1

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T139	5		T136	1		T287	11
values[0]	27	1			T144	4		T301	5		T273	18
values[1]	650	1			T3	1		T5	1		T12	7
values[2]	677	1			T8	11		T9	4		T40	6
values[3]	645	1			T4	1		T5	1		T7	21
values[4]	785	1			T3	1		T9	10		T40	14
values[5]	792	1			T5	1		T131	3		T148	12
values[6]	634	1			T13	26		T140	5		T25	24
values[7]	644	1			T43	15		T139	12		T16	17
values[8]	2868	1			T2	10		T3	1		T7	2
values[9]	1384	1			T4	1		T7	1		T9	7
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	920	1			T3	1		T5	1		T8	11
values[1]	562	1			T5	1		T9	4		T67	1
values[2]	671	1			T4	1		T7	21		T39	16
values[3]	897	1			T3	1		T9	10		T131	3
values[4]	656	1			T5	1		T13	26		T148	12
values[5]	656	1			T32	1		T142	5		T16	4
values[6]	3036	1			T2	10		T7	2		T11	3
values[7]	537	1			T3	1		T131	11		T151	1
values[8]	972	1			T4	1		T7	1		T43	16
values[9]	192	1			T9	7		T79	23		T254	1
minimum	18665	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	1		T12	1		T40	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T5	1		T8	11		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	1		T32	1		T52	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	1		T67	1		T39	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	11		T219	1		T224	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T4	1		T39	9		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	1		T9	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T14	6		T150	1		T78	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	15		T140	1		T233	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	1		T148	1		T25	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T142	5		T16	3		T217	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T32	1		T143	8		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T2	1		T11	1		T38	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	1		T43	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	1		T16	5		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T131	1		T151	1		T142	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T7	1		T43	1		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T4	1		T131	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T9	1		T147	17		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T79	12		T254	1		T226	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18513	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	6		T40	12		T52	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T139	10		T223	9		T16	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T9	3		T52	10		T190	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T39	5		T140	3		T221	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	10		T219	2		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T39	7		T191	8		T160	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	9		T131	2		T40	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T14	20		T150	8		T78	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	11		T140	4		T133	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T148	11		T25	12		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T16	1		T217	6		T242	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T143	4		T220	9		T218	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T2	9		T11	2		T269	35
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	1		T43	14		T139	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T16	11		T221	5		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T131	10		T144	11		T56	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T43	15		T150	14		T133	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T131	1		T139	4		T78	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T9	6		T147	5		T160	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T79	11		T177	4		T190	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	1		T67	1		T14	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T136	1		T287	11		T23	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T139	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T301	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T144	1		T273	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T12	1		T40	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T139	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	1		T40	6		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	11		T140	1		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	11		T32	1		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	1		T5	1		T67	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	1		T9	1		T40	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T151	1		T150	1		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T131	1		T27	1		T233	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	1		T148	1		T14	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	15		T140	1		T142	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T25	12		T149	1		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T16	6		T218	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T43	1		T139	1		T78	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T2	1		T3	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	1		T131	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T7	1		T9	1		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T4	1		T131	1		T16	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T23	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T139	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T301	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T144	3		T273	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	6		T40	12		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T139	10		T223	9		T16	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	3		T52	9		T35	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T140	3		T242	3		T224	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	10		T52	10		T219	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	12		T221	3		T191	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	9		T40	9		T86	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T150	8		T78	12		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T131	2		T247	10		T215	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T148	11		T14	20		T132	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	11		T140	4		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T25	12		T34	1		T143	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T16	11		T218	5		T137	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T43	14		T139	11		T78	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T2	9		T11	2		T269	35
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	1		T131	10		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T9	6		T43	15		T150	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T131	1		T78	3		T79	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T3	1		T12	7		T40	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	1		T8	1		T139	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	4		T32	1		T52	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	1		T67	1		T39	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	11		T219	3		T224	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	1		T39	8		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	1		T9	10		T131	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T14	23		T150	9		T78	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	12		T140	5		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	1		T148	12		T25	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T142	1		T16	3		T217	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T32	1		T143	5		T220	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T2	10		T11	3		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T7	2		T43	15		T139	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T16	14		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T131	11		T151	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	1		T43	16		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T4	1		T131	2		T139	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T9	7		T147	6		T160	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T79	12		T254	1		T226	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18663	1			T1	138		T6	15		T10	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T40	7		T52	10		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	10		T223	9		T16	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T52	2		T190	2		T302	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T39	7		T221	3		T224	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	10		T224	9		T260	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T39	8		T84	2		T163	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T40	4		T84	8		T86	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T14	3		T36	3		T216	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	14		T233	12		T133	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T25	11		T132	12		T82	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T142	4		T16	1		T217	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T143	7		T94	10		T303	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T38	27		T41	26		T28	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T222	3		T240	2		T226	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T16	2		T212	18		T221	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T142	16		T155	7		T179	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T133	9		T224	1		T237	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T143	2		T231	15		T262	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T147	16		T164	11		T304	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T79	11		T226	2		T177	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T285	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T136	1		T287	1		T23	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T139	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T301	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T144	4		T273	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	1		T12	7		T40	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	1		T139	11		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T9	4		T40	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T140	4		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	11		T32	1		T52	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	1		T5	1		T67	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	1		T9	10		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T151	1		T150	9		T78	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T131	3		T27	1		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T5	1		T148	12		T14	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	12		T140	5		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T25	13		T149	1		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	15		T218	6		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T43	15		T139	12		T78	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T2	10		T3	1		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	2		T131	11		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T7	1		T9	7		T43	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T4	1		T131	2		T16	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T287	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T301	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T273	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T40	2		T15	2		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T223	9		T16	18		T237	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T40	5		T52	10		T35	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	10		T224	12		T240	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	10		T52	2		T224	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T39	15		T84	2		T221	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T40	4		T84	4		T86	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T36	3		T216	10		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T233	12		T84	4		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	3		T132	12		T82	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	14		T142	4		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T25	11		T143	7		T222	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T16	2		T188	12		T289	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T240	2		T226	13		T303	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T38	27		T41	26		T28	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T142	16		T21	1		T197	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T133	9		T221	6		T224	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T79	11		T143	2		T231	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14