Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24109

1

T1

138

T2

10

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3655

1

T4

2

T5

3

T7

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21868

1

T1

138

T3

2

T4

1

auto[1]

5896

1

T2

10

T3

1

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	306	1			T7	1		T9	7		T139	5
values[0]	18	1			T273	18		-	-		-	-
values[1]	662	1			T3	1		T5	1		T12	7
values[2]	680	1			T8	11		T9	4		T67	1
values[3]	645	1			T4	1		T5	1		T7	21
values[4]	789	1			T3	1		T9	10		T40	14
values[5]	705	1			T5	1		T131	3		T148	12
values[6]	777	1			T13	26		T140	5		T25	24
values[7]	596	1			T43	15		T139	12		T16	19
values[8]	2838	1			T2	10		T3	1		T7	2
values[9]	1110	1			T4	1		T43	16		T131	2
minimum	18638	1			T1	138		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	731	1			T3	1		T5	1		T8	11
values[1]	574	1			T5	1		T9	4		T67	1
values[2]	698	1			T4	1		T7	21		T39	16
values[3]	872	1			T3	1		T9	10		T131	3
values[4]	686	1			T5	1		T13	26		T148	12
values[5]	598	1			T139	12		T142	5		T16	4
values[6]	3067	1			T2	10		T3	1		T7	2
values[7]	526	1			T131	11		T151	1		T142	17
values[8]	973	1			T4	1		T7	1		T43	16
values[9]	197	1			T9	7		T79	23		T254	1
minimum	18842	1			T1	138		T6	15		T10	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	1		T12	1		T40	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	1		T8	11		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	1		T32	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T67	1		T39	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T7	11		T32	1		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	1		T39	9		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	1		T9	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T14	6		T132	13		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	15		T140	1		T233	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T148	1		T25	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T142	5		T16	3		T217	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T139	1		T143	8		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T2	1		T3	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	1		T43	1		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T134	1		T212	19		T221	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T131	1		T151	1		T142	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	1		T43	1		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T4	1		T131	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T9	1		T270	1		T287	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T79	12		T254	1		T177	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18561	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T35	1		T85	1		T237	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	6		T40	12		T52	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T139	10		T223	9		T16	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	3		T190	9		T154	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T39	5		T140	3		T242	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	10		T219	2		T221	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	7		T52	10		T234	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	9		T131	2		T40	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T14	20		T132	7		T150	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	11		T140	4		T133	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T148	11		T25	12		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	1		T217	6		T242	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T139	11		T143	4		T220	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T2	9		T11	2		T269	35
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	1		T43	14		T78	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T221	5		T37	1		T228	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T131	10		T144	11		T56	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T43	15		T150	14		T133	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T131	1		T139	4		T78	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T9	6		T270	4		T147	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T79	11		T177	4		T190	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	1		T67	1		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T222	9		T147	22		T305	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T7	1		T9	1		T246	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T139	1		T254	1		T20	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T273	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	1		T12	1		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T139	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	1		T40	9		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	11		T67	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	11		T32	1		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	1		T5	1		T39	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	1		T9	1		T40	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T150	1		T85	1		T36	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T131	1		T233	13		T84	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	1		T148	1		T14	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	15		T140	1		T142	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T25	12		T149	1		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T16	7		T86	13		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T43	1		T139	1		T78	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T2	1		T3	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	1		T131	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T43	1		T15	2		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T4	1		T131	1		T16	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18508	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T9	6		T270	4		T249	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T139	4		T20	1		T278	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T273	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	6		T15	1		T195	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T139	10		T223	9		T16	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	3		T40	12		T52	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T242	3		T224	11		T240	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	10		T219	2		T221	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T39	12		T140	3		T52	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	9		T40	9		T78	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T150	8		T36	5		T216	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T131	2		T247	10		T215	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T148	11		T14	20		T132	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	11		T140	4		T133	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	12		T34	1		T143	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T16	12		T86	13		T218	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T43	14		T139	11		T78	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T2	9		T11	2		T269	35
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	1		T131	10		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T43	15		T150	14		T133	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T131	1		T78	3		T79	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	1		T12	7		T40	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	1		T8	1		T139	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	4		T32	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	1		T67	1		T39	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	11		T32	1		T219	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	1		T39	8		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	1		T9	10		T131	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T14	23		T132	8		T150	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	12		T140	5		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	1		T148	12		T25	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T142	1		T16	3		T217	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T139	12		T143	5		T220	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T2	10		T3	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T7	2		T43	15		T78	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T134	1		T212	1		T221	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T131	11		T151	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	1		T43	16		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T4	1		T131	2		T139	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T9	7		T270	5		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T79	12		T254	1		T177	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18695	1			T1	138		T6	15		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T35	1		T85	1		T237	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T40	7		T52	10		T35	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	10		T223	9		T16	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T190	2		T302	12		T250	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	7		T224	12		T146	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	10		T221	3		T224	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	8		T52	2		T84	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T40	4		T84	8		T86	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	3		T132	12		T36	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	14		T233	12		T133	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T25	11		T82	13		T230	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T142	4		T16	1		T217	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T143	7		T216	7		T240	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T38	27		T41	26		T28	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T222	3		T226	13		T303	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T212	18		T221	6		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T142	16		T155	7		T179	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T133	9		T224	1		T237	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T143	2		T231	15		T262	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T287	10		T147	16		T304	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T79	11		T177	1		T190	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T15	2		T232	4		T306	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T237	7		T222	10		T147	22

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T7	1		T9	7		T246	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T139	5		T254	1		T20	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T273	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	1		T12	7		T15	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T139	11		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T9	4		T40	14		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	1		T67	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	11		T32	1		T219	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	1		T5	1		T39	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	1		T9	10		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T150	9		T85	1		T36	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T131	3		T233	1		T84	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	1		T148	12		T14	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T13	12		T140	5		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T25	13		T149	1		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	16		T86	14		T218	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T43	15		T139	12		T78	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T2	10		T3	1		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	2		T131	11		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T43	16		T15	2		T150	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T4	1		T131	2		T16	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18638	1			T1	138		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T287	10		T249	8		T238	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T278	5		T261	11		T307	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T273	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T15	2		T17	1		T248	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T223	9		T16	9		T237	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	7		T52	10		T35	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T8	10		T224	12		T240	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	10		T221	3		T224	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T39	15		T52	2		T84	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T40	4		T84	4		T86	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T36	3		T216	10		T234	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T233	12		T84	4		T134	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	3		T132	12		T82	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	14		T142	4		T133	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T25	11		T143	7		T216	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T16	3		T86	12		T188	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T222	3		T240	2		T226	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T38	27		T41	26		T28	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T142	16		T21	1		T197	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T133	9		T224	1		T237	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T79	11		T143	2		T231	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14