Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

138

T2

10

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24374

1

T1

138

T2

10

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3390

1

T3

2

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21274

1

T1

135

T3

1

T4

2

auto[1]

6490

1

T1

3

T2

10

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23651

1

T1

138

T2

1

T3

3

auto[1]

4113

1

T2

9

T7

11

T9

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	704	1			T1	3		T9	10		T44	1
values[0]	65	1			T3	1		T139	11		T29	1
values[1]	798	1			T5	1		T8	11		T39	16
values[2]	3097	1			T2	10		T7	21		T9	4
values[3]	451	1			T3	1		T5	1		T7	3
values[4]	783	1			T9	7		T149	1		T52	33
values[5]	854	1			T4	1		T131	11		T40	15
values[6]	505	1			T4	1		T5	1		T131	2
values[7]	811	1			T39	13		T14	26		T27	2
values[8]	576	1			T131	3		T148	12		T151	1
values[9]	994	1			T3	1		T13	26		T43	15
minimum	18126	1			T1	135		T6	15		T10	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	724	1			T5	1		T9	4		T39	16
values[1]	2955	1			T2	10		T7	23		T11	3
values[2]	489	1			T3	1		T5	1		T7	1
values[3]	843	1			T9	7		T32	1		T149	1
values[4]	800	1			T4	1		T131	11		T40	15
values[5]	574	1			T4	1		T5	1		T131	2
values[6]	754	1			T14	26		T27	1		T149	1
values[7]	640	1			T131	3		T148	12		T151	1
values[8]	842	1			T9	10		T13	26		T43	15
values[9]	129	1			T3	1		T40	6		T86	26
minimum	19014	1			T1	138		T3	1		T6	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

4054

1

T7

10

T8

10

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T9	1		T144	1		T224	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	1		T39	9		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1601	1			T2	1		T7	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	11		T43	1		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T67	1		T133	3		T17	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	1		T5	1		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T35	1		T150	1		T133	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T32	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	1		T15	2		T142	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T131	1		T40	3		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T131	1		T39	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T4	1		T140	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T27	1		T16	5		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	6		T149	1		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T148	1		T151	1		T308	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T131	1		T150	1		T78	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T43	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T13	15		T25	12		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T86	13		T221	3		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T3	1		T40	6		T237	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18613	1			T1	138		T3	1		T6	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	11		T234	1		T188	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	3		T144	3		T224	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T39	7		T140	4		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T2	9		T7	1		T11	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	10		T43	15		T40	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T133	4		T17	1		T222	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T139	11		T234	9		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T150	9		T133	12		T218	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	6		T52	19		T16	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T247	10		T93	12		T278	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T131	10		T40	12		T230	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T131	1		T39	5		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T140	3		T16	10		T78	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	11		T219	2		T217	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	20		T34	1		T132	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T148	11		T21	7		T177	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T131	2		T150	14		T78	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	9		T43	14		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	11		T25	12		T195	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T86	13		T221	8		T218	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	1		T67	1		T139	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T234	7		T258	4		T272	19

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	609	1			T1	3		T9	1		T44	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T188	9		T171	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T3	1		T139	1		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T309	1		T310	12		T311	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T144	1		T224	10		T216	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	1		T8	11		T39	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T2	1		T9	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	11		T40	5		T82	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	1		T67	1		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T3	1		T5	1		T7	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T35	1		T150	1		T133	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	1		T149	1		T52	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	1		T15	2		T142	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T131	1		T40	3		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T131	1		T16	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T4	1		T140	1		T16	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T39	8		T27	1		T16	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	6		T27	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T148	1		T151	1		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T131	1		T34	2		T132	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T43	1		T139	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T3	1		T13	15		T40	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17996	1			T1	135		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T9	9		T86	13		T143	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T139	10		T312	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T310	10		T311	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T144	3		T224	10		T216	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	7		T140	4		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1073	1			T2	9		T9	3		T11	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	10		T40	9		T82	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T7	1		T133	4		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T43	15		T139	11		T78	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T150	9		T133	12		T218	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	6		T52	19		T16	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T247	10		T93	12		T278	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T131	10		T40	12		T230	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T131	1		T16	1		T147	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T140	3		T16	10		T78	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T39	5		T16	11		T219	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	20		T242	3		T302	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T148	11		T234	6		T228	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T131	2		T34	1		T132	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T43	14		T139	4		T35	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	11		T25	12		T195	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T67	1		T14	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	4		T144	4		T224	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T39	8		T140	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T2	10		T7	2		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	11		T43	16		T40	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T67	1		T133	5		T17	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	1		T5	1		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T35	1		T150	10		T133	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T9	7		T32	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	1		T15	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T131	11		T40	13		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T131	2		T39	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	1		T140	4		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T27	1		T16	14		T219	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	23		T149	1		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T148	12		T151	1		T308	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T131	3		T150	15		T78	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	10		T43	15		T139	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	12		T25	13		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T86	14		T221	9		T218	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T3	1		T40	1		T237	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18743	1			T1	138		T3	1		T6	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T8	1		T234	8		T188	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T224	9		T229	2		T21	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	8		T15	2		T79	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T38	27		T41	26		T28	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T7	10		T40	4		T82	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T133	2		T17	1		T222	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T234	13		T222	10		T280	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T133	9		T84	6		T212	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T52	12		T16	9		T303	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T142	4		T134	12		T247	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	2		T230	12		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T39	7		T16	1		T143	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T16	9		T228	19		T161	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T16	2		T217	7		T234	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T14	3		T132	12		T133	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	6		T177	1		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T221	6		T224	12		T240	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T142	16		T35	6		T223	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	14		T25	11		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T86	12		T221	2		T156	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T40	5		T237	7		T188	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T216	10		T155	2		T313	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T8	10		T188	12		T275	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	610	1			T1	3		T9	10		T44	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T188	1		T171	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T3	1		T139	11		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T309	1		T310	11		T311	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T144	4		T224	11		T216	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T8	1		T39	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T2	10		T9	4		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	11		T40	10		T82	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	2		T67	1		T133	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	1		T5	1		T7	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	1		T150	10		T133	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T9	7		T149	1		T52	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	1		T15	2		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T131	11		T40	13		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	1		T131	2		T16	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	1		T140	4		T16	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T39	6		T27	1		T16	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	23		T27	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T148	12		T151	1		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T131	3		T34	3		T132	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T43	15		T139	5		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T3	1		T13	12		T40	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18126	1			T1	135		T6	15		T10	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T86	12		T143	2		T221	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T188	8		T171	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T312	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T310	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T224	9		T216	10		T229	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	10		T39	8		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T38	27		T41	26		T28	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	10		T40	4		T82	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T133	2		T17	1		T222	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T234	13		T222	10		T314	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T133	9		T84	6		T212	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T52	12		T16	9		T303	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T142	4		T247	12		T278	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T40	2		T230	12		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	1		T134	12		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T16	9		T94	10		T97	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T39	7		T16	2		T143	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	3		T133	7		T287	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T234	7		T228	2		T260	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T132	12		T221	6		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T142	16		T35	6		T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T13	14		T40	5		T25	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23710

1

T1

138

T2

10

T3

3

auto[1]

auto[0]

4054

1

T7

10

T8

10

T13

14