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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.07 96.67 100.00 100.00 98.83 98.33 91.42


Total test records in report: 917
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T183 /workspace/coverage/default/34.adc_ctrl_filters_both.2369363010 Jul 25 06:43:01 PM PDT 24 Jul 25 06:44:45 PM PDT 24 322814855556 ps
T794 /workspace/coverage/default/30.adc_ctrl_filters_both.1103534681 Jul 25 06:42:38 PM PDT 24 Jul 25 06:44:32 PM PDT 24 189647513474 ps
T88 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.413060 Jul 25 07:13:53 PM PDT 24 Jul 25 07:13:54 PM PDT 24 562750030 ps
T57 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2227022742 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:53 PM PDT 24 437968210 ps
T110 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4233198405 Jul 25 07:13:50 PM PDT 24 Jul 25 07:13:51 PM PDT 24 600003114 ps
T795 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2939402184 Jul 25 07:14:05 PM PDT 24 Jul 25 07:14:07 PM PDT 24 451057004 ps
T58 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.620449812 Jul 25 07:13:44 PM PDT 24 Jul 25 07:13:46 PM PDT 24 885115382 ps
T128 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.847095592 Jul 25 07:13:15 PM PDT 24 Jul 25 07:13:16 PM PDT 24 854716357 ps
T796 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2036280855 Jul 25 07:14:09 PM PDT 24 Jul 25 07:14:10 PM PDT 24 403105263 ps
T797 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.265826533 Jul 25 07:13:55 PM PDT 24 Jul 25 07:13:56 PM PDT 24 321135579 ps
T798 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2777274651 Jul 25 07:13:29 PM PDT 24 Jul 25 07:13:30 PM PDT 24 396982282 ps
T49 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3341555319 Jul 25 07:13:43 PM PDT 24 Jul 25 07:13:58 PM PDT 24 4817646281 ps
T65 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2938108251 Jul 25 07:13:55 PM PDT 24 Jul 25 07:13:56 PM PDT 24 686287457 ps
T50 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4283781756 Jul 25 07:13:58 PM PDT 24 Jul 25 07:14:03 PM PDT 24 4911426049 ps
T799 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3863731392 Jul 25 07:14:07 PM PDT 24 Jul 25 07:14:08 PM PDT 24 470589405 ps
T111 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4042348993 Jul 25 07:13:30 PM PDT 24 Jul 25 07:13:32 PM PDT 24 910009638 ps
T64 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3252602082 Jul 25 07:13:53 PM PDT 24 Jul 25 07:13:55 PM PDT 24 357549780 ps
T51 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1991647615 Jul 25 07:13:14 PM PDT 24 Jul 25 07:14:35 PM PDT 24 36561074349 ps
T121 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4113408804 Jul 25 07:13:59 PM PDT 24 Jul 25 07:14:06 PM PDT 24 2010259281 ps
T74 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3213182034 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:46 PM PDT 24 494300511 ps
T800 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3332921641 Jul 25 07:14:05 PM PDT 24 Jul 25 07:14:07 PM PDT 24 372293233 ps
T89 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3335570251 Jul 25 07:14:01 PM PDT 24 Jul 25 07:14:02 PM PDT 24 400193667 ps
T68 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.907902164 Jul 25 07:13:53 PM PDT 24 Jul 25 07:13:55 PM PDT 24 378157415 ps
T801 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1463380988 Jul 25 07:14:06 PM PDT 24 Jul 25 07:14:08 PM PDT 24 515301332 ps
T122 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3586629484 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:58 PM PDT 24 2223443874 ps
T802 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3611897505 Jul 25 07:14:07 PM PDT 24 Jul 25 07:14:08 PM PDT 24 376846001 ps
T66 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2066843926 Jul 25 07:13:53 PM PDT 24 Jul 25 07:13:56 PM PDT 24 582708864 ps
T73 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3335493878 Jul 25 07:13:43 PM PDT 24 Jul 25 07:13:45 PM PDT 24 508065717 ps
T803 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3593345795 Jul 25 07:13:29 PM PDT 24 Jul 25 07:13:30 PM PDT 24 346094331 ps
T123 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.606437745 Jul 25 07:13:53 PM PDT 24 Jul 25 07:13:56 PM PDT 24 1779449784 ps
T124 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4290747418 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:50 PM PDT 24 2030777181 ps
T53 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.946510462 Jul 25 07:13:29 PM PDT 24 Jul 25 07:13:34 PM PDT 24 5190252779 ps
T804 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.273926616 Jul 25 07:14:06 PM PDT 24 Jul 25 07:14:07 PM PDT 24 317696572 ps
T69 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.611513298 Jul 25 07:13:53 PM PDT 24 Jul 25 07:13:55 PM PDT 24 1166642575 ps
T54 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2025919835 Jul 25 07:13:59 PM PDT 24 Jul 25 07:14:08 PM PDT 24 4545414676 ps
T125 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3928447718 Jul 25 07:13:58 PM PDT 24 Jul 25 07:14:03 PM PDT 24 4469701436 ps
T805 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1632627277 Jul 25 07:13:58 PM PDT 24 Jul 25 07:13:59 PM PDT 24 432600845 ps
T55 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3008243345 Jul 25 07:13:16 PM PDT 24 Jul 25 07:13:24 PM PDT 24 8676503442 ps
T806 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2970401904 Jul 25 07:14:06 PM PDT 24 Jul 25 07:14:07 PM PDT 24 397999576 ps
T807 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2598637272 Jul 25 07:14:05 PM PDT 24 Jul 25 07:14:07 PM PDT 24 488843367 ps
T126 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2609536128 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:53 PM PDT 24 585411383 ps
T71 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3931601043 Jul 25 07:13:38 PM PDT 24 Jul 25 07:13:40 PM PDT 24 327755294 ps
T72 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.74135895 Jul 25 07:13:55 PM PDT 24 Jul 25 07:13:59 PM PDT 24 498524530 ps
T808 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1686795409 Jul 25 07:13:42 PM PDT 24 Jul 25 07:13:43 PM PDT 24 748130904 ps
T75 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.761098868 Jul 25 07:13:58 PM PDT 24 Jul 25 07:14:00 PM PDT 24 1034910621 ps
T127 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4196781098 Jul 25 07:13:53 PM PDT 24 Jul 25 07:13:55 PM PDT 24 2208212991 ps
T809 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2155395247 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:48 PM PDT 24 442481354 ps
T59 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1963798479 Jul 25 07:13:44 PM PDT 24 Jul 25 07:13:56 PM PDT 24 9329398952 ps
T810 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3802306347 Jul 25 07:13:51 PM PDT 24 Jul 25 07:13:52 PM PDT 24 330084594 ps
T811 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2021408956 Jul 25 07:14:05 PM PDT 24 Jul 25 07:14:07 PM PDT 24 444303397 ps
T812 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2746651883 Jul 25 07:13:51 PM PDT 24 Jul 25 07:13:52 PM PDT 24 489899827 ps
T813 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4248571248 Jul 25 07:13:29 PM PDT 24 Jul 25 07:13:33 PM PDT 24 398196822 ps
T340 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3952452183 Jul 25 07:13:52 PM PDT 24 Jul 25 07:14:00 PM PDT 24 8550096591 ps
T112 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3333061372 Jul 25 07:13:46 PM PDT 24 Jul 25 07:13:47 PM PDT 24 458572360 ps
T814 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1730748553 Jul 25 07:13:59 PM PDT 24 Jul 25 07:14:00 PM PDT 24 401467288 ps
T815 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1500907526 Jul 25 07:13:59 PM PDT 24 Jul 25 07:14:01 PM PDT 24 439092217 ps
T816 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3576417603 Jul 25 07:13:57 PM PDT 24 Jul 25 07:13:59 PM PDT 24 487228914 ps
T817 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.688877572 Jul 25 07:13:51 PM PDT 24 Jul 25 07:14:05 PM PDT 24 2678404973 ps
T818 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3813011554 Jul 25 07:13:57 PM PDT 24 Jul 25 07:13:59 PM PDT 24 322205139 ps
T819 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3734347891 Jul 25 07:13:56 PM PDT 24 Jul 25 07:13:58 PM PDT 24 531580259 ps
T60 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3962333658 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:56 PM PDT 24 4251128554 ps
T113 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3007981243 Jul 25 07:13:46 PM PDT 24 Jul 25 07:13:48 PM PDT 24 490298810 ps
T820 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1277041120 Jul 25 07:14:07 PM PDT 24 Jul 25 07:14:09 PM PDT 24 457676661 ps
T821 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2580035775 Jul 25 07:14:09 PM PDT 24 Jul 25 07:14:10 PM PDT 24 500504874 ps
T822 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4258808510 Jul 25 07:13:59 PM PDT 24 Jul 25 07:14:01 PM PDT 24 536760708 ps
T823 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1612262720 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:57 PM PDT 24 9272967528 ps
T824 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2749687898 Jul 25 07:14:00 PM PDT 24 Jul 25 07:14:02 PM PDT 24 489794717 ps
T825 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3125900199 Jul 25 07:13:30 PM PDT 24 Jul 25 07:13:32 PM PDT 24 823554380 ps
T826 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3825458500 Jul 25 07:13:51 PM PDT 24 Jul 25 07:13:53 PM PDT 24 523265527 ps
T827 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.478196946 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:54 PM PDT 24 598084466 ps
T828 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2191382244 Jul 25 07:13:43 PM PDT 24 Jul 25 07:13:49 PM PDT 24 8949185545 ps
T829 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1471067714 Jul 25 07:14:09 PM PDT 24 Jul 25 07:14:10 PM PDT 24 310980928 ps
T830 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2513944218 Jul 25 07:13:29 PM PDT 24 Jul 25 07:13:31 PM PDT 24 2491003377 ps
T831 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.481251075 Jul 25 07:13:18 PM PDT 24 Jul 25 07:13:21 PM PDT 24 500189095 ps
T832 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2623703793 Jul 25 07:13:53 PM PDT 24 Jul 25 07:13:54 PM PDT 24 320589074 ps
T833 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1160342257 Jul 25 07:14:03 PM PDT 24 Jul 25 07:14:04 PM PDT 24 502809127 ps
T834 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1632508987 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:47 PM PDT 24 392916949 ps
T835 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.314518415 Jul 25 07:14:00 PM PDT 24 Jul 25 07:14:01 PM PDT 24 525113620 ps
T836 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2842241346 Jul 25 07:13:46 PM PDT 24 Jul 25 07:13:47 PM PDT 24 567526227 ps
T837 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1435059991 Jul 25 07:13:43 PM PDT 24 Jul 25 07:13:45 PM PDT 24 488662908 ps
T838 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.440000489 Jul 25 07:13:44 PM PDT 24 Jul 25 07:13:54 PM PDT 24 2341834284 ps
T839 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1572734599 Jul 25 07:14:05 PM PDT 24 Jul 25 07:14:07 PM PDT 24 419621890 ps
T840 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3962674514 Jul 25 07:14:03 PM PDT 24 Jul 25 07:14:08 PM PDT 24 3018448436 ps
T841 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2486595210 Jul 25 07:14:05 PM PDT 24 Jul 25 07:14:16 PM PDT 24 4368377298 ps
T842 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4236277347 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:53 PM PDT 24 526053376 ps
T843 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1520163098 Jul 25 07:13:56 PM PDT 24 Jul 25 07:13:57 PM PDT 24 464899990 ps
T844 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2224980053 Jul 25 07:14:06 PM PDT 24 Jul 25 07:14:08 PM PDT 24 520925437 ps
T845 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3287334795 Jul 25 07:14:08 PM PDT 24 Jul 25 07:14:09 PM PDT 24 329778737 ps
T846 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2694938371 Jul 25 07:13:29 PM PDT 24 Jul 25 07:13:31 PM PDT 24 915262258 ps
T847 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3693858634 Jul 25 07:13:14 PM PDT 24 Jul 25 07:13:15 PM PDT 24 536771413 ps
T848 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3211916502 Jul 25 07:14:06 PM PDT 24 Jul 25 07:14:08 PM PDT 24 362321508 ps
T849 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1684606718 Jul 25 07:13:54 PM PDT 24 Jul 25 07:13:55 PM PDT 24 435793455 ps
T850 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.324874005 Jul 25 07:14:03 PM PDT 24 Jul 25 07:14:05 PM PDT 24 413427638 ps
T851 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2033127425 Jul 25 07:13:56 PM PDT 24 Jul 25 07:13:57 PM PDT 24 368249865 ps
T852 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2446826064 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:54 PM PDT 24 533622930 ps
T853 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1998937240 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:53 PM PDT 24 396445053 ps
T114 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1122718585 Jul 25 07:13:15 PM PDT 24 Jul 25 07:13:17 PM PDT 24 766334980 ps
T115 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3384061249 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:47 PM PDT 24 438323174 ps
T854 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4004530606 Jul 25 07:13:43 PM PDT 24 Jul 25 07:13:44 PM PDT 24 522570924 ps
T855 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.281382230 Jul 25 07:14:03 PM PDT 24 Jul 25 07:14:05 PM PDT 24 399530197 ps
T856 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3497742346 Jul 25 07:13:33 PM PDT 24 Jul 25 07:13:35 PM PDT 24 525192716 ps
T857 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.881560053 Jul 25 07:13:59 PM PDT 24 Jul 25 07:14:00 PM PDT 24 345015838 ps
T858 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2812974442 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:56 PM PDT 24 4207370610 ps
T859 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4094832067 Jul 25 07:13:44 PM PDT 24 Jul 25 07:13:46 PM PDT 24 628848424 ps
T860 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.493167854 Jul 25 07:13:56 PM PDT 24 Jul 25 07:14:07 PM PDT 24 4467298783 ps
T861 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.461470553 Jul 25 07:14:06 PM PDT 24 Jul 25 07:14:07 PM PDT 24 348305550 ps
T116 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.615569429 Jul 25 07:13:53 PM PDT 24 Jul 25 07:13:54 PM PDT 24 434333401 ps
T862 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3717031799 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:48 PM PDT 24 1017123553 ps
T117 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2219361742 Jul 25 07:13:32 PM PDT 24 Jul 25 07:13:33 PM PDT 24 449017818 ps
T863 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1751055564 Jul 25 07:13:56 PM PDT 24 Jul 25 07:13:57 PM PDT 24 430411134 ps
T864 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2580055836 Jul 25 07:13:43 PM PDT 24 Jul 25 07:13:45 PM PDT 24 457447748 ps
T118 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3830814825 Jul 25 07:13:30 PM PDT 24 Jul 25 07:13:49 PM PDT 24 50797170059 ps
T865 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1783681654 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:55 PM PDT 24 858023292 ps
T866 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2822450258 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:47 PM PDT 24 641099771 ps
T867 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.531931295 Jul 25 07:14:07 PM PDT 24 Jul 25 07:14:08 PM PDT 24 539533896 ps
T868 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3872537307 Jul 25 07:14:00 PM PDT 24 Jul 25 07:14:02 PM PDT 24 793477708 ps
T869 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4265208109 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:47 PM PDT 24 458729951 ps
T870 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2051330961 Jul 25 07:14:06 PM PDT 24 Jul 25 07:14:07 PM PDT 24 439366701 ps
T871 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3886156801 Jul 25 07:13:58 PM PDT 24 Jul 25 07:14:00 PM PDT 24 405654207 ps
T872 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4024371301 Jul 25 07:13:56 PM PDT 24 Jul 25 07:14:06 PM PDT 24 2105920676 ps
T119 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3460686508 Jul 25 07:13:44 PM PDT 24 Jul 25 07:14:45 PM PDT 24 27033626982 ps
T873 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4029900712 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:51 PM PDT 24 4273036921 ps
T874 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2579130144 Jul 25 07:13:44 PM PDT 24 Jul 25 07:13:45 PM PDT 24 530606901 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1527840535 Jul 25 07:13:13 PM PDT 24 Jul 25 07:13:14 PM PDT 24 527331915 ps
T876 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3144092874 Jul 25 07:13:46 PM PDT 24 Jul 25 07:13:47 PM PDT 24 433695628 ps
T877 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2207103118 Jul 25 07:13:57 PM PDT 24 Jul 25 07:14:03 PM PDT 24 4020502774 ps
T120 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3387417242 Jul 25 07:13:43 PM PDT 24 Jul 25 07:13:48 PM PDT 24 1021797033 ps
T878 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2943491896 Jul 25 07:13:54 PM PDT 24 Jul 25 07:14:01 PM PDT 24 4279134805 ps
T879 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2906871365 Jul 25 07:13:29 PM PDT 24 Jul 25 07:13:39 PM PDT 24 4282775040 ps
T880 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3669540565 Jul 25 07:13:30 PM PDT 24 Jul 25 07:13:32 PM PDT 24 623591298 ps
T881 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2405596893 Jul 25 07:13:44 PM PDT 24 Jul 25 07:13:47 PM PDT 24 413050915 ps
T882 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2799200262 Jul 25 07:13:43 PM PDT 24 Jul 25 07:14:01 PM PDT 24 25847701862 ps
T883 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1544821384 Jul 25 07:14:09 PM PDT 24 Jul 25 07:14:11 PM PDT 24 385004601 ps
T884 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3881286716 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:50 PM PDT 24 4194864979 ps
T885 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3955031339 Jul 25 07:13:54 PM PDT 24 Jul 25 07:13:56 PM PDT 24 440607264 ps
T886 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.836460572 Jul 25 07:14:06 PM PDT 24 Jul 25 07:14:07 PM PDT 24 474747899 ps
T887 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.991920686 Jul 25 07:14:06 PM PDT 24 Jul 25 07:14:08 PM PDT 24 331922107 ps
T888 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2392399389 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:47 PM PDT 24 515065396 ps
T889 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3933868754 Jul 25 07:13:42 PM PDT 24 Jul 25 07:13:44 PM PDT 24 1835951832 ps
T890 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3243468243 Jul 25 07:13:30 PM PDT 24 Jul 25 07:13:36 PM PDT 24 1994997224 ps
T891 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1460535395 Jul 25 07:13:56 PM PDT 24 Jul 25 07:13:58 PM PDT 24 647976551 ps
T892 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.943394411 Jul 25 07:13:57 PM PDT 24 Jul 25 07:13:58 PM PDT 24 350918984 ps
T893 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3098048328 Jul 25 07:14:05 PM PDT 24 Jul 25 07:14:09 PM PDT 24 5009515882 ps
T894 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2841754633 Jul 25 07:14:03 PM PDT 24 Jul 25 07:14:08 PM PDT 24 4209588395 ps
T895 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3317310265 Jul 25 07:14:06 PM PDT 24 Jul 25 07:14:07 PM PDT 24 568309856 ps
T896 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3585842118 Jul 25 07:13:59 PM PDT 24 Jul 25 07:14:02 PM PDT 24 1409204665 ps
T897 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1445619268 Jul 25 07:13:43 PM PDT 24 Jul 25 07:13:44 PM PDT 24 377977576 ps
T898 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1259507785 Jul 25 07:13:42 PM PDT 24 Jul 25 07:13:44 PM PDT 24 529178956 ps
T899 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3354612420 Jul 25 07:13:29 PM PDT 24 Jul 25 07:14:31 PM PDT 24 26504737531 ps
T900 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2355693096 Jul 25 07:13:58 PM PDT 24 Jul 25 07:13:59 PM PDT 24 504348467 ps
T901 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2012116803 Jul 25 07:13:55 PM PDT 24 Jul 25 07:13:56 PM PDT 24 350591521 ps
T902 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1455870511 Jul 25 07:13:44 PM PDT 24 Jul 25 07:13:46 PM PDT 24 679185530 ps
T903 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2584894091 Jul 25 07:13:58 PM PDT 24 Jul 25 07:13:59 PM PDT 24 405814189 ps
T904 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.493080864 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:53 PM PDT 24 369292069 ps
T905 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.342700361 Jul 25 07:13:54 PM PDT 24 Jul 25 07:13:55 PM PDT 24 389262640 ps
T906 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3320900782 Jul 25 07:13:44 PM PDT 24 Jul 25 07:13:45 PM PDT 24 397207639 ps
T907 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3179867658 Jul 25 07:13:38 PM PDT 24 Jul 25 07:13:39 PM PDT 24 430058532 ps
T908 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1027931780 Jul 25 07:13:38 PM PDT 24 Jul 25 07:13:40 PM PDT 24 1247106052 ps
T909 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1117515397 Jul 25 07:13:54 PM PDT 24 Jul 25 07:14:06 PM PDT 24 8516597154 ps
T910 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1187015848 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:54 PM PDT 24 572560133 ps
T911 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1062510217 Jul 25 07:13:51 PM PDT 24 Jul 25 07:13:59 PM PDT 24 8159113357 ps
T912 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1437308474 Jul 25 07:13:52 PM PDT 24 Jul 25 07:13:56 PM PDT 24 4269687517 ps
T913 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1379603528 Jul 25 07:13:45 PM PDT 24 Jul 25 07:13:50 PM PDT 24 8808519221 ps
T914 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1621790890 Jul 25 07:13:51 PM PDT 24 Jul 25 07:13:56 PM PDT 24 2593127859 ps
T915 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2696594133 Jul 25 07:13:58 PM PDT 24 Jul 25 07:13:59 PM PDT 24 404989811 ps
T916 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1964289460 Jul 25 07:13:52 PM PDT 24 Jul 25 07:14:12 PM PDT 24 5216256731 ps
T917 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.185310356 Jul 25 07:13:28 PM PDT 24 Jul 25 07:13:35 PM PDT 24 4658718563 ps

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1020469268
Short name T7
Test name
Test status
Simulation time 539456471591 ps
CPU time 465.43 seconds
Started Jul 25 06:42:39 PM PDT 24
Finished Jul 25 06:50:25 PM PDT 24
Peak memory 201244 kb
Host smart-5a29e31f-afe5-4457-a568-e13ffdf4e675
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020469268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1020469268
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2255654120
Short name T1
Test name
Test status
Simulation time 87699706967 ps
CPU time 306.23 seconds
Started Jul 25 06:41:48 PM PDT 24
Finished Jul 25 06:46:54 PM PDT 24
Peak memory 201668 kb
Host smart-78ea518c-57f0-4aad-b5c1-afb03daa56f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255654120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2255654120
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1017698521
Short name T16
Test name
Test status
Simulation time 980707682227 ps
CPU time 267.21 seconds
Started Jul 25 06:41:29 PM PDT 24
Finished Jul 25 06:45:56 PM PDT 24
Peak memory 210076 kb
Host smart-b4532765-98f9-4b2b-81de-75282069d5c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017698521 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1017698521
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1198923421
Short name T9
Test name
Test status
Simulation time 501992084819 ps
CPU time 1212.21 seconds
Started Jul 25 06:44:41 PM PDT 24
Finished Jul 25 07:04:54 PM PDT 24
Peak memory 201304 kb
Host smart-4f93d0ed-9e19-40b9-a5a0-8bd4d473f33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198923421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1198923421
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3546113567
Short name T56
Test name
Test status
Simulation time 320440233403 ps
CPU time 319.32 seconds
Started Jul 25 06:43:44 PM PDT 24
Finished Jul 25 06:49:03 PM PDT 24
Peak memory 218100 kb
Host smart-bcd6f6cb-61c9-4d55-852b-4f703a178543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546113567 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3546113567
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.4064932820
Short name T40
Test name
Test status
Simulation time 537548949764 ps
CPU time 1289.66 seconds
Started Jul 25 06:44:12 PM PDT 24
Finished Jul 25 07:05:42 PM PDT 24
Peak memory 201204 kb
Host smart-5d5f091f-1b25-4307-b28b-5082fcc70f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064932820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.4064932820
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.91472321
Short name T21
Test name
Test status
Simulation time 680539416105 ps
CPU time 392.81 seconds
Started Jul 25 06:42:57 PM PDT 24
Finished Jul 25 06:49:30 PM PDT 24
Peak memory 209976 kb
Host smart-742d596b-8917-4a87-95b9-3f8389874ccd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91472321 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.91472321
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1558975187
Short name T133
Test name
Test status
Simulation time 593874049549 ps
CPU time 1340.04 seconds
Started Jul 25 06:42:01 PM PDT 24
Finished Jul 25 07:04:21 PM PDT 24
Peak memory 201244 kb
Host smart-d970197f-0860-4a59-8b4a-cbd4df796b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558975187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1558975187
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2860074489
Short name T221
Test name
Test status
Simulation time 517814706769 ps
CPU time 1264.46 seconds
Started Jul 25 06:44:18 PM PDT 24
Finished Jul 25 07:05:23 PM PDT 24
Peak memory 201228 kb
Host smart-c537a4c0-9e75-41f3-a605-4ac3f2127331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860074489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2860074489
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.117914197
Short name T139
Test name
Test status
Simulation time 481248446575 ps
CPU time 311.91 seconds
Started Jul 25 06:41:46 PM PDT 24
Finished Jul 25 06:46:58 PM PDT 24
Peak memory 201292 kb
Host smart-f01b75bf-b90e-4a66-9ca9-8859550bbbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117914197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.117914197
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2963179496
Short name T61
Test name
Test status
Simulation time 3794180614 ps
CPU time 5.25 seconds
Started Jul 25 06:40:43 PM PDT 24
Finished Jul 25 06:40:49 PM PDT 24
Peak memory 216992 kb
Host smart-e8a5e655-a914-4bf7-936d-3cf6b1064cf5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963179496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2963179496
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3458348112
Short name T150
Test name
Test status
Simulation time 498412534336 ps
CPU time 1051.39 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:58:18 PM PDT 24
Peak memory 201228 kb
Host smart-db8ef80b-88ee-491f-afe9-6c8ad0585750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458348112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3458348112
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.736268597
Short name T224
Test name
Test status
Simulation time 543193422277 ps
CPU time 360.18 seconds
Started Jul 25 06:40:42 PM PDT 24
Finished Jul 25 06:46:42 PM PDT 24
Peak memory 201188 kb
Host smart-cef04f43-3948-429d-825e-2bcb440eac5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736268597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.736268597
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2814162613
Short name T84
Test name
Test status
Simulation time 638269538896 ps
CPU time 404.53 seconds
Started Jul 25 06:41:52 PM PDT 24
Finished Jul 25 06:48:37 PM PDT 24
Peak memory 201256 kb
Host smart-086c96e1-64ce-4ae9-bd0d-668fd91bac34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814162613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2814162613
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.957244901
Short name T234
Test name
Test status
Simulation time 517794646061 ps
CPU time 1206.18 seconds
Started Jul 25 06:41:11 PM PDT 24
Finished Jul 25 07:01:17 PM PDT 24
Peak memory 201288 kb
Host smart-5c98bc94-e30d-4a31-a0ed-b3ddb635d00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957244901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.957244901
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1991647615
Short name T51
Test name
Test status
Simulation time 36561074349 ps
CPU time 80.96 seconds
Started Jul 25 07:13:14 PM PDT 24
Finished Jul 25 07:14:35 PM PDT 24
Peak memory 201796 kb
Host smart-9a822913-e8ef-45e2-ae32-29fc69dc26ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991647615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1991647615
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.10857252
Short name T222
Test name
Test status
Simulation time 328446696983 ps
CPU time 380.82 seconds
Started Jul 25 06:42:24 PM PDT 24
Finished Jul 25 06:48:45 PM PDT 24
Peak memory 201304 kb
Host smart-cb189433-c3d5-496a-92a7-0934ab1dcc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10857252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.10857252
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.620449812
Short name T58
Test name
Test status
Simulation time 885115382 ps
CPU time 2.05 seconds
Started Jul 25 07:13:44 PM PDT 24
Finished Jul 25 07:13:46 PM PDT 24
Peak memory 201832 kb
Host smart-79c3d362-6b00-489b-bbb2-2e7c429d5159
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620449812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.620449812
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1274581547
Short name T38
Test name
Test status
Simulation time 390105674402 ps
CPU time 797.62 seconds
Started Jul 25 06:40:43 PM PDT 24
Finished Jul 25 06:54:01 PM PDT 24
Peak memory 201216 kb
Host smart-0b1a9989-f38a-4c97-817a-1914f01cd17d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274581547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1274581547
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3132626513
Short name T143
Test name
Test status
Simulation time 351782622480 ps
CPU time 651.75 seconds
Started Jul 25 06:41:32 PM PDT 24
Finished Jul 25 06:52:24 PM PDT 24
Peak memory 201196 kb
Host smart-2088d44a-263f-45da-a9ed-4e62d8c0e7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132626513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3132626513
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2297174091
Short name T15
Test name
Test status
Simulation time 101625213845 ps
CPU time 219.62 seconds
Started Jul 25 06:44:26 PM PDT 24
Finished Jul 25 06:48:06 PM PDT 24
Peak memory 217488 kb
Host smart-10af9a3a-6d97-4066-8c40-7d449fd64599
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297174091 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2297174091
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2655862756
Short name T164
Test name
Test status
Simulation time 504102778121 ps
CPU time 244.63 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:45:29 PM PDT 24
Peak memory 201248 kb
Host smart-448dd7d8-e7fd-44a4-a212-8feaa163a91f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655862756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2655862756
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3789035383
Short name T155
Test name
Test status
Simulation time 500253819711 ps
CPU time 577.53 seconds
Started Jul 25 06:42:44 PM PDT 24
Finished Jul 25 06:52:22 PM PDT 24
Peak memory 210088 kb
Host smart-4d86b87f-62ee-46ea-b30f-da5aeb62766f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789035383 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3789035383
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.824845901
Short name T188
Test name
Test status
Simulation time 538567229917 ps
CPU time 335.27 seconds
Started Jul 25 06:41:53 PM PDT 24
Finished Jul 25 06:47:28 PM PDT 24
Peak memory 201248 kb
Host smart-c22bc607-ad9d-483b-9854-dbf4b2326494
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824845901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.824845901
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3314658199
Short name T186
Test name
Test status
Simulation time 553427100871 ps
CPU time 98.8 seconds
Started Jul 25 06:41:16 PM PDT 24
Finished Jul 25 06:42:55 PM PDT 24
Peak memory 201304 kb
Host smart-899afdfe-d284-41ec-9909-f5602cbd4964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314658199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3314658199
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.80393073
Short name T180
Test name
Test status
Simulation time 499674070438 ps
CPU time 104.57 seconds
Started Jul 25 06:41:20 PM PDT 24
Finished Jul 25 06:43:04 PM PDT 24
Peak memory 201228 kb
Host smart-5149367d-eee4-4aa1-b2a3-d22f637eaa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80393073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.80393073
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.458837509
Short name T273
Test name
Test status
Simulation time 170696174735 ps
CPU time 213.58 seconds
Started Jul 25 06:41:01 PM PDT 24
Finished Jul 25 06:44:34 PM PDT 24
Peak memory 201240 kb
Host smart-81c4c68a-1330-4088-9b8f-2a57cfcbe6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458837509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.458837509
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.839091386
Short name T35
Test name
Test status
Simulation time 129630711775 ps
CPU time 58.55 seconds
Started Jul 25 06:43:52 PM PDT 24
Finished Jul 25 06:44:51 PM PDT 24
Peak memory 209516 kb
Host smart-2fb55ac7-8f75-4d67-96a5-4758a0475959
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839091386 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.839091386
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3415074964
Short name T289
Test name
Test status
Simulation time 272294684228 ps
CPU time 170.77 seconds
Started Jul 25 06:41:01 PM PDT 24
Finished Jul 25 06:43:52 PM PDT 24
Peak memory 209596 kb
Host smart-3ef02101-10a6-46f1-9089-6f13f170716b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415074964 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3415074964
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.112083540
Short name T354
Test name
Test status
Simulation time 564763075 ps
CPU time 0.77 seconds
Started Jul 25 06:41:07 PM PDT 24
Finished Jul 25 06:41:08 PM PDT 24
Peak memory 201012 kb
Host smart-40a0a98d-ff57-4330-b510-a26cc60efd6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112083540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.112083540
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3008243345
Short name T55
Test name
Test status
Simulation time 8676503442 ps
CPU time 7.17 seconds
Started Jul 25 07:13:16 PM PDT 24
Finished Jul 25 07:13:24 PM PDT 24
Peak memory 201824 kb
Host smart-1a4dd444-4bf0-462c-bd13-bc06c74f727c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008243345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3008243345
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2743124864
Short name T5
Test name
Test status
Simulation time 495927310565 ps
CPU time 338.01 seconds
Started Jul 25 06:40:51 PM PDT 24
Finished Jul 25 06:46:29 PM PDT 24
Peak memory 201220 kb
Host smart-fe2fd3b2-2a62-49df-967f-00a0e9b0d9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743124864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2743124864
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4242053497
Short name T258
Test name
Test status
Simulation time 552595761793 ps
CPU time 1170.15 seconds
Started Jul 25 06:41:33 PM PDT 24
Finished Jul 25 07:01:03 PM PDT 24
Peak memory 201268 kb
Host smart-ecb1fe6d-84a9-4ef4-8803-586f9a190821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242053497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4242053497
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4048346657
Short name T177
Test name
Test status
Simulation time 341288009441 ps
CPU time 230.97 seconds
Started Jul 25 06:45:16 PM PDT 24
Finished Jul 25 06:49:07 PM PDT 24
Peak memory 201284 kb
Host smart-df28a0f7-5595-4c10-a4d2-c351cacc89b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048346657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4048346657
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3847974941
Short name T191
Test name
Test status
Simulation time 495287703165 ps
CPU time 262.63 seconds
Started Jul 25 06:45:23 PM PDT 24
Finished Jul 25 06:49:45 PM PDT 24
Peak memory 201244 kb
Host smart-42c9830d-90c0-4184-af15-0f2f263f0209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847974941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3847974941
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1778682906
Short name T271
Test name
Test status
Simulation time 320988817537 ps
CPU time 173.87 seconds
Started Jul 25 06:40:45 PM PDT 24
Finished Jul 25 06:43:39 PM PDT 24
Peak memory 201204 kb
Host smart-9b14467d-6d4a-4856-83d9-1a937056fae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778682906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1778682906
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1107318622
Short name T161
Test name
Test status
Simulation time 345245992503 ps
CPU time 862.4 seconds
Started Jul 25 06:40:59 PM PDT 24
Finished Jul 25 06:55:22 PM PDT 24
Peak memory 201236 kb
Host smart-62eceaf9-76d5-4564-be9e-103942d850f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107318622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1107318622
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1497974570
Short name T272
Test name
Test status
Simulation time 537976371035 ps
CPU time 1161.8 seconds
Started Jul 25 06:41:15 PM PDT 24
Finished Jul 25 07:00:37 PM PDT 24
Peak memory 201300 kb
Host smart-880012f6-30a4-4be5-a1be-66af93539f99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497974570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1497974570
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.176660929
Short name T278
Test name
Test status
Simulation time 370599849797 ps
CPU time 1515.93 seconds
Started Jul 25 06:41:19 PM PDT 24
Finished Jul 25 07:06:35 PM PDT 24
Peak memory 209940 kb
Host smart-270d6f27-aa4e-4248-b7bc-1cd866146cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176660929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
176660929
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2147483243
Short name T165
Test name
Test status
Simulation time 489457935566 ps
CPU time 214.48 seconds
Started Jul 25 06:42:51 PM PDT 24
Finished Jul 25 06:46:26 PM PDT 24
Peak memory 201256 kb
Host smart-4adcee55-2f5c-48d8-a2d2-0d26b33a6fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147483243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2147483243
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.873300634
Short name T25
Test name
Test status
Simulation time 177788421139 ps
CPU time 73.32 seconds
Started Jul 25 06:40:44 PM PDT 24
Finished Jul 25 06:41:57 PM PDT 24
Peak memory 201260 kb
Host smart-d6c692d0-bf3c-4a16-ab1e-6f41456a2cba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873300634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.873300634
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.4208538251
Short name T208
Test name
Test status
Simulation time 108482726319 ps
CPU time 130.06 seconds
Started Jul 25 06:41:52 PM PDT 24
Finished Jul 25 06:44:02 PM PDT 24
Peak memory 210100 kb
Host smart-1551ee6e-0477-4135-b884-2dc1da2f74dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208538251 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.4208538251
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1443816713
Short name T287
Test name
Test status
Simulation time 656120037676 ps
CPU time 401.65 seconds
Started Jul 25 06:42:08 PM PDT 24
Finished Jul 25 06:48:50 PM PDT 24
Peak memory 201256 kb
Host smart-9a9bcd76-77d6-4e9c-aa84-edb8619a211a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443816713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1443816713
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3617209703
Short name T223
Test name
Test status
Simulation time 164316669048 ps
CPU time 390.07 seconds
Started Jul 25 06:43:23 PM PDT 24
Finished Jul 25 06:49:53 PM PDT 24
Peak memory 201236 kb
Host smart-a3c30f7d-1593-4233-82f1-5e784ab1446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617209703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3617209703
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2348746108
Short name T210
Test name
Test status
Simulation time 494126622907 ps
CPU time 1156.62 seconds
Started Jul 25 06:41:23 PM PDT 24
Finished Jul 25 07:00:40 PM PDT 24
Peak memory 201208 kb
Host smart-1f273063-baf8-4de0-923d-ca5035aa1f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348746108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2348746108
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4196781098
Short name T127
Test name
Test status
Simulation time 2208212991 ps
CPU time 2.06 seconds
Started Jul 25 07:13:53 PM PDT 24
Finished Jul 25 07:13:55 PM PDT 24
Peak memory 201636 kb
Host smart-3a8bf255-da85-42a4-8f61-3e7bae823dc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196781098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.4196781098
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.481251075
Short name T831
Test name
Test status
Simulation time 500189095 ps
CPU time 3.36 seconds
Started Jul 25 07:13:18 PM PDT 24
Finished Jul 25 07:13:21 PM PDT 24
Peak memory 210016 kb
Host smart-8e313e52-e40b-4339-a1d2-dcb59b5b3425
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481251075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.481251075
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3743093705
Short name T13
Test name
Test status
Simulation time 218827219428 ps
CPU time 133.55 seconds
Started Jul 25 06:42:12 PM PDT 24
Finished Jul 25 06:44:26 PM PDT 24
Peak memory 201300 kb
Host smart-7f0b6ceb-028b-4023-96a4-09688a4ab6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743093705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3743093705
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2015545675
Short name T97
Test name
Test status
Simulation time 1682829937704 ps
CPU time 1551.66 seconds
Started Jul 25 06:42:58 PM PDT 24
Finished Jul 25 07:08:50 PM PDT 24
Peak memory 212588 kb
Host smart-50c5df2f-196a-4b99-8c1d-37ebee814262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015545675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2015545675
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1004889477
Short name T239
Test name
Test status
Simulation time 324453470499 ps
CPU time 113.27 seconds
Started Jul 25 06:43:18 PM PDT 24
Finished Jul 25 06:45:11 PM PDT 24
Peak memory 201156 kb
Host smart-b6182442-36a7-4857-a55b-2b58f2c073f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004889477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1004889477
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.412213235
Short name T310
Test name
Test status
Simulation time 380870827197 ps
CPU time 109.24 seconds
Started Jul 25 06:44:31 PM PDT 24
Finished Jul 25 06:46:21 PM PDT 24
Peak memory 201300 kb
Host smart-b3944285-f8a2-4b54-a356-cdb91a21d1ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412213235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.412213235
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2262521882
Short name T107
Test name
Test status
Simulation time 484158186652 ps
CPU time 109.1 seconds
Started Jul 25 06:41:21 PM PDT 24
Finished Jul 25 06:43:10 PM PDT 24
Peak memory 201316 kb
Host smart-eccd70ef-fe4e-4960-83b7-f21c42e05f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262521882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2262521882
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2738471272
Short name T265
Test name
Test status
Simulation time 527887396645 ps
CPU time 301.25 seconds
Started Jul 25 06:42:39 PM PDT 24
Finished Jul 25 06:47:41 PM PDT 24
Peak memory 201284 kb
Host smart-1777b5c4-08e9-4852-8eba-cc5e6b0766e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738471272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2738471272
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1120569416
Short name T293
Test name
Test status
Simulation time 330124154643 ps
CPU time 392.58 seconds
Started Jul 25 06:40:43 PM PDT 24
Finished Jul 25 06:47:16 PM PDT 24
Peak memory 201248 kb
Host smart-80b532a4-6818-4f7a-aefa-b8c08b7e6d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120569416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1120569416
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1536060046
Short name T176
Test name
Test status
Simulation time 165268849629 ps
CPU time 25.63 seconds
Started Jul 25 06:41:07 PM PDT 24
Finished Jul 25 06:41:32 PM PDT 24
Peak memory 201208 kb
Host smart-a6139f82-6d1e-4b12-b1d1-27adbc63b627
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536060046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1536060046
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2401782055
Short name T247
Test name
Test status
Simulation time 330943295085 ps
CPU time 378.06 seconds
Started Jul 25 06:41:08 PM PDT 24
Finished Jul 25 06:47:26 PM PDT 24
Peak memory 201228 kb
Host smart-2e109d0d-2478-4f47-8d63-1002d6ae24f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401782055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2401782055
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3955773360
Short name T333
Test name
Test status
Simulation time 106659948334 ps
CPU time 96.24 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 06:43:03 PM PDT 24
Peak memory 209576 kb
Host smart-be7abce5-95d0-4738-8fbd-dbede4b8ed52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955773360 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3955773360
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.430276819
Short name T327
Test name
Test status
Simulation time 368847401954 ps
CPU time 170.6 seconds
Started Jul 25 06:41:26 PM PDT 24
Finished Jul 25 06:44:17 PM PDT 24
Peak memory 201300 kb
Host smart-3b4c32b3-7705-41c4-a233-d24d4910b955
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430276819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.430276819
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.608853877
Short name T168
Test name
Test status
Simulation time 352225321333 ps
CPU time 50.2 seconds
Started Jul 25 06:41:42 PM PDT 24
Finished Jul 25 06:42:33 PM PDT 24
Peak memory 201288 kb
Host smart-074d9468-157c-44ef-bc74-dcc1ec859dc3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608853877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.608853877
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2031469050
Short name T266
Test name
Test status
Simulation time 1073418813923 ps
CPU time 255.89 seconds
Started Jul 25 06:43:16 PM PDT 24
Finished Jul 25 06:47:32 PM PDT 24
Peak memory 210072 kb
Host smart-786af576-5c05-4053-98a9-5c301b485ef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031469050 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2031469050
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1236505065
Short name T301
Test name
Test status
Simulation time 4261944516433 ps
CPU time 6798.53 seconds
Started Jul 25 06:44:46 PM PDT 24
Finished Jul 25 08:38:06 PM PDT 24
Peak memory 209844 kb
Host smart-6be950a9-13cc-4722-a077-ef03d981e18b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236505065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1236505065
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3110885258
Short name T285
Test name
Test status
Simulation time 175204414769 ps
CPU time 108.56 seconds
Started Jul 25 06:42:00 PM PDT 24
Finished Jul 25 06:43:48 PM PDT 24
Peak memory 201220 kb
Host smart-6b3c54a4-f7ed-40d8-b5c9-99e534414910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110885258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3110885258
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3182067195
Short name T205
Test name
Test status
Simulation time 348687576724 ps
CPU time 1349.96 seconds
Started Jul 25 06:42:14 PM PDT 24
Finished Jul 25 07:04:44 PM PDT 24
Peak memory 209904 kb
Host smart-997a1f60-48f5-4edc-9a76-9e5d943bba0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182067195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3182067195
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1620925981
Short name T330
Test name
Test status
Simulation time 464437460433 ps
CPU time 866.48 seconds
Started Jul 25 06:43:50 PM PDT 24
Finished Jul 25 06:58:17 PM PDT 24
Peak memory 201676 kb
Host smart-d68d3187-7c24-4777-8690-3ab0d55f9975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620925981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1620925981
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3461948462
Short name T282
Test name
Test status
Simulation time 491726446629 ps
CPU time 1080.09 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:59:01 PM PDT 24
Peak memory 201308 kb
Host smart-df963d40-50bb-409d-92ef-3bd360f82eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461948462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3461948462
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.645611036
Short name T202
Test name
Test status
Simulation time 85204459425 ps
CPU time 427.81 seconds
Started Jul 25 06:40:43 PM PDT 24
Finished Jul 25 06:47:51 PM PDT 24
Peak memory 201620 kb
Host smart-7233e81e-05d5-459b-a547-8dc7e41e6287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645611036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.645611036
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2897821555
Short name T197
Test name
Test status
Simulation time 76927425103 ps
CPU time 223.36 seconds
Started Jul 25 06:41:18 PM PDT 24
Finished Jul 25 06:45:01 PM PDT 24
Peak memory 217332 kb
Host smart-f27d7329-a83c-4917-ab54-c78aa38784b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897821555 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2897821555
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2085805814
Short name T290
Test name
Test status
Simulation time 620804821613 ps
CPU time 1442.58 seconds
Started Jul 25 06:42:04 PM PDT 24
Finished Jul 25 07:06:07 PM PDT 24
Peak memory 201204 kb
Host smart-5eb69fd6-35c6-447c-bd40-8b194535b015
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085805814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2085805814
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3321280475
Short name T23
Test name
Test status
Simulation time 115374213113 ps
CPU time 276.38 seconds
Started Jul 25 06:42:06 PM PDT 24
Finished Jul 25 06:46:43 PM PDT 24
Peak memory 209980 kb
Host smart-2a7e4a5a-9f39-4df4-a860-5a5d6b408357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321280475 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3321280475
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2645804898
Short name T32
Test name
Test status
Simulation time 496398990798 ps
CPU time 1103.72 seconds
Started Jul 25 06:40:48 PM PDT 24
Finished Jul 25 06:59:12 PM PDT 24
Peak memory 201296 kb
Host smart-25011f8e-28f0-41ff-980a-4ab1edb9a582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645804898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2645804898
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3908865325
Short name T211
Test name
Test status
Simulation time 272899260887 ps
CPU time 147.11 seconds
Started Jul 25 06:43:57 PM PDT 24
Finished Jul 25 06:46:24 PM PDT 24
Peak memory 209680 kb
Host smart-c48f9075-dd4e-4a5d-b4b1-3f8b1a477292
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908865325 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3908865325
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.703471605
Short name T232
Test name
Test status
Simulation time 281384203085 ps
CPU time 319.71 seconds
Started Jul 25 06:44:33 PM PDT 24
Finished Jul 25 06:49:52 PM PDT 24
Peak memory 201232 kb
Host smart-d05d0296-0a22-4ac7-9cab-6c28d0a9def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703471605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.703471605
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1834114405
Short name T146
Test name
Test status
Simulation time 163895626335 ps
CPU time 305.04 seconds
Started Jul 25 06:45:05 PM PDT 24
Finished Jul 25 06:50:10 PM PDT 24
Peak memory 201240 kb
Host smart-c47645f9-08e7-448f-9aac-f26d84450468
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834114405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1834114405
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2025919835
Short name T54
Test name
Test status
Simulation time 4545414676 ps
CPU time 9.19 seconds
Started Jul 25 07:13:59 PM PDT 24
Finished Jul 25 07:14:08 PM PDT 24
Peak memory 201836 kb
Host smart-c33a1851-359f-492e-84ce-b02e2bb212eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025919835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2025919835
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2485948310
Short name T259
Test name
Test status
Simulation time 710310315651 ps
CPU time 440.04 seconds
Started Jul 25 06:41:08 PM PDT 24
Finished Jul 25 06:48:28 PM PDT 24
Peak memory 201292 kb
Host smart-eca2fe74-3795-4083-b1ad-2ce3abe25ebd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485948310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2485948310
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.256256974
Short name T298
Test name
Test status
Simulation time 362593702416 ps
CPU time 227.15 seconds
Started Jul 25 06:40:48 PM PDT 24
Finished Jul 25 06:44:35 PM PDT 24
Peak memory 201228 kb
Host smart-c1783cb5-69da-44e9-83b3-b88d7790edd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256256974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.256256974
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3924306173
Short name T291
Test name
Test status
Simulation time 322831410748 ps
CPU time 792.92 seconds
Started Jul 25 06:41:48 PM PDT 24
Finished Jul 25 06:55:01 PM PDT 24
Peak memory 201260 kb
Host smart-cf5350cc-8041-4d9d-9f2d-78efa95faf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924306173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3924306173
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2529846269
Short name T277
Test name
Test status
Simulation time 448724986062 ps
CPU time 1285.85 seconds
Started Jul 25 06:42:46 PM PDT 24
Finished Jul 25 07:04:12 PM PDT 24
Peak memory 201684 kb
Host smart-f4b8b866-e8db-46ac-8eb3-be76fe72a0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529846269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2529846269
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1233223692
Short name T263
Test name
Test status
Simulation time 177686776841 ps
CPU time 161.17 seconds
Started Jul 25 06:40:48 PM PDT 24
Finished Jul 25 06:43:29 PM PDT 24
Peak memory 201248 kb
Host smart-d52efada-6464-4f26-92bb-ea1a3706f0aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233223692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1233223692
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.169369481
Short name T286
Test name
Test status
Simulation time 183517464537 ps
CPU time 20.14 seconds
Started Jul 25 06:44:13 PM PDT 24
Finished Jul 25 06:44:33 PM PDT 24
Peak memory 201324 kb
Host smart-7ba78ac8-a5d3-4dd7-b75f-b591ca5d2f2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169369481 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.169369481
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1035248029
Short name T312
Test name
Test status
Simulation time 524163968748 ps
CPU time 287.76 seconds
Started Jul 25 06:45:01 PM PDT 24
Finished Jul 25 06:49:49 PM PDT 24
Peak memory 201240 kb
Host smart-025b5260-d92d-4a40-9c3a-0fd0909e3dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035248029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1035248029
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3242214524
Short name T206
Test name
Test status
Simulation time 242421317885 ps
CPU time 747.8 seconds
Started Jul 25 06:45:06 PM PDT 24
Finished Jul 25 06:57:35 PM PDT 24
Peak memory 201668 kb
Host smart-03ac93b3-0966-4540-8e16-f653fbb96d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242214524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3242214524
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.101004414
Short name T337
Test name
Test status
Simulation time 539354694567 ps
CPU time 1140.31 seconds
Started Jul 25 06:40:53 PM PDT 24
Finished Jul 25 06:59:54 PM PDT 24
Peak memory 201288 kb
Host smart-f80a2212-e97e-4515-a99e-53a3ffd6eb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101004414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.101004414
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1122718585
Short name T114
Test name
Test status
Simulation time 766334980 ps
CPU time 1.98 seconds
Started Jul 25 07:13:15 PM PDT 24
Finished Jul 25 07:13:17 PM PDT 24
Peak memory 201696 kb
Host smart-53bd872e-83f8-445b-89b4-e62997ff33ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122718585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1122718585
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.847095592
Short name T128
Test name
Test status
Simulation time 854716357 ps
CPU time 1.2 seconds
Started Jul 25 07:13:15 PM PDT 24
Finished Jul 25 07:13:16 PM PDT 24
Peak memory 201492 kb
Host smart-f5f64cef-f9a6-4f28-b8e0-e95aa43f6ce4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847095592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.847095592
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3179867658
Short name T907
Test name
Test status
Simulation time 430058532 ps
CPU time 1.06 seconds
Started Jul 25 07:13:38 PM PDT 24
Finished Jul 25 07:13:39 PM PDT 24
Peak memory 201560 kb
Host smart-d0626530-ddde-4aa3-8176-4626f63786e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179867658 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3179867658
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1527840535
Short name T875
Test name
Test status
Simulation time 527331915 ps
CPU time 1.23 seconds
Started Jul 25 07:13:13 PM PDT 24
Finished Jul 25 07:13:14 PM PDT 24
Peak memory 201460 kb
Host smart-58443055-4ade-4cea-ae4a-658e9ef3a465
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527840535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1527840535
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3693858634
Short name T847
Test name
Test status
Simulation time 536771413 ps
CPU time 0.91 seconds
Started Jul 25 07:13:14 PM PDT 24
Finished Jul 25 07:13:15 PM PDT 24
Peak memory 201468 kb
Host smart-ee309a2f-3028-4523-a78b-bb77e81176f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693858634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3693858634
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2513944218
Short name T830
Test name
Test status
Simulation time 2491003377 ps
CPU time 1.81 seconds
Started Jul 25 07:13:29 PM PDT 24
Finished Jul 25 07:13:31 PM PDT 24
Peak memory 201588 kb
Host smart-52d9d60a-0841-4243-aa5a-31a8ec438791
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513944218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2513944218
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4042348993
Short name T111
Test name
Test status
Simulation time 910009638 ps
CPU time 2.14 seconds
Started Jul 25 07:13:30 PM PDT 24
Finished Jul 25 07:13:32 PM PDT 24
Peak memory 201672 kb
Host smart-09f9ba7f-0494-4382-9c26-cdad356f72bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042348993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4042348993
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3830814825
Short name T118
Test name
Test status
Simulation time 50797170059 ps
CPU time 18.97 seconds
Started Jul 25 07:13:30 PM PDT 24
Finished Jul 25 07:13:49 PM PDT 24
Peak memory 201732 kb
Host smart-a0427a94-8eaf-46e3-afd6-3a5841b17e93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830814825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3830814825
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2694938371
Short name T846
Test name
Test status
Simulation time 915262258 ps
CPU time 1.65 seconds
Started Jul 25 07:13:29 PM PDT 24
Finished Jul 25 07:13:31 PM PDT 24
Peak memory 201448 kb
Host smart-cfb70908-f946-4b5f-9399-2b59f12b2cd7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694938371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2694938371
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3669540565
Short name T880
Test name
Test status
Simulation time 623591298 ps
CPU time 1.42 seconds
Started Jul 25 07:13:30 PM PDT 24
Finished Jul 25 07:13:32 PM PDT 24
Peak memory 211420 kb
Host smart-bd40a0b5-7834-4f34-a879-37eb9525c053
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669540565 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3669540565
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2219361742
Short name T117
Test name
Test status
Simulation time 449017818 ps
CPU time 1.03 seconds
Started Jul 25 07:13:32 PM PDT 24
Finished Jul 25 07:13:33 PM PDT 24
Peak memory 201456 kb
Host smart-47ec5ddb-68a1-4149-968f-c3096cbded65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219361742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2219361742
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2777274651
Short name T798
Test name
Test status
Simulation time 396982282 ps
CPU time 0.78 seconds
Started Jul 25 07:13:29 PM PDT 24
Finished Jul 25 07:13:30 PM PDT 24
Peak memory 201480 kb
Host smart-8f9a5551-2234-46f1-b392-ea32a5de50a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777274651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2777274651
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3243468243
Short name T890
Test name
Test status
Simulation time 1994997224 ps
CPU time 5.22 seconds
Started Jul 25 07:13:30 PM PDT 24
Finished Jul 25 07:13:36 PM PDT 24
Peak memory 201556 kb
Host smart-e786bea9-5004-4ccc-8b4f-52e2cfb057af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243468243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3243468243
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4248571248
Short name T813
Test name
Test status
Simulation time 398196822 ps
CPU time 3.52 seconds
Started Jul 25 07:13:29 PM PDT 24
Finished Jul 25 07:13:33 PM PDT 24
Peak memory 201840 kb
Host smart-2da82469-ece8-483a-b268-10a45bcb4e23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248571248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.4248571248
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2906871365
Short name T879
Test name
Test status
Simulation time 4282775040 ps
CPU time 10.31 seconds
Started Jul 25 07:13:29 PM PDT 24
Finished Jul 25 07:13:39 PM PDT 24
Peak memory 201824 kb
Host smart-0c137e6f-371a-42e0-9565-0eb24dcdfd35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906871365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2906871365
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1160342257
Short name T833
Test name
Test status
Simulation time 502809127 ps
CPU time 0.96 seconds
Started Jul 25 07:14:03 PM PDT 24
Finished Jul 25 07:14:04 PM PDT 24
Peak memory 201588 kb
Host smart-94823ae2-f91e-4567-9a89-b5e756fe30c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160342257 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1160342257
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.615569429
Short name T116
Test name
Test status
Simulation time 434333401 ps
CPU time 0.95 seconds
Started Jul 25 07:13:53 PM PDT 24
Finished Jul 25 07:13:54 PM PDT 24
Peak memory 201476 kb
Host smart-e96b82ae-c54c-437e-9793-4d7f66ccab3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615569429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.615569429
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2033127425
Short name T851
Test name
Test status
Simulation time 368249865 ps
CPU time 0.71 seconds
Started Jul 25 07:13:56 PM PDT 24
Finished Jul 25 07:13:57 PM PDT 24
Peak memory 201440 kb
Host smart-c6659159-38d6-4edf-8a9d-77f5a5de4f2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033127425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2033127425
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.688877572
Short name T817
Test name
Test status
Simulation time 2678404973 ps
CPU time 13.12 seconds
Started Jul 25 07:13:51 PM PDT 24
Finished Jul 25 07:14:05 PM PDT 24
Peak memory 201624 kb
Host smart-6b1a408c-d366-4f5b-8611-3c2309371f3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688877572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.688877572
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.478196946
Short name T827
Test name
Test status
Simulation time 598084466 ps
CPU time 1.98 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:54 PM PDT 24
Peak memory 210000 kb
Host smart-a5ed3b3b-ef29-40fa-9c52-87f0581f6a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478196946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.478196946
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3952452183
Short name T340
Test name
Test status
Simulation time 8550096591 ps
CPU time 7.36 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:14:00 PM PDT 24
Peak memory 201832 kb
Host smart-f76859f1-0ad4-40ac-bf7d-17e6b731f182
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952452183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3952452183
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2938108251
Short name T65
Test name
Test status
Simulation time 686287457 ps
CPU time 1.3 seconds
Started Jul 25 07:13:55 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 201560 kb
Host smart-fde0e6c2-ed7e-4c90-aa04-0bb21247dd79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938108251 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2938108251
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1187015848
Short name T910
Test name
Test status
Simulation time 572560133 ps
CPU time 2 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:54 PM PDT 24
Peak memory 201460 kb
Host smart-60b12659-8ec8-4974-b139-dbcec8996c2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187015848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1187015848
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3802306347
Short name T810
Test name
Test status
Simulation time 330084594 ps
CPU time 1.44 seconds
Started Jul 25 07:13:51 PM PDT 24
Finished Jul 25 07:13:52 PM PDT 24
Peak memory 201484 kb
Host smart-4836d9e5-dcb8-4f0b-b854-044df2645578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802306347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3802306347
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2446826064
Short name T852
Test name
Test status
Simulation time 533622930 ps
CPU time 1.61 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:54 PM PDT 24
Peak memory 201840 kb
Host smart-128d93b7-2912-42ef-8156-5e8c9fefb0c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446826064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2446826064
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1437308474
Short name T912
Test name
Test status
Simulation time 4269687517 ps
CPU time 3.91 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 201764 kb
Host smart-77da35d5-774c-469a-bb6a-61a9ea13e82e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437308474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1437308474
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2066843926
Short name T66
Test name
Test status
Simulation time 582708864 ps
CPU time 2.1 seconds
Started Jul 25 07:13:53 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 201568 kb
Host smart-d8886a01-82b8-40a5-b2d1-76d3b80ff1f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066843926 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2066843926
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.493080864
Short name T904
Test name
Test status
Simulation time 369292069 ps
CPU time 1.71 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:53 PM PDT 24
Peak memory 201444 kb
Host smart-3be888d4-eeeb-46bb-bfc0-422f50e3dc7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493080864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.493080864
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2746651883
Short name T812
Test name
Test status
Simulation time 489899827 ps
CPU time 0.91 seconds
Started Jul 25 07:13:51 PM PDT 24
Finished Jul 25 07:13:52 PM PDT 24
Peak memory 201480 kb
Host smart-952561d4-0598-4700-9e80-da8be2e2bcff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746651883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2746651883
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4024371301
Short name T872
Test name
Test status
Simulation time 2105920676 ps
CPU time 10.09 seconds
Started Jul 25 07:13:56 PM PDT 24
Finished Jul 25 07:14:06 PM PDT 24
Peak memory 201520 kb
Host smart-211117be-9e01-47d3-87b1-6b17f5311234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024371301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.4024371301
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1460535395
Short name T891
Test name
Test status
Simulation time 647976551 ps
CPU time 1.66 seconds
Started Jul 25 07:13:56 PM PDT 24
Finished Jul 25 07:13:58 PM PDT 24
Peak memory 201804 kb
Host smart-9bcc2da5-76e6-45e8-939c-203ccea8c77d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460535395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1460535395
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1062510217
Short name T911
Test name
Test status
Simulation time 8159113357 ps
CPU time 7.01 seconds
Started Jul 25 07:13:51 PM PDT 24
Finished Jul 25 07:13:59 PM PDT 24
Peak memory 201836 kb
Host smart-b25d43c7-5d77-4d78-a8e6-ad50c7e73d17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062510217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1062510217
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.281382230
Short name T855
Test name
Test status
Simulation time 399530197 ps
CPU time 1.51 seconds
Started Jul 25 07:14:03 PM PDT 24
Finished Jul 25 07:14:05 PM PDT 24
Peak memory 209444 kb
Host smart-874e08fb-cd11-4b78-abce-4c9c5b37c6ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281382230 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.281382230
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.342700361
Short name T905
Test name
Test status
Simulation time 389262640 ps
CPU time 0.95 seconds
Started Jul 25 07:13:54 PM PDT 24
Finished Jul 25 07:13:55 PM PDT 24
Peak memory 201444 kb
Host smart-9c7d84cd-df67-49fe-ae9e-5a2e6e8caec3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342700361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.342700361
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.265826533
Short name T797
Test name
Test status
Simulation time 321135579 ps
CPU time 0.85 seconds
Started Jul 25 07:13:55 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 201484 kb
Host smart-37f73f20-5f6d-44c8-bb97-0e8dcda44270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265826533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.265826533
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.606437745
Short name T123
Test name
Test status
Simulation time 1779449784 ps
CPU time 2.65 seconds
Started Jul 25 07:13:53 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 201512 kb
Host smart-43d71d8c-8cab-4b07-9b01-1ffb2bb5a2c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606437745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.606437745
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.611513298
Short name T69
Test name
Test status
Simulation time 1166642575 ps
CPU time 2.28 seconds
Started Jul 25 07:13:53 PM PDT 24
Finished Jul 25 07:13:55 PM PDT 24
Peak memory 201864 kb
Host smart-0e92db85-8be7-4ccf-b8ed-975410911abb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611513298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.611513298
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3962333658
Short name T60
Test name
Test status
Simulation time 4251128554 ps
CPU time 4.23 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 201764 kb
Host smart-218e7c7c-0140-49d1-a112-4e1951a7c1e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962333658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3962333658
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2227022742
Short name T57
Test name
Test status
Simulation time 437968210 ps
CPU time 1.01 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:53 PM PDT 24
Peak memory 201612 kb
Host smart-6bb686f4-be84-4274-af92-609138b005d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227022742 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2227022742
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2012116803
Short name T901
Test name
Test status
Simulation time 350591521 ps
CPU time 0.85 seconds
Started Jul 25 07:13:55 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 201452 kb
Host smart-0bca07be-5478-4d1a-ae58-63b23250244a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012116803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2012116803
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2623703793
Short name T832
Test name
Test status
Simulation time 320589074 ps
CPU time 1.39 seconds
Started Jul 25 07:13:53 PM PDT 24
Finished Jul 25 07:13:54 PM PDT 24
Peak memory 201456 kb
Host smart-86e31e1e-5dd7-4149-ba0d-43b59736b900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623703793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2623703793
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3962674514
Short name T840
Test name
Test status
Simulation time 3018448436 ps
CPU time 4.33 seconds
Started Jul 25 07:14:03 PM PDT 24
Finished Jul 25 07:14:08 PM PDT 24
Peak memory 200704 kb
Host smart-9a4eeb01-3398-47f9-9d86-7510b9dd8089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962674514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3962674514
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3252602082
Short name T64
Test name
Test status
Simulation time 357549780 ps
CPU time 2.29 seconds
Started Jul 25 07:13:53 PM PDT 24
Finished Jul 25 07:13:55 PM PDT 24
Peak memory 201760 kb
Host smart-b48c70ff-9901-4ba7-9ea3-04c0807b50dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252602082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3252602082
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2841754633
Short name T894
Test name
Test status
Simulation time 4209588395 ps
CPU time 4.29 seconds
Started Jul 25 07:14:03 PM PDT 24
Finished Jul 25 07:14:08 PM PDT 24
Peak memory 201812 kb
Host smart-e443e5be-6ec9-4739-bf9e-ade4055a4095
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841754633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2841754633
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.413060
Short name T88
Test name
Test status
Simulation time 562750030 ps
CPU time 1.14 seconds
Started Jul 25 07:13:53 PM PDT 24
Finished Jul 25 07:13:54 PM PDT 24
Peak memory 201556 kb
Host smart-3fa72b04-5b96-4e5e-8826-5e34f1ec60d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413060 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.413060
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3825458500
Short name T826
Test name
Test status
Simulation time 523265527 ps
CPU time 0.93 seconds
Started Jul 25 07:13:51 PM PDT 24
Finished Jul 25 07:13:53 PM PDT 24
Peak memory 201540 kb
Host smart-d55e321e-3a0a-4a48-8091-98b722ab4b4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825458500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3825458500
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3955031339
Short name T885
Test name
Test status
Simulation time 440607264 ps
CPU time 1.72 seconds
Started Jul 25 07:13:54 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 201452 kb
Host smart-5ca6ff38-3bf3-45d8-82ab-0a5327a1d1ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955031339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3955031339
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1964289460
Short name T916
Test name
Test status
Simulation time 5216256731 ps
CPU time 19.95 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:14:12 PM PDT 24
Peak memory 201808 kb
Host smart-dff227b3-fabc-432d-b711-7c3a0b6b6d90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964289460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1964289460
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.907902164
Short name T68
Test name
Test status
Simulation time 378157415 ps
CPU time 2.13 seconds
Started Jul 25 07:13:53 PM PDT 24
Finished Jul 25 07:13:55 PM PDT 24
Peak memory 201824 kb
Host smart-164acfa4-d400-426e-81a2-a4168a0e8ea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907902164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.907902164
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2943491896
Short name T878
Test name
Test status
Simulation time 4279134805 ps
CPU time 6.75 seconds
Started Jul 25 07:13:54 PM PDT 24
Finished Jul 25 07:14:01 PM PDT 24
Peak memory 201732 kb
Host smart-a9a9482f-bde6-44a4-a142-c11264898c3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943491896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2943491896
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1572734599
Short name T839
Test name
Test status
Simulation time 419621890 ps
CPU time 1.35 seconds
Started Jul 25 07:14:05 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201812 kb
Host smart-f781edb1-9ef6-4ca5-977c-9225047f9fc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572734599 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1572734599
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3576417603
Short name T816
Test name
Test status
Simulation time 487228914 ps
CPU time 1.94 seconds
Started Jul 25 07:13:57 PM PDT 24
Finished Jul 25 07:13:59 PM PDT 24
Peak memory 201460 kb
Host smart-300a9d0d-c118-4848-9c47-8a68dfff3ec6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576417603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3576417603
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1632627277
Short name T805
Test name
Test status
Simulation time 432600845 ps
CPU time 0.82 seconds
Started Jul 25 07:13:58 PM PDT 24
Finished Jul 25 07:13:59 PM PDT 24
Peak memory 201472 kb
Host smart-22c8cf36-017b-4d0e-a6ee-8cd2855faf32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632627277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1632627277
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3098048328
Short name T893
Test name
Test status
Simulation time 5009515882 ps
CPU time 3.79 seconds
Started Jul 25 07:14:05 PM PDT 24
Finished Jul 25 07:14:09 PM PDT 24
Peak memory 201748 kb
Host smart-e40f6596-66d0-4c2e-8bb2-529e88593b8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098048328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3098048328
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.74135895
Short name T72
Test name
Test status
Simulation time 498524530 ps
CPU time 3.49 seconds
Started Jul 25 07:13:55 PM PDT 24
Finished Jul 25 07:13:59 PM PDT 24
Peak memory 211040 kb
Host smart-9ec8e52c-0e55-4b51-b134-dcec7d5dbebe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74135895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.74135895
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.493167854
Short name T860
Test name
Test status
Simulation time 4467298783 ps
CPU time 10.84 seconds
Started Jul 25 07:13:56 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201700 kb
Host smart-59654ff9-bd3d-4360-8280-3a1058e7d2e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493167854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.493167854
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.991920686
Short name T887
Test name
Test status
Simulation time 331922107 ps
CPU time 1.4 seconds
Started Jul 25 07:14:06 PM PDT 24
Finished Jul 25 07:14:08 PM PDT 24
Peak memory 201552 kb
Host smart-40744a80-f089-4fb8-93bd-f5260d4793ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991920686 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.991920686
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4258808510
Short name T822
Test name
Test status
Simulation time 536760708 ps
CPU time 1.39 seconds
Started Jul 25 07:13:59 PM PDT 24
Finished Jul 25 07:14:01 PM PDT 24
Peak memory 201440 kb
Host smart-286acc48-4d0b-457d-905f-72e1777b7053
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258808510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.4258808510
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3734347891
Short name T819
Test name
Test status
Simulation time 531580259 ps
CPU time 1.54 seconds
Started Jul 25 07:13:56 PM PDT 24
Finished Jul 25 07:13:58 PM PDT 24
Peak memory 201504 kb
Host smart-6b2b524e-cd84-40be-8d79-e7d4a2f26a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734347891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3734347891
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4113408804
Short name T121
Test name
Test status
Simulation time 2010259281 ps
CPU time 6.27 seconds
Started Jul 25 07:13:59 PM PDT 24
Finished Jul 25 07:14:06 PM PDT 24
Peak memory 201488 kb
Host smart-7314b783-3c4d-410a-9a15-94989f83f8ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113408804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.4113408804
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3872537307
Short name T868
Test name
Test status
Simulation time 793477708 ps
CPU time 1.87 seconds
Started Jul 25 07:14:00 PM PDT 24
Finished Jul 25 07:14:02 PM PDT 24
Peak memory 201800 kb
Host smart-563c3fa3-5d9c-440f-9537-9b688677e4ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872537307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3872537307
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2207103118
Short name T877
Test name
Test status
Simulation time 4020502774 ps
CPU time 5.09 seconds
Started Jul 25 07:13:57 PM PDT 24
Finished Jul 25 07:14:03 PM PDT 24
Peak memory 201804 kb
Host smart-75d539d5-d66f-4651-81ea-9fcf8ca5cc28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207103118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2207103118
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3335570251
Short name T89
Test name
Test status
Simulation time 400193667 ps
CPU time 1.19 seconds
Started Jul 25 07:14:01 PM PDT 24
Finished Jul 25 07:14:02 PM PDT 24
Peak memory 201616 kb
Host smart-812f061f-cb8b-43fd-9d6e-6a83ff33bd02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335570251 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3335570251
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2584894091
Short name T903
Test name
Test status
Simulation time 405814189 ps
CPU time 1.03 seconds
Started Jul 25 07:13:58 PM PDT 24
Finished Jul 25 07:13:59 PM PDT 24
Peak memory 201540 kb
Host smart-b50d5826-9798-4c19-b159-c12f6c753524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584894091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2584894091
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2355693096
Short name T900
Test name
Test status
Simulation time 504348467 ps
CPU time 1.18 seconds
Started Jul 25 07:13:58 PM PDT 24
Finished Jul 25 07:13:59 PM PDT 24
Peak memory 201464 kb
Host smart-500fa3fc-5d5c-4f65-8b5a-2322d275a7eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355693096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2355693096
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3928447718
Short name T125
Test name
Test status
Simulation time 4469701436 ps
CPU time 5.52 seconds
Started Jul 25 07:13:58 PM PDT 24
Finished Jul 25 07:14:03 PM PDT 24
Peak memory 201796 kb
Host smart-2d8a8cff-b92e-40e2-bf01-a844faafd8d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928447718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3928447718
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3585842118
Short name T896
Test name
Test status
Simulation time 1409204665 ps
CPU time 2.89 seconds
Started Jul 25 07:13:59 PM PDT 24
Finished Jul 25 07:14:02 PM PDT 24
Peak memory 209972 kb
Host smart-7919ce75-dde4-4fb3-99c7-a10fd733d249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585842118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3585842118
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2486595210
Short name T841
Test name
Test status
Simulation time 4368377298 ps
CPU time 11.45 seconds
Started Jul 25 07:14:05 PM PDT 24
Finished Jul 25 07:14:16 PM PDT 24
Peak memory 201748 kb
Host smart-d375564b-8149-4580-84fc-7c87c3d4d828
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486595210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2486595210
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3886156801
Short name T871
Test name
Test status
Simulation time 405654207 ps
CPU time 2.07 seconds
Started Jul 25 07:13:58 PM PDT 24
Finished Jul 25 07:14:00 PM PDT 24
Peak memory 201676 kb
Host smart-759723f2-516e-4e14-a5b8-04d3c2a0ae63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886156801 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3886156801
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2021408956
Short name T811
Test name
Test status
Simulation time 444303397 ps
CPU time 1.72 seconds
Started Jul 25 07:14:05 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201428 kb
Host smart-a6767602-748d-412c-b303-fe7c7e02c26d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021408956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2021408956
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.881560053
Short name T857
Test name
Test status
Simulation time 345015838 ps
CPU time 0.82 seconds
Started Jul 25 07:13:59 PM PDT 24
Finished Jul 25 07:14:00 PM PDT 24
Peak memory 201444 kb
Host smart-3d9b9b5b-0857-4905-b7f0-ebe115d7a761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881560053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.881560053
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4283781756
Short name T50
Test name
Test status
Simulation time 4911426049 ps
CPU time 4.77 seconds
Started Jul 25 07:13:58 PM PDT 24
Finished Jul 25 07:14:03 PM PDT 24
Peak memory 201768 kb
Host smart-bb4f8bf0-844b-4dde-b31c-f8735196775c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283781756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.4283781756
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.761098868
Short name T75
Test name
Test status
Simulation time 1034910621 ps
CPU time 1.82 seconds
Started Jul 25 07:13:58 PM PDT 24
Finished Jul 25 07:14:00 PM PDT 24
Peak memory 218036 kb
Host smart-24b648ef-b266-4d77-97a3-e29c216f6f86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761098868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.761098868
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3125900199
Short name T825
Test name
Test status
Simulation time 823554380 ps
CPU time 2.23 seconds
Started Jul 25 07:13:30 PM PDT 24
Finished Jul 25 07:13:32 PM PDT 24
Peak memory 201736 kb
Host smart-93773e86-e224-4aff-aa22-ae17ba3d174a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125900199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3125900199
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3354612420
Short name T899
Test name
Test status
Simulation time 26504737531 ps
CPU time 61.2 seconds
Started Jul 25 07:13:29 PM PDT 24
Finished Jul 25 07:14:31 PM PDT 24
Peak memory 201672 kb
Host smart-4af93828-f4f7-4745-b704-110cc7229903
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354612420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3354612420
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1027931780
Short name T908
Test name
Test status
Simulation time 1247106052 ps
CPU time 1.52 seconds
Started Jul 25 07:13:38 PM PDT 24
Finished Jul 25 07:13:40 PM PDT 24
Peak memory 201448 kb
Host smart-2028cf0f-21a9-4d24-b4f1-032fffe305dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027931780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1027931780
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3213182034
Short name T74
Test name
Test status
Simulation time 494300511 ps
CPU time 1.14 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:46 PM PDT 24
Peak memory 201616 kb
Host smart-01e29ea4-1961-4ac8-98e4-6c98f1f45169
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213182034 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3213182034
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3497742346
Short name T856
Test name
Test status
Simulation time 525192716 ps
CPU time 1.92 seconds
Started Jul 25 07:13:33 PM PDT 24
Finished Jul 25 07:13:35 PM PDT 24
Peak memory 201456 kb
Host smart-9b1bd0b1-5ed0-4652-8cfe-82c23af573f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497742346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3497742346
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3593345795
Short name T803
Test name
Test status
Simulation time 346094331 ps
CPU time 0.82 seconds
Started Jul 25 07:13:29 PM PDT 24
Finished Jul 25 07:13:30 PM PDT 24
Peak memory 201476 kb
Host smart-710bbb42-e642-4113-86a6-1ddfa8f96aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593345795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3593345795
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.185310356
Short name T917
Test name
Test status
Simulation time 4658718563 ps
CPU time 6.7 seconds
Started Jul 25 07:13:28 PM PDT 24
Finished Jul 25 07:13:35 PM PDT 24
Peak memory 201892 kb
Host smart-01677d47-4a05-4301-872f-1e0bed0a06e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185310356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.185310356
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3931601043
Short name T71
Test name
Test status
Simulation time 327755294 ps
CPU time 2.33 seconds
Started Jul 25 07:13:38 PM PDT 24
Finished Jul 25 07:13:40 PM PDT 24
Peak memory 201808 kb
Host smart-0a3354db-950a-45f6-8561-f01078e8d4f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931601043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3931601043
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.946510462
Short name T53
Test name
Test status
Simulation time 5190252779 ps
CPU time 4.16 seconds
Started Jul 25 07:13:29 PM PDT 24
Finished Jul 25 07:13:34 PM PDT 24
Peak memory 201764 kb
Host smart-03032e97-a69b-431a-9961-f2b632f5465c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946510462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.946510462
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3813011554
Short name T818
Test name
Test status
Simulation time 322205139 ps
CPU time 1.38 seconds
Started Jul 25 07:13:57 PM PDT 24
Finished Jul 25 07:13:59 PM PDT 24
Peak memory 201432 kb
Host smart-0f76d0cc-3d3d-44fa-8222-d39c88052806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813011554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3813011554
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2696594133
Short name T915
Test name
Test status
Simulation time 404989811 ps
CPU time 0.87 seconds
Started Jul 25 07:13:58 PM PDT 24
Finished Jul 25 07:13:59 PM PDT 24
Peak memory 201416 kb
Host smart-83faf55f-ca4f-4346-8070-a3f9e5b0bc57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696594133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2696594133
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1730748553
Short name T814
Test name
Test status
Simulation time 401467288 ps
CPU time 1.11 seconds
Started Jul 25 07:13:59 PM PDT 24
Finished Jul 25 07:14:00 PM PDT 24
Peak memory 201488 kb
Host smart-2286085c-6b21-4566-b3a0-1636463b1281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730748553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1730748553
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.943394411
Short name T892
Test name
Test status
Simulation time 350918984 ps
CPU time 0.85 seconds
Started Jul 25 07:13:57 PM PDT 24
Finished Jul 25 07:13:58 PM PDT 24
Peak memory 201464 kb
Host smart-678bfd89-1a6f-494d-bf43-8732dca1bfcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943394411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.943394411
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.314518415
Short name T835
Test name
Test status
Simulation time 525113620 ps
CPU time 0.67 seconds
Started Jul 25 07:14:00 PM PDT 24
Finished Jul 25 07:14:01 PM PDT 24
Peak memory 201444 kb
Host smart-60f3ca63-1a82-401e-86c8-9ffeb3d33684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314518415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.314518415
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.461470553
Short name T861
Test name
Test status
Simulation time 348305550 ps
CPU time 0.85 seconds
Started Jul 25 07:14:06 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201420 kb
Host smart-815a5843-b7d5-4d51-bec1-05f869a0eaea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461470553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.461470553
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1520163098
Short name T843
Test name
Test status
Simulation time 464899990 ps
CPU time 0.92 seconds
Started Jul 25 07:13:56 PM PDT 24
Finished Jul 25 07:13:57 PM PDT 24
Peak memory 201472 kb
Host smart-d72dfeeb-30cb-4810-b977-a1c7bc6c55dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520163098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1520163098
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2749687898
Short name T824
Test name
Test status
Simulation time 489794717 ps
CPU time 1.75 seconds
Started Jul 25 07:14:00 PM PDT 24
Finished Jul 25 07:14:02 PM PDT 24
Peak memory 201444 kb
Host smart-9a5a20af-82d7-4bb5-a96a-556f952da59b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749687898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2749687898
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1751055564
Short name T863
Test name
Test status
Simulation time 430411134 ps
CPU time 0.88 seconds
Started Jul 25 07:13:56 PM PDT 24
Finished Jul 25 07:13:57 PM PDT 24
Peak memory 201432 kb
Host smart-32dc3f2d-ab41-4402-baec-b8fbc732bba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751055564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1751055564
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1500907526
Short name T815
Test name
Test status
Simulation time 439092217 ps
CPU time 1.14 seconds
Started Jul 25 07:13:59 PM PDT 24
Finished Jul 25 07:14:01 PM PDT 24
Peak memory 201424 kb
Host smart-8ae2be70-46a6-49d4-8f2b-bd2473289fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500907526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1500907526
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3387417242
Short name T120
Test name
Test status
Simulation time 1021797033 ps
CPU time 4.35 seconds
Started Jul 25 07:13:43 PM PDT 24
Finished Jul 25 07:13:48 PM PDT 24
Peak memory 201720 kb
Host smart-f76b0ff6-04fc-42f2-bd02-9e2a65743376
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387417242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3387417242
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3460686508
Short name T119
Test name
Test status
Simulation time 27033626982 ps
CPU time 60.63 seconds
Started Jul 25 07:13:44 PM PDT 24
Finished Jul 25 07:14:45 PM PDT 24
Peak memory 201724 kb
Host smart-b95ca78d-6059-4fd8-bb6b-9e2ef3ae9494
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460686508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3460686508
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1686795409
Short name T808
Test name
Test status
Simulation time 748130904 ps
CPU time 0.78 seconds
Started Jul 25 07:13:42 PM PDT 24
Finished Jul 25 07:13:43 PM PDT 24
Peak memory 201472 kb
Host smart-1540b83c-1fac-48e2-9a33-1002679c99ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686795409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1686795409
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3335493878
Short name T73
Test name
Test status
Simulation time 508065717 ps
CPU time 1.51 seconds
Started Jul 25 07:13:43 PM PDT 24
Finished Jul 25 07:13:45 PM PDT 24
Peak memory 201596 kb
Host smart-a552cd80-68c0-442e-97a6-655862a3842a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335493878 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3335493878
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3384061249
Short name T115
Test name
Test status
Simulation time 438323174 ps
CPU time 1.06 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:47 PM PDT 24
Peak memory 201448 kb
Host smart-0d68c1bd-b5cd-4d34-847a-9b9386c49639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384061249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3384061249
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2842241346
Short name T836
Test name
Test status
Simulation time 567526227 ps
CPU time 0.74 seconds
Started Jul 25 07:13:46 PM PDT 24
Finished Jul 25 07:13:47 PM PDT 24
Peak memory 201448 kb
Host smart-26fb43ec-f050-44f8-b4d6-627f0789636a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842241346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2842241346
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3341555319
Short name T49
Test name
Test status
Simulation time 4817646281 ps
CPU time 14.98 seconds
Started Jul 25 07:13:43 PM PDT 24
Finished Jul 25 07:13:58 PM PDT 24
Peak memory 201760 kb
Host smart-ad793814-2564-4d52-87eb-5617ac6a8be0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341555319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3341555319
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2405596893
Short name T881
Test name
Test status
Simulation time 413050915 ps
CPU time 2.89 seconds
Started Jul 25 07:13:44 PM PDT 24
Finished Jul 25 07:13:47 PM PDT 24
Peak memory 201864 kb
Host smart-d4ddbe8d-b0d0-431a-8def-b982df4cdd8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405596893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2405596893
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2191382244
Short name T828
Test name
Test status
Simulation time 8949185545 ps
CPU time 5.99 seconds
Started Jul 25 07:13:43 PM PDT 24
Finished Jul 25 07:13:49 PM PDT 24
Peak memory 201768 kb
Host smart-cc43ce32-475f-48b7-bea3-f572535d465c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191382244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2191382244
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2036280855
Short name T796
Test name
Test status
Simulation time 403105263 ps
CPU time 1.05 seconds
Started Jul 25 07:14:09 PM PDT 24
Finished Jul 25 07:14:10 PM PDT 24
Peak memory 201460 kb
Host smart-df877b17-5ca4-4a6a-997b-1ea15e5bcef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036280855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2036280855
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2580035775
Short name T821
Test name
Test status
Simulation time 500504874 ps
CPU time 0.96 seconds
Started Jul 25 07:14:09 PM PDT 24
Finished Jul 25 07:14:10 PM PDT 24
Peak memory 201464 kb
Host smart-fc0c2a2f-216c-4bad-866d-cc6151ed1026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580035775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2580035775
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2939402184
Short name T795
Test name
Test status
Simulation time 451057004 ps
CPU time 1.67 seconds
Started Jul 25 07:14:05 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201436 kb
Host smart-83afa8d2-313f-4827-9092-f780f6482ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939402184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2939402184
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1463380988
Short name T801
Test name
Test status
Simulation time 515301332 ps
CPU time 1.74 seconds
Started Jul 25 07:14:06 PM PDT 24
Finished Jul 25 07:14:08 PM PDT 24
Peak memory 201480 kb
Host smart-695438d5-8b22-4f75-9284-14713d62034a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463380988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1463380988
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2598637272
Short name T807
Test name
Test status
Simulation time 488843367 ps
CPU time 1.7 seconds
Started Jul 25 07:14:05 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201432 kb
Host smart-2a3499ce-36c9-4553-9e8d-fdd4129de2de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598637272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2598637272
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3332921641
Short name T800
Test name
Test status
Simulation time 372293233 ps
CPU time 0.87 seconds
Started Jul 25 07:14:05 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201428 kb
Host smart-413288d4-bca0-4542-83dd-ba4d45c1e864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332921641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3332921641
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3317310265
Short name T895
Test name
Test status
Simulation time 568309856 ps
CPU time 0.74 seconds
Started Jul 25 07:14:06 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201492 kb
Host smart-60b3c13d-2013-4b89-bf1a-469768964dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317310265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3317310265
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2224980053
Short name T844
Test name
Test status
Simulation time 520925437 ps
CPU time 1.21 seconds
Started Jul 25 07:14:06 PM PDT 24
Finished Jul 25 07:14:08 PM PDT 24
Peak memory 201436 kb
Host smart-ee833d63-f871-4f4b-a800-638b132691cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224980053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2224980053
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1471067714
Short name T829
Test name
Test status
Simulation time 310980928 ps
CPU time 1.3 seconds
Started Jul 25 07:14:09 PM PDT 24
Finished Jul 25 07:14:10 PM PDT 24
Peak memory 201460 kb
Host smart-14a2c9d4-b107-4ae9-98a4-407eb9ac2f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471067714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1471067714
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3611897505
Short name T802
Test name
Test status
Simulation time 376846001 ps
CPU time 1.5 seconds
Started Jul 25 07:14:07 PM PDT 24
Finished Jul 25 07:14:08 PM PDT 24
Peak memory 201468 kb
Host smart-885bcd92-2ed2-407c-9649-15a4b503ab0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611897505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3611897505
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3717031799
Short name T862
Test name
Test status
Simulation time 1017123553 ps
CPU time 2.02 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:48 PM PDT 24
Peak memory 201652 kb
Host smart-8ff609fa-1bdd-45cb-a4e3-e77ba71068d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717031799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3717031799
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2799200262
Short name T882
Test name
Test status
Simulation time 25847701862 ps
CPU time 17.4 seconds
Started Jul 25 07:13:43 PM PDT 24
Finished Jul 25 07:14:01 PM PDT 24
Peak memory 201760 kb
Host smart-4d53fcb1-d3dd-4463-a154-1b060d81ff4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799200262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2799200262
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1455870511
Short name T902
Test name
Test status
Simulation time 679185530 ps
CPU time 2.25 seconds
Started Jul 25 07:13:44 PM PDT 24
Finished Jul 25 07:13:46 PM PDT 24
Peak memory 201456 kb
Host smart-2086215e-63ff-4c09-a6bc-5126958b3f62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455870511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1455870511
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1435059991
Short name T837
Test name
Test status
Simulation time 488662908 ps
CPU time 2.06 seconds
Started Jul 25 07:13:43 PM PDT 24
Finished Jul 25 07:13:45 PM PDT 24
Peak memory 201600 kb
Host smart-3443372e-e22a-49cc-8e0c-4a61b8c06d95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435059991 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1435059991
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1445619268
Short name T897
Test name
Test status
Simulation time 377977576 ps
CPU time 1.51 seconds
Started Jul 25 07:13:43 PM PDT 24
Finished Jul 25 07:13:44 PM PDT 24
Peak memory 201468 kb
Host smart-797aec34-add9-408f-9f9d-1987be817816
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445619268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1445619268
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3144092874
Short name T876
Test name
Test status
Simulation time 433695628 ps
CPU time 1.59 seconds
Started Jul 25 07:13:46 PM PDT 24
Finished Jul 25 07:13:47 PM PDT 24
Peak memory 201452 kb
Host smart-14a2190c-d021-4631-955f-09dd355e6ed2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144092874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3144092874
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4029900712
Short name T873
Test name
Test status
Simulation time 4273036921 ps
CPU time 5.2 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:51 PM PDT 24
Peak memory 201848 kb
Host smart-d0985f90-46d7-452b-bfb7-47cdfc14ada4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029900712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.4029900712
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1379603528
Short name T913
Test name
Test status
Simulation time 8808519221 ps
CPU time 5 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:50 PM PDT 24
Peak memory 201796 kb
Host smart-47d76208-c510-49f6-9d4d-a58f2292f434
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379603528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1379603528
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1277041120
Short name T820
Test name
Test status
Simulation time 457676661 ps
CPU time 0.87 seconds
Started Jul 25 07:14:07 PM PDT 24
Finished Jul 25 07:14:09 PM PDT 24
Peak memory 201436 kb
Host smart-7892b00f-5958-4e7e-90ed-e5df42210391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277041120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1277041120
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1544821384
Short name T883
Test name
Test status
Simulation time 385004601 ps
CPU time 1.56 seconds
Started Jul 25 07:14:09 PM PDT 24
Finished Jul 25 07:14:11 PM PDT 24
Peak memory 201460 kb
Host smart-31f4423f-18a3-4021-9746-7d2a420877d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544821384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1544821384
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.836460572
Short name T886
Test name
Test status
Simulation time 474747899 ps
CPU time 0.88 seconds
Started Jul 25 07:14:06 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201432 kb
Host smart-ab17c3ab-1178-4ab5-9c01-0df693a55945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836460572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.836460572
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.273926616
Short name T804
Test name
Test status
Simulation time 317696572 ps
CPU time 0.79 seconds
Started Jul 25 07:14:06 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201436 kb
Host smart-bc2dce07-201b-4d25-81d5-14447fb2005d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273926616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.273926616
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2051330961
Short name T870
Test name
Test status
Simulation time 439366701 ps
CPU time 1.49 seconds
Started Jul 25 07:14:06 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201440 kb
Host smart-b02d0f89-cda4-46b4-90df-baa2ac614926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051330961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2051330961
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3863731392
Short name T799
Test name
Test status
Simulation time 470589405 ps
CPU time 1.22 seconds
Started Jul 25 07:14:07 PM PDT 24
Finished Jul 25 07:14:08 PM PDT 24
Peak memory 201452 kb
Host smart-d5bc8d2a-0681-4823-870b-74f3eb35aa58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863731392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3863731392
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2970401904
Short name T806
Test name
Test status
Simulation time 397999576 ps
CPU time 0.67 seconds
Started Jul 25 07:14:06 PM PDT 24
Finished Jul 25 07:14:07 PM PDT 24
Peak memory 201500 kb
Host smart-4da30318-7246-4e52-830f-aa3679c3009b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970401904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2970401904
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.531931295
Short name T867
Test name
Test status
Simulation time 539533896 ps
CPU time 0.76 seconds
Started Jul 25 07:14:07 PM PDT 24
Finished Jul 25 07:14:08 PM PDT 24
Peak memory 201488 kb
Host smart-e80d768e-ad08-4a21-a7ea-0b5576fd9b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531931295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.531931295
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3211916502
Short name T848
Test name
Test status
Simulation time 362321508 ps
CPU time 1.48 seconds
Started Jul 25 07:14:06 PM PDT 24
Finished Jul 25 07:14:08 PM PDT 24
Peak memory 201504 kb
Host smart-6edf5ee3-4d0f-4bd7-9cca-8fe0edb0ebce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211916502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3211916502
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3287334795
Short name T845
Test name
Test status
Simulation time 329778737 ps
CPU time 1.36 seconds
Started Jul 25 07:14:08 PM PDT 24
Finished Jul 25 07:14:09 PM PDT 24
Peak memory 201436 kb
Host smart-4022543f-4cc9-4c3a-b4f2-6bca29d39b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287334795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3287334795
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2580055836
Short name T864
Test name
Test status
Simulation time 457447748 ps
CPU time 1.49 seconds
Started Jul 25 07:13:43 PM PDT 24
Finished Jul 25 07:13:45 PM PDT 24
Peak memory 201628 kb
Host smart-6be9a862-acc1-45b0-aa39-aa847761f23b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580055836 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2580055836
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3007981243
Short name T113
Test name
Test status
Simulation time 490298810 ps
CPU time 1.9 seconds
Started Jul 25 07:13:46 PM PDT 24
Finished Jul 25 07:13:48 PM PDT 24
Peak memory 201424 kb
Host smart-e252466f-1ad2-4558-a83b-eb13cd06adb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007981243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3007981243
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4265208109
Short name T869
Test name
Test status
Simulation time 458729951 ps
CPU time 1.01 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:47 PM PDT 24
Peak memory 201452 kb
Host smart-659fb5cd-b017-4ead-b58a-a1cddf909d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265208109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.4265208109
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4290747418
Short name T124
Test name
Test status
Simulation time 2030777181 ps
CPU time 4.9 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:50 PM PDT 24
Peak memory 201524 kb
Host smart-56910815-7c90-4d04-814e-0e74c3415001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290747418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.4290747418
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4094832067
Short name T859
Test name
Test status
Simulation time 628848424 ps
CPU time 2.04 seconds
Started Jul 25 07:13:44 PM PDT 24
Finished Jul 25 07:13:46 PM PDT 24
Peak memory 210020 kb
Host smart-f72825a1-fc79-419b-8b47-b32fa1edebb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094832067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4094832067
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1963798479
Short name T59
Test name
Test status
Simulation time 9329398952 ps
CPU time 11.66 seconds
Started Jul 25 07:13:44 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 201864 kb
Host smart-ee1cdce7-70c2-48a3-a36d-a99c0ad70b44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963798479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1963798479
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2392399389
Short name T888
Test name
Test status
Simulation time 515065396 ps
CPU time 1.42 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:47 PM PDT 24
Peak memory 201576 kb
Host smart-4ab4747c-947e-46f9-9a64-0b39b84d1162
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392399389 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2392399389
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3320900782
Short name T906
Test name
Test status
Simulation time 397207639 ps
CPU time 0.97 seconds
Started Jul 25 07:13:44 PM PDT 24
Finished Jul 25 07:13:45 PM PDT 24
Peak memory 201492 kb
Host smart-beb260a3-beca-4d02-8092-2bb1427034a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320900782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3320900782
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4004530606
Short name T854
Test name
Test status
Simulation time 522570924 ps
CPU time 1.5 seconds
Started Jul 25 07:13:43 PM PDT 24
Finished Jul 25 07:13:44 PM PDT 24
Peak memory 201472 kb
Host smart-53613045-c7f5-4b87-af47-23f0a6de22e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004530606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4004530606
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3933868754
Short name T889
Test name
Test status
Simulation time 1835951832 ps
CPU time 1.5 seconds
Started Jul 25 07:13:42 PM PDT 24
Finished Jul 25 07:13:44 PM PDT 24
Peak memory 201512 kb
Host smart-b65f0087-5e4a-47a8-8612-ad0da5adab2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933868754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3933868754
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1259507785
Short name T898
Test name
Test status
Simulation time 529178956 ps
CPU time 1.78 seconds
Started Jul 25 07:13:42 PM PDT 24
Finished Jul 25 07:13:44 PM PDT 24
Peak memory 217748 kb
Host smart-091af809-b139-4ab3-9a71-a08f211cdb39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259507785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1259507785
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2812974442
Short name T858
Test name
Test status
Simulation time 4207370610 ps
CPU time 10.49 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 201768 kb
Host smart-377075fb-c5e5-4596-bca0-a0911f64a032
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812974442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2812974442
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2579130144
Short name T874
Test name
Test status
Simulation time 530606901 ps
CPU time 1.58 seconds
Started Jul 25 07:13:44 PM PDT 24
Finished Jul 25 07:13:45 PM PDT 24
Peak memory 201576 kb
Host smart-3d0590d6-1de6-4a0c-a793-80b2158eb6ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579130144 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2579130144
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3333061372
Short name T112
Test name
Test status
Simulation time 458572360 ps
CPU time 0.92 seconds
Started Jul 25 07:13:46 PM PDT 24
Finished Jul 25 07:13:47 PM PDT 24
Peak memory 201420 kb
Host smart-59fa60c8-2bbd-4a5b-9839-7cf71264d6af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333061372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3333061372
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1632508987
Short name T834
Test name
Test status
Simulation time 392916949 ps
CPU time 1.53 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:47 PM PDT 24
Peak memory 201412 kb
Host smart-0dc2b7af-3003-4cc6-b319-e68db3977812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632508987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1632508987
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.440000489
Short name T838
Test name
Test status
Simulation time 2341834284 ps
CPU time 9.49 seconds
Started Jul 25 07:13:44 PM PDT 24
Finished Jul 25 07:13:54 PM PDT 24
Peak memory 201600 kb
Host smart-ab64e3e2-c57e-4c5d-b284-7a409569da2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440000489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.440000489
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2155395247
Short name T809
Test name
Test status
Simulation time 442481354 ps
CPU time 1.89 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:48 PM PDT 24
Peak memory 201792 kb
Host smart-0967b23e-5a5c-452c-9306-031f85aa500c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155395247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2155395247
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3881286716
Short name T884
Test name
Test status
Simulation time 4194864979 ps
CPU time 4.03 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:50 PM PDT 24
Peak memory 201736 kb
Host smart-1def246e-8059-4d79-b323-42d9f1e6e6ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881286716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3881286716
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1998937240
Short name T853
Test name
Test status
Simulation time 396445053 ps
CPU time 1.11 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:53 PM PDT 24
Peak memory 201576 kb
Host smart-450f2f0b-7aaf-4af5-9a17-25307599f963
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998937240 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1998937240
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2609536128
Short name T126
Test name
Test status
Simulation time 585411383 ps
CPU time 1.16 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:53 PM PDT 24
Peak memory 201404 kb
Host smart-d8659d5c-e10d-49fd-8072-03322bdeccdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609536128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2609536128
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1684606718
Short name T849
Test name
Test status
Simulation time 435793455 ps
CPU time 0.79 seconds
Started Jul 25 07:13:54 PM PDT 24
Finished Jul 25 07:13:55 PM PDT 24
Peak memory 201440 kb
Host smart-7ffc8ba6-1f70-431e-874d-f732a6548bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684606718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1684606718
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1621790890
Short name T914
Test name
Test status
Simulation time 2593127859 ps
CPU time 4.64 seconds
Started Jul 25 07:13:51 PM PDT 24
Finished Jul 25 07:13:56 PM PDT 24
Peak memory 201584 kb
Host smart-db5bdb7e-645b-4b8e-acf0-c62c7c5045d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621790890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1621790890
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2822450258
Short name T866
Test name
Test status
Simulation time 641099771 ps
CPU time 2.06 seconds
Started Jul 25 07:13:45 PM PDT 24
Finished Jul 25 07:13:47 PM PDT 24
Peak memory 201868 kb
Host smart-d346fc9e-ef77-44f5-b4be-f22fc6e9e63b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822450258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2822450258
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1117515397
Short name T909
Test name
Test status
Simulation time 8516597154 ps
CPU time 12.42 seconds
Started Jul 25 07:13:54 PM PDT 24
Finished Jul 25 07:14:06 PM PDT 24
Peak memory 201852 kb
Host smart-ef3501d1-c08b-4ba2-ad01-66daae8f5c06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117515397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1117515397
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.324874005
Short name T850
Test name
Test status
Simulation time 413427638 ps
CPU time 1.31 seconds
Started Jul 25 07:14:03 PM PDT 24
Finished Jul 25 07:14:05 PM PDT 24
Peak memory 201584 kb
Host smart-f01ece16-af3e-4fac-951f-a82f6de9f7f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324874005 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.324874005
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4233198405
Short name T110
Test name
Test status
Simulation time 600003114 ps
CPU time 0.86 seconds
Started Jul 25 07:13:50 PM PDT 24
Finished Jul 25 07:13:51 PM PDT 24
Peak memory 201512 kb
Host smart-4a37e437-84c2-4b3d-b517-cdbe2b6cad04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233198405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4233198405
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4236277347
Short name T842
Test name
Test status
Simulation time 526053376 ps
CPU time 0.93 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:53 PM PDT 24
Peak memory 201448 kb
Host smart-52c4fb38-e478-4558-8f33-3a8c2dc12437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236277347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4236277347
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3586629484
Short name T122
Test name
Test status
Simulation time 2223443874 ps
CPU time 5.14 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:58 PM PDT 24
Peak memory 201592 kb
Host smart-b1d72394-398b-4691-a66a-a7df0f5dafdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586629484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3586629484
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1783681654
Short name T865
Test name
Test status
Simulation time 858023292 ps
CPU time 2.9 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:55 PM PDT 24
Peak memory 210076 kb
Host smart-03c8bc4d-0709-4176-8547-2ab24f5e64ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783681654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1783681654
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1612262720
Short name T823
Test name
Test status
Simulation time 9272967528 ps
CPU time 4.68 seconds
Started Jul 25 07:13:52 PM PDT 24
Finished Jul 25 07:13:57 PM PDT 24
Peak memory 201848 kb
Host smart-f79585e0-7760-4b41-a562-f824b0f1f1e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612262720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1612262720
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2089336509
Short name T704
Test name
Test status
Simulation time 339327016 ps
CPU time 1.37 seconds
Started Jul 25 06:40:41 PM PDT 24
Finished Jul 25 06:40:43 PM PDT 24
Peak memory 201048 kb
Host smart-3561c436-7576-4fa8-91ca-f4d8784671da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089336509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2089336509
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2930844318
Short name T52
Test name
Test status
Simulation time 332083702586 ps
CPU time 361.13 seconds
Started Jul 25 06:40:44 PM PDT 24
Finished Jul 25 06:46:45 PM PDT 24
Peak memory 201244 kb
Host smart-7b2f23d7-15a0-48eb-a5ca-6e5795f23f44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930844318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2930844318
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.673952750
Short name T137
Test name
Test status
Simulation time 489980644738 ps
CPU time 88.93 seconds
Started Jul 25 06:40:44 PM PDT 24
Finished Jul 25 06:42:13 PM PDT 24
Peak memory 201296 kb
Host smart-cd3e7ae7-c85e-4cc0-a97e-3a0b7b981868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673952750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.673952750
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3115808540
Short name T641
Test name
Test status
Simulation time 486101701633 ps
CPU time 270.87 seconds
Started Jul 25 06:40:43 PM PDT 24
Finished Jul 25 06:45:14 PM PDT 24
Peak memory 201232 kb
Host smart-68d32dac-4f4a-4a75-93ef-bd76410eb96f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115808540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3115808540
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1484423739
Short name T27
Test name
Test status
Simulation time 486569970938 ps
CPU time 270.56 seconds
Started Jul 25 06:40:43 PM PDT 24
Finished Jul 25 06:45:13 PM PDT 24
Peak memory 201208 kb
Host smart-28ccab26-1ff1-4b04-90e8-80a88b1f6f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484423739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1484423739
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2700961428
Short name T691
Test name
Test status
Simulation time 488358471659 ps
CPU time 293 seconds
Started Jul 25 06:40:43 PM PDT 24
Finished Jul 25 06:45:36 PM PDT 24
Peak memory 201220 kb
Host smart-5835e95f-c23d-4333-99b6-d1b16582b02d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700961428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2700961428
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1116594038
Short name T162
Test name
Test status
Simulation time 351080403833 ps
CPU time 421.45 seconds
Started Jul 25 06:40:44 PM PDT 24
Finished Jul 25 06:47:45 PM PDT 24
Peak memory 201116 kb
Host smart-3574fb0c-a57b-47a9-a06c-bdd543e36216
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116594038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1116594038
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1359558772
Short name T616
Test name
Test status
Simulation time 408887625983 ps
CPU time 110.27 seconds
Started Jul 25 06:40:41 PM PDT 24
Finished Jul 25 06:42:31 PM PDT 24
Peak memory 201248 kb
Host smart-31cb6a60-6687-44a3-898c-6982cf8a6b47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359558772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1359558772
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.319547559
Short name T561
Test name
Test status
Simulation time 33506564879 ps
CPU time 69.88 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:41:57 PM PDT 24
Peak memory 201060 kb
Host smart-68065d00-d5a0-4db2-8bc8-e67c3dfba2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319547559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.319547559
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.71423778
Short name T581
Test name
Test status
Simulation time 5119975347 ps
CPU time 2.76 seconds
Started Jul 25 06:40:44 PM PDT 24
Finished Jul 25 06:40:47 PM PDT 24
Peak memory 201036 kb
Host smart-ede26dca-7281-4a30-ad07-b5b6a258add2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71423778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.71423778
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2740556081
Short name T770
Test name
Test status
Simulation time 5636137409 ps
CPU time 3.98 seconds
Started Jul 25 06:40:45 PM PDT 24
Finished Jul 25 06:40:49 PM PDT 24
Peak memory 201100 kb
Host smart-e58c75fa-f678-4b75-aebf-6e9e309cfecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740556081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2740556081
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3460437504
Short name T574
Test name
Test status
Simulation time 288994775260 ps
CPU time 689.87 seconds
Started Jul 25 06:40:43 PM PDT 24
Finished Jul 25 06:52:14 PM PDT 24
Peak memory 201628 kb
Host smart-2798b517-9656-4c5d-9265-1ab5e40e42c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460437504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3460437504
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.711209079
Short name T477
Test name
Test status
Simulation time 176741371324 ps
CPU time 224.69 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:44:31 PM PDT 24
Peak memory 217348 kb
Host smart-e6cd2ba3-1693-4aac-841b-2a3d85dbebe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711209079 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.711209079
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.708351879
Short name T419
Test name
Test status
Simulation time 530736608 ps
CPU time 0.8 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:40:47 PM PDT 24
Peak memory 201024 kb
Host smart-006271f8-8471-45f7-af36-a7134764af05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708351879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.708351879
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3274682743
Short name T230
Test name
Test status
Simulation time 162959421675 ps
CPU time 278.06 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:45:24 PM PDT 24
Peak memory 201232 kb
Host smart-bfbaa1b5-4d8a-4070-accc-408b39ff2812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274682743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3274682743
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3443694264
Short name T409
Test name
Test status
Simulation time 338153942264 ps
CPU time 197.49 seconds
Started Jul 25 06:40:43 PM PDT 24
Finished Jul 25 06:44:01 PM PDT 24
Peak memory 201164 kb
Host smart-6eb01361-7f19-44f2-9624-0221c061159b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443694264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3443694264
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2955912178
Short name T96
Test name
Test status
Simulation time 330207028248 ps
CPU time 176.81 seconds
Started Jul 25 06:40:44 PM PDT 24
Finished Jul 25 06:43:41 PM PDT 24
Peak memory 201192 kb
Host smart-f6681e77-5417-4b4f-a948-982dd10de444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955912178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2955912178
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3694161459
Short name T443
Test name
Test status
Simulation time 332157472628 ps
CPU time 165.61 seconds
Started Jul 25 06:40:43 PM PDT 24
Finished Jul 25 06:43:29 PM PDT 24
Peak memory 201200 kb
Host smart-d3664033-6dcc-4888-87cc-2df524b12d68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694161459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3694161459
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3673293215
Short name T714
Test name
Test status
Simulation time 179105498852 ps
CPU time 113.87 seconds
Started Jul 25 06:40:43 PM PDT 24
Finished Jul 25 06:42:37 PM PDT 24
Peak memory 201280 kb
Host smart-f11acb39-29e0-46de-a1c3-69059289618f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673293215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3673293215
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1422599578
Short name T343
Test name
Test status
Simulation time 81072853334 ps
CPU time 308.91 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:45:56 PM PDT 24
Peak memory 201756 kb
Host smart-be16f9c9-3f86-4042-9602-17c3a93be203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422599578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1422599578
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3893580582
Short name T389
Test name
Test status
Simulation time 45008410606 ps
CPU time 28.77 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:41:16 PM PDT 24
Peak memory 201096 kb
Host smart-419d57ad-420b-4cee-bb67-4125f8db7ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893580582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3893580582
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.4034388629
Short name T519
Test name
Test status
Simulation time 2935618373 ps
CPU time 6.85 seconds
Started Jul 25 06:40:42 PM PDT 24
Finished Jul 25 06:40:49 PM PDT 24
Peak memory 201096 kb
Host smart-9422222c-040a-4064-8dc0-3c682d5dcbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034388629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.4034388629
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3431834047
Short name T63
Test name
Test status
Simulation time 4538972611 ps
CPU time 2.71 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:40:50 PM PDT 24
Peak memory 216872 kb
Host smart-c8b2a6b2-eb56-448b-b6ab-eb06241c5422
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431834047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3431834047
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.335380425
Short name T559
Test name
Test status
Simulation time 5619385689 ps
CPU time 6.8 seconds
Started Jul 25 06:40:42 PM PDT 24
Finished Jul 25 06:40:49 PM PDT 24
Peak memory 201112 kb
Host smart-43aa9098-687e-4f51-9059-27e1b95474e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335380425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.335380425
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3766674758
Short name T721
Test name
Test status
Simulation time 166461660362 ps
CPU time 374.21 seconds
Started Jul 25 06:40:48 PM PDT 24
Finished Jul 25 06:47:03 PM PDT 24
Peak memory 201260 kb
Host smart-9ccb95f8-914c-4d8a-b063-f4cc081556c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766674758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3766674758
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3513986966
Short name T14
Test name
Test status
Simulation time 311013826025 ps
CPU time 54.46 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:41:41 PM PDT 24
Peak memory 209632 kb
Host smart-08b5c916-de21-4d20-850a-bd2c204dbe84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513986966 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3513986966
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.241629314
Short name T484
Test name
Test status
Simulation time 176335563943 ps
CPU time 364.66 seconds
Started Jul 25 06:41:09 PM PDT 24
Finished Jul 25 06:47:13 PM PDT 24
Peak memory 201284 kb
Host smart-e66cb866-315f-45b7-89d7-4579a333321d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241629314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.241629314
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2179655993
Short name T217
Test name
Test status
Simulation time 245300525752 ps
CPU time 563.84 seconds
Started Jul 25 06:41:07 PM PDT 24
Finished Jul 25 06:50:31 PM PDT 24
Peak memory 201280 kb
Host smart-01081fa1-113f-49b3-8e78-d7809afca8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179655993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2179655993
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3276420353
Short name T219
Test name
Test status
Simulation time 159954806401 ps
CPU time 197.95 seconds
Started Jul 25 06:41:13 PM PDT 24
Finished Jul 25 06:44:31 PM PDT 24
Peak memory 201276 kb
Host smart-c973a75c-c609-48a6-b5c8-311995da406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276420353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3276420353
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.4121224580
Short name T169
Test name
Test status
Simulation time 327200761134 ps
CPU time 98.77 seconds
Started Jul 25 06:41:06 PM PDT 24
Finished Jul 25 06:42:45 PM PDT 24
Peak memory 201220 kb
Host smart-0c738937-9087-4ee9-b1a6-d520d49f7d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121224580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.4121224580
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.4144666697
Short name T488
Test name
Test status
Simulation time 489047623870 ps
CPU time 1114.15 seconds
Started Jul 25 06:41:08 PM PDT 24
Finished Jul 25 06:59:42 PM PDT 24
Peak memory 201224 kb
Host smart-f751a66f-b9b9-469a-bff2-4dc49f6bd91f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144666697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.4144666697
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3014183283
Short name T597
Test name
Test status
Simulation time 193693676994 ps
CPU time 475.41 seconds
Started Jul 25 06:41:07 PM PDT 24
Finished Jul 25 06:49:03 PM PDT 24
Peak memory 201236 kb
Host smart-bd2cefff-61fa-40e8-a647-477692688f0e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014183283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3014183283
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.361371116
Short name T753
Test name
Test status
Simulation time 74843254326 ps
CPU time 307.94 seconds
Started Jul 25 06:41:09 PM PDT 24
Finished Jul 25 06:46:17 PM PDT 24
Peak memory 201672 kb
Host smart-8a6b1603-8bbb-4a60-a66f-2d70a6a4326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361371116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.361371116
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3240853052
Short name T792
Test name
Test status
Simulation time 39349868497 ps
CPU time 21.51 seconds
Started Jul 25 06:41:08 PM PDT 24
Finished Jul 25 06:41:30 PM PDT 24
Peak memory 201060 kb
Host smart-1fb3820d-7544-4998-855f-78d144a1f249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240853052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3240853052
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2965592385
Short name T758
Test name
Test status
Simulation time 4617140178 ps
CPU time 6.23 seconds
Started Jul 25 06:41:07 PM PDT 24
Finished Jul 25 06:41:13 PM PDT 24
Peak memory 201060 kb
Host smart-f92a1998-9653-4708-8e06-36aa5cf100da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965592385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2965592385
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.793558110
Short name T685
Test name
Test status
Simulation time 6160403908 ps
CPU time 15.61 seconds
Started Jul 25 06:41:05 PM PDT 24
Finished Jul 25 06:41:21 PM PDT 24
Peak memory 200968 kb
Host smart-15beb4a5-2401-40bc-85eb-78c9530a6b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793558110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.793558110
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.763856561
Short name T318
Test name
Test status
Simulation time 119156908912 ps
CPU time 67.98 seconds
Started Jul 25 06:41:09 PM PDT 24
Finished Jul 25 06:42:17 PM PDT 24
Peak memory 210028 kb
Host smart-17e586ce-97c9-4ae3-971a-4c4b9717b645
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763856561 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.763856561
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2464519307
Short name T390
Test name
Test status
Simulation time 317044394 ps
CPU time 0.85 seconds
Started Jul 25 06:41:13 PM PDT 24
Finished Jul 25 06:41:14 PM PDT 24
Peak memory 201008 kb
Host smart-b384e808-a680-4532-8f78-2d8ead3a56b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464519307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2464519307
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2714926504
Short name T661
Test name
Test status
Simulation time 191527887061 ps
CPU time 258.31 seconds
Started Jul 25 06:41:14 PM PDT 24
Finished Jul 25 06:45:32 PM PDT 24
Peak memory 201212 kb
Host smart-9cb49d98-ac1c-46f3-9660-4f6f08ed02b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714926504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2714926504
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.773727819
Short name T154
Test name
Test status
Simulation time 326281577407 ps
CPU time 713.36 seconds
Started Jul 25 06:41:09 PM PDT 24
Finished Jul 25 06:53:02 PM PDT 24
Peak memory 201228 kb
Host smart-99279ade-6837-4c89-a2e0-5185f317745a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773727819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.773727819
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3713261298
Short name T99
Test name
Test status
Simulation time 495383409405 ps
CPU time 532.35 seconds
Started Jul 25 06:41:14 PM PDT 24
Finished Jul 25 06:50:06 PM PDT 24
Peak memory 201220 kb
Host smart-c17845cf-9590-4a41-ad3e-6e25d1ba5317
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713261298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3713261298
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3401975042
Short name T95
Test name
Test status
Simulation time 487816815728 ps
CPU time 182.28 seconds
Started Jul 25 06:41:08 PM PDT 24
Finished Jul 25 06:44:11 PM PDT 24
Peak memory 201224 kb
Host smart-a68f69b6-90f8-4aa3-8f58-fcdf65214bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401975042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3401975042
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.179501132
Short name T500
Test name
Test status
Simulation time 160765797621 ps
CPU time 367.32 seconds
Started Jul 25 06:41:13 PM PDT 24
Finished Jul 25 06:47:20 PM PDT 24
Peak memory 201264 kb
Host smart-f2c8f6c8-3aa0-4590-8f50-f588393970b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=179501132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.179501132
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2941696083
Short name T275
Test name
Test status
Simulation time 169847667655 ps
CPU time 96.37 seconds
Started Jul 25 06:41:10 PM PDT 24
Finished Jul 25 06:42:46 PM PDT 24
Peak memory 201272 kb
Host smart-c8aaf421-cb12-486f-9e7d-c747bfcf7164
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941696083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2941696083
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1851537247
Short name T572
Test name
Test status
Simulation time 593729912471 ps
CPU time 474.09 seconds
Started Jul 25 06:41:08 PM PDT 24
Finished Jul 25 06:49:02 PM PDT 24
Peak memory 201256 kb
Host smart-886dffac-bb65-4e7d-b869-07f23b7a87f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851537247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1851537247
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.678746254
Short name T532
Test name
Test status
Simulation time 108258027235 ps
CPU time 323.66 seconds
Started Jul 25 06:41:09 PM PDT 24
Finished Jul 25 06:46:32 PM PDT 24
Peak memory 201688 kb
Host smart-0548b436-222e-47ab-a688-dae4ca3206df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678746254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.678746254
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2490076680
Short name T441
Test name
Test status
Simulation time 25492299357 ps
CPU time 28.94 seconds
Started Jul 25 06:41:10 PM PDT 24
Finished Jul 25 06:41:39 PM PDT 24
Peak memory 201104 kb
Host smart-746b2529-5b49-4a02-9316-e4e10b5aa309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490076680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2490076680
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.133317894
Short name T666
Test name
Test status
Simulation time 5119733507 ps
CPU time 13.44 seconds
Started Jul 25 06:41:11 PM PDT 24
Finished Jul 25 06:41:24 PM PDT 24
Peak memory 201128 kb
Host smart-f53e42f0-ffe8-4c7e-a931-50656b737522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133317894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.133317894
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1318982373
Short name T480
Test name
Test status
Simulation time 5696038112 ps
CPU time 12.33 seconds
Started Jul 25 06:41:07 PM PDT 24
Finished Jul 25 06:41:20 PM PDT 24
Peak memory 201100 kb
Host smart-b012c774-6a28-4b56-813b-b2ee5c1e4e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318982373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1318982373
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3894626583
Short name T473
Test name
Test status
Simulation time 330619313458 ps
CPU time 683.47 seconds
Started Jul 25 06:41:19 PM PDT 24
Finished Jul 25 06:52:42 PM PDT 24
Peak memory 201220 kb
Host smart-2b50f62f-6691-47e4-8fb9-91a288af008a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894626583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3894626583
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2544116508
Short name T36
Test name
Test status
Simulation time 250663955103 ps
CPU time 67.5 seconds
Started Jul 25 06:41:14 PM PDT 24
Finished Jul 25 06:42:22 PM PDT 24
Peak memory 201372 kb
Host smart-0c5e6584-ba2d-4975-8394-a00c6638daa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544116508 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2544116508
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.928859161
Short name T428
Test name
Test status
Simulation time 521573987 ps
CPU time 1.9 seconds
Started Jul 25 06:41:19 PM PDT 24
Finished Jul 25 06:41:21 PM PDT 24
Peak memory 201036 kb
Host smart-7af99d91-848d-4672-9644-80ad662a7820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928859161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.928859161
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3997381535
Short name T663
Test name
Test status
Simulation time 169107186792 ps
CPU time 353.18 seconds
Started Jul 25 06:41:15 PM PDT 24
Finished Jul 25 06:47:08 PM PDT 24
Peak memory 201200 kb
Host smart-3ca7ba94-ec18-42f5-aa1c-0e89cee16a9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997381535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3997381535
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2304436808
Short name T592
Test name
Test status
Simulation time 321624873286 ps
CPU time 228.21 seconds
Started Jul 25 06:41:13 PM PDT 24
Finished Jul 25 06:45:02 PM PDT 24
Peak memory 201300 kb
Host smart-11ebbecf-5cc9-4443-8507-8721c3baffd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304436808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2304436808
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1167665661
Short name T702
Test name
Test status
Simulation time 330263389468 ps
CPU time 112.73 seconds
Started Jul 25 06:41:13 PM PDT 24
Finished Jul 25 06:43:06 PM PDT 24
Peak memory 201220 kb
Host smart-030f6ed2-54b1-46a5-b89d-44127c89c5e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167665661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1167665661
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1015581060
Short name T153
Test name
Test status
Simulation time 499870318239 ps
CPU time 116.56 seconds
Started Jul 25 06:41:14 PM PDT 24
Finished Jul 25 06:43:11 PM PDT 24
Peak memory 201224 kb
Host smart-47657403-8108-4240-b438-e7585c51b253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015581060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1015581060
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2142167747
Short name T80
Test name
Test status
Simulation time 169817916214 ps
CPU time 272.86 seconds
Started Jul 25 06:41:15 PM PDT 24
Finished Jul 25 06:45:48 PM PDT 24
Peak memory 201224 kb
Host smart-1fba078a-61ea-4be0-9877-6c464f47707f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142167747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2142167747
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1536077792
Short name T610
Test name
Test status
Simulation time 375591161742 ps
CPU time 894.93 seconds
Started Jul 25 06:41:14 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 201248 kb
Host smart-f7b2f717-ecc8-412d-ad70-c62fa79ab40e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536077792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1536077792
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.811830787
Short name T524
Test name
Test status
Simulation time 202705426021 ps
CPU time 490.58 seconds
Started Jul 25 06:41:16 PM PDT 24
Finished Jul 25 06:49:26 PM PDT 24
Peak memory 201300 kb
Host smart-01bd25c9-6bc0-4c9a-b27e-1a7637fa7a8f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811830787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.811830787
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3030923629
Short name T175
Test name
Test status
Simulation time 117698249553 ps
CPU time 377.35 seconds
Started Jul 25 06:41:16 PM PDT 24
Finished Jul 25 06:47:33 PM PDT 24
Peak memory 201740 kb
Host smart-a784164c-faae-4fa2-9cf3-a6f66f201495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030923629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3030923629
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.57295011
Short name T736
Test name
Test status
Simulation time 42462036582 ps
CPU time 34.79 seconds
Started Jul 25 06:41:17 PM PDT 24
Finished Jul 25 06:41:52 PM PDT 24
Peak memory 201060 kb
Host smart-d93eb0f5-83d1-4ce9-b652-1690e5569232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57295011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.57295011
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.4043593697
Short name T368
Test name
Test status
Simulation time 5244117118 ps
CPU time 8.36 seconds
Started Jul 25 06:41:16 PM PDT 24
Finished Jul 25 06:41:25 PM PDT 24
Peak memory 201112 kb
Host smart-0d3c7a1d-9cb1-4e1a-8e7a-fc698796e6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043593697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.4043593697
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3903067028
Short name T552
Test name
Test status
Simulation time 5891927022 ps
CPU time 7.55 seconds
Started Jul 25 06:41:14 PM PDT 24
Finished Jul 25 06:41:22 PM PDT 24
Peak memory 201096 kb
Host smart-58fd3bc5-cf4d-480f-be0a-bca22ba9f500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903067028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3903067028
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2463378224
Short name T322
Test name
Test status
Simulation time 426567028794 ps
CPU time 949.6 seconds
Started Jul 25 06:41:16 PM PDT 24
Finished Jul 25 06:57:06 PM PDT 24
Peak memory 210020 kb
Host smart-96711dbb-8140-42bc-b388-9d71fdb9d811
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463378224 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2463378224
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2535073852
Short name T359
Test name
Test status
Simulation time 427749450 ps
CPU time 1.08 seconds
Started Jul 25 06:41:18 PM PDT 24
Finished Jul 25 06:41:19 PM PDT 24
Peak memory 201028 kb
Host smart-1ebcb92e-c28f-4ee4-9dba-e32a120e46d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535073852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2535073852
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.639539098
Short name T228
Test name
Test status
Simulation time 362050618354 ps
CPU time 737.83 seconds
Started Jul 25 06:41:17 PM PDT 24
Finished Jul 25 06:53:35 PM PDT 24
Peak memory 201212 kb
Host smart-9b224279-e894-4a39-a6a9-210fb38565ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639539098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.639539098
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2927691991
Short name T696
Test name
Test status
Simulation time 483549000328 ps
CPU time 314.78 seconds
Started Jul 25 06:41:15 PM PDT 24
Finished Jul 25 06:46:30 PM PDT 24
Peak memory 201240 kb
Host smart-01c24070-32b1-48eb-9397-cde3e0c6f185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927691991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2927691991
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2737291093
Short name T534
Test name
Test status
Simulation time 495523398739 ps
CPU time 196.38 seconds
Started Jul 25 06:41:18 PM PDT 24
Finished Jul 25 06:44:35 PM PDT 24
Peak memory 201236 kb
Host smart-c835ee85-625c-4e8a-a064-85ce9b8ba1e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737291093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2737291093
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.642027030
Short name T151
Test name
Test status
Simulation time 327804331834 ps
CPU time 715.3 seconds
Started Jul 25 06:41:17 PM PDT 24
Finished Jul 25 06:53:12 PM PDT 24
Peak memory 201288 kb
Host smart-beee0699-af8c-452b-8a83-bc3ffa300f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642027030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.642027030
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1864359172
Short name T24
Test name
Test status
Simulation time 161371986934 ps
CPU time 172.89 seconds
Started Jul 25 06:41:18 PM PDT 24
Finished Jul 25 06:44:11 PM PDT 24
Peak memory 201248 kb
Host smart-00108157-803d-49cc-9e11-679084e9a42a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864359172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1864359172
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1263834696
Short name T229
Test name
Test status
Simulation time 191094533104 ps
CPU time 161.61 seconds
Started Jul 25 06:41:18 PM PDT 24
Finished Jul 25 06:44:00 PM PDT 24
Peak memory 201248 kb
Host smart-bff0bf53-4c96-4925-8924-8585fb2afbd4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263834696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1263834696
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2894714784
Short name T762
Test name
Test status
Simulation time 399392977994 ps
CPU time 477.04 seconds
Started Jul 25 06:41:16 PM PDT 24
Finished Jul 25 06:49:14 PM PDT 24
Peak memory 201292 kb
Host smart-bd68b849-abc7-4cc3-8804-c3502025248c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894714784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2894714784
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.203653024
Short name T209
Test name
Test status
Simulation time 119603479937 ps
CPU time 399.54 seconds
Started Jul 25 06:41:18 PM PDT 24
Finished Jul 25 06:47:57 PM PDT 24
Peak memory 201700 kb
Host smart-83c9b020-fed8-4c76-8b19-01b59adc5852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203653024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.203653024
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4116010378
Short name T521
Test name
Test status
Simulation time 22977668108 ps
CPU time 13.78 seconds
Started Jul 25 06:41:20 PM PDT 24
Finished Jul 25 06:41:34 PM PDT 24
Peak memory 201052 kb
Host smart-c645fda6-9a6a-4cc0-9de2-1f2db948b8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116010378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4116010378
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2205339697
Short name T498
Test name
Test status
Simulation time 3491146619 ps
CPU time 9.15 seconds
Started Jul 25 06:41:17 PM PDT 24
Finished Jul 25 06:41:27 PM PDT 24
Peak memory 201084 kb
Host smart-7ca0d21c-80ef-45fd-b81e-957559fd664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205339697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2205339697
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2542642106
Short name T445
Test name
Test status
Simulation time 5826050388 ps
CPU time 14.72 seconds
Started Jul 25 06:41:19 PM PDT 24
Finished Jul 25 06:41:34 PM PDT 24
Peak memory 201096 kb
Host smart-1db70140-a1c2-41f4-b9e1-61e31020fde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542642106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2542642106
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3907691203
Short name T30
Test name
Test status
Simulation time 469326359 ps
CPU time 1.14 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:41:25 PM PDT 24
Peak memory 200960 kb
Host smart-0fa699e5-6a47-430c-9a2b-0ec54b73551b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907691203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3907691203
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2012651942
Short name T482
Test name
Test status
Simulation time 332980143534 ps
CPU time 214.12 seconds
Started Jul 25 06:41:22 PM PDT 24
Finished Jul 25 06:44:56 PM PDT 24
Peak memory 201312 kb
Host smart-4b58dcad-d050-4ad0-a9d3-9fadc2d6bd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012651942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2012651942
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2108959315
Short name T587
Test name
Test status
Simulation time 491521955336 ps
CPU time 1165.55 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 07:00:50 PM PDT 24
Peak memory 201216 kb
Host smart-ef6aa331-9242-40ed-8d2a-522515b3128b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108959315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2108959315
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3909813326
Short name T529
Test name
Test status
Simulation time 494626432617 ps
CPU time 1067.2 seconds
Started Jul 25 06:41:15 PM PDT 24
Finished Jul 25 06:59:03 PM PDT 24
Peak memory 201288 kb
Host smart-fbec8783-587d-4206-a7c7-a10c522a5e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909813326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3909813326
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.821931989
Short name T437
Test name
Test status
Simulation time 328995743284 ps
CPU time 360.26 seconds
Started Jul 25 06:41:20 PM PDT 24
Finished Jul 25 06:47:20 PM PDT 24
Peak memory 201200 kb
Host smart-56d0bb73-9932-4045-b13e-76ac553559b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=821931989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.821931989
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.267727982
Short name T253
Test name
Test status
Simulation time 197161715842 ps
CPU time 445.32 seconds
Started Jul 25 06:41:22 PM PDT 24
Finished Jul 25 06:48:47 PM PDT 24
Peak memory 201208 kb
Host smart-55a14452-1454-4c62-b311-88cd0c2a2fac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267727982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.267727982
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.340603666
Short name T631
Test name
Test status
Simulation time 206063143427 ps
CPU time 475.12 seconds
Started Jul 25 06:41:21 PM PDT 24
Finished Jul 25 06:49:17 PM PDT 24
Peak memory 201232 kb
Host smart-534717f4-abdf-496c-abbb-b1a0d4d9d653
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340603666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.340603666
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.4020317575
Short name T783
Test name
Test status
Simulation time 122119148092 ps
CPU time 453.88 seconds
Started Jul 25 06:41:22 PM PDT 24
Finished Jul 25 06:48:56 PM PDT 24
Peak memory 201632 kb
Host smart-d63ddb57-2af5-4bf7-a587-19e84f93c4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020317575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.4020317575
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1519255862
Short name T613
Test name
Test status
Simulation time 27938899759 ps
CPU time 64.38 seconds
Started Jul 25 06:41:23 PM PDT 24
Finished Jul 25 06:42:28 PM PDT 24
Peak memory 201068 kb
Host smart-74c85e77-3cd9-49b7-a1f4-5ba947eb02af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519255862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1519255862
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2503282701
Short name T411
Test name
Test status
Simulation time 4516607855 ps
CPU time 1.19 seconds
Started Jul 25 06:41:22 PM PDT 24
Finished Jul 25 06:41:23 PM PDT 24
Peak memory 201060 kb
Host smart-0f033c86-31bf-4813-91a9-859fe01a27c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503282701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2503282701
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.382778162
Short name T465
Test name
Test status
Simulation time 5872175367 ps
CPU time 4.52 seconds
Started Jul 25 06:41:17 PM PDT 24
Finished Jul 25 06:41:22 PM PDT 24
Peak memory 201104 kb
Host smart-b3279eb7-73b8-4632-9bb7-c694a631a6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382778162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.382778162
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3002146841
Short name T244
Test name
Test status
Simulation time 425965005864 ps
CPU time 1778.75 seconds
Started Jul 25 06:41:21 PM PDT 24
Finished Jul 25 07:11:00 PM PDT 24
Peak memory 209884 kb
Host smart-3bc6165d-b187-49ad-853b-00682a15391c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002146841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3002146841
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2620892029
Short name T37
Test name
Test status
Simulation time 44365594888 ps
CPU time 100.31 seconds
Started Jul 25 06:41:20 PM PDT 24
Finished Jul 25 06:43:01 PM PDT 24
Peak memory 209996 kb
Host smart-3488da16-8593-45a7-85fc-d6be67eb6117
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620892029 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2620892029
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3650217467
Short name T711
Test name
Test status
Simulation time 463937957 ps
CPU time 0.72 seconds
Started Jul 25 06:41:26 PM PDT 24
Finished Jul 25 06:41:27 PM PDT 24
Peak memory 201024 kb
Host smart-1038b9d0-b4f1-49c8-bcdd-99784a65fd2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650217467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3650217467
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3544852389
Short name T281
Test name
Test status
Simulation time 356657782723 ps
CPU time 192.55 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:44:37 PM PDT 24
Peak memory 201176 kb
Host smart-c458f469-5a82-4882-8c4e-5dc5370271e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544852389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3544852389
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.304852991
Short name T288
Test name
Test status
Simulation time 347683411825 ps
CPU time 592.85 seconds
Started Jul 25 06:41:21 PM PDT 24
Finished Jul 25 06:51:14 PM PDT 24
Peak memory 201288 kb
Host smart-5c91b684-8738-4913-9e23-5a848dfe6a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304852991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.304852991
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.90454633
Short name T220
Test name
Test status
Simulation time 333311708228 ps
CPU time 761.62 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:54:06 PM PDT 24
Peak memory 201300 kb
Host smart-af0acdb3-7aa9-4a8b-b38a-fa1d71ffdfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90454633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.90454633
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1594505385
Short name T481
Test name
Test status
Simulation time 492092010496 ps
CPU time 317.38 seconds
Started Jul 25 06:41:20 PM PDT 24
Finished Jul 25 06:46:37 PM PDT 24
Peak memory 201260 kb
Host smart-0acd72c5-e8cd-4432-b5d6-452d8f27b5ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594505385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1594505385
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2845320684
Short name T785
Test name
Test status
Simulation time 160573637673 ps
CPU time 90.45 seconds
Started Jul 25 06:41:23 PM PDT 24
Finished Jul 25 06:42:54 PM PDT 24
Peak memory 201220 kb
Host smart-129d57f7-df15-4e56-85ef-ab76bdbe33ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845320684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2845320684
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.4292361940
Short name T172
Test name
Test status
Simulation time 369685633637 ps
CPU time 217.13 seconds
Started Jul 25 06:41:20 PM PDT 24
Finished Jul 25 06:44:58 PM PDT 24
Peak memory 201216 kb
Host smart-7ceee44e-6152-41f9-9ae8-631b07551aaa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292361940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.4292361940
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.929821952
Short name T28
Test name
Test status
Simulation time 604826596044 ps
CPU time 838.7 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:55:23 PM PDT 24
Peak memory 201228 kb
Host smart-ac761c34-fa74-4b40-bdc7-c4a3eb74158b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929821952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.929821952
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.556592058
Short name T738
Test name
Test status
Simulation time 80427932684 ps
CPU time 479.51 seconds
Started Jul 25 06:41:26 PM PDT 24
Finished Jul 25 06:49:26 PM PDT 24
Peak memory 201680 kb
Host smart-a4d5a184-1fc7-46fc-8d07-c66622d89e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556592058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.556592058
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3591316257
Short name T505
Test name
Test status
Simulation time 32374377778 ps
CPU time 48.69 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:42:12 PM PDT 24
Peak memory 201100 kb
Host smart-1e41d90f-9619-4a4c-9d1f-83ebcf236a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591316257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3591316257
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.238709891
Short name T556
Test name
Test status
Simulation time 3157311699 ps
CPU time 8.25 seconds
Started Jul 25 06:41:26 PM PDT 24
Finished Jul 25 06:41:34 PM PDT 24
Peak memory 201052 kb
Host smart-1a8aa9d5-67a2-4d1f-8e67-e663fdd249b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238709891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.238709891
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3614435886
Short name T364
Test name
Test status
Simulation time 5871498941 ps
CPU time 15.3 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:41:39 PM PDT 24
Peak memory 201108 kb
Host smart-35ab9268-7e6f-4bda-9880-7241d70533d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614435886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3614435886
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2161840236
Short name T422
Test name
Test status
Simulation time 35676116870 ps
CPU time 77.77 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:42:42 PM PDT 24
Peak memory 201072 kb
Host smart-75ab24df-27c2-4359-8b25-7f44c83c2c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161840236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2161840236
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3240800154
Short name T567
Test name
Test status
Simulation time 460492406 ps
CPU time 1.77 seconds
Started Jul 25 06:41:22 PM PDT 24
Finished Jul 25 06:41:24 PM PDT 24
Peak memory 201052 kb
Host smart-0751a948-df04-442f-82e7-941254e77c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240800154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3240800154
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.73001778
Short name T261
Test name
Test status
Simulation time 328055319174 ps
CPU time 330.22 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:46:54 PM PDT 24
Peak memory 201224 kb
Host smart-367093d9-aa0d-4941-921e-f839fa53f67a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73001778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gatin
g.73001778
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1920561056
Short name T267
Test name
Test status
Simulation time 356967792560 ps
CPU time 772.3 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:54:16 PM PDT 24
Peak memory 201236 kb
Host smart-7dfee7d2-fd15-4aec-a97b-a70bbe02c004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920561056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1920561056
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.435600482
Short name T609
Test name
Test status
Simulation time 331847131646 ps
CPU time 362.93 seconds
Started Jul 25 06:41:21 PM PDT 24
Finished Jul 25 06:47:24 PM PDT 24
Peak memory 201284 kb
Host smart-9dd4fbc6-dae9-4b1a-ab9b-000365be6b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435600482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.435600482
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3727311565
Short name T652
Test name
Test status
Simulation time 481449469969 ps
CPU time 288.78 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:46:13 PM PDT 24
Peak memory 201168 kb
Host smart-f4826c7a-f233-4859-846b-433e17177e0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727311565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3727311565
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3964645892
Short name T4
Test name
Test status
Simulation time 320979751242 ps
CPU time 773.76 seconds
Started Jul 25 06:41:23 PM PDT 24
Finished Jul 25 06:54:17 PM PDT 24
Peak memory 201268 kb
Host smart-4ed5887d-e2b0-40a1-88e7-ee96dd0a0c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964645892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3964645892
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.659310330
Short name T374
Test name
Test status
Simulation time 166885311142 ps
CPU time 82.28 seconds
Started Jul 25 06:41:25 PM PDT 24
Finished Jul 25 06:42:47 PM PDT 24
Peak memory 201244 kb
Host smart-28351b8c-5535-45c9-83ff-1fb98bf5f456
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=659310330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.659310330
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3925924818
Short name T507
Test name
Test status
Simulation time 183618900193 ps
CPU time 101.1 seconds
Started Jul 25 06:41:21 PM PDT 24
Finished Jul 25 06:43:02 PM PDT 24
Peak memory 201236 kb
Host smart-13452166-a4f9-440d-bdad-f6660cdeaccf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925924818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3925924818
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2528801096
Short name T461
Test name
Test status
Simulation time 201886333451 ps
CPU time 34.06 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:41:58 PM PDT 24
Peak memory 201160 kb
Host smart-23082e09-5776-448d-9641-94097071990e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528801096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2528801096
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3306236201
Short name T45
Test name
Test status
Simulation time 126141617079 ps
CPU time 447.03 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:48:52 PM PDT 24
Peak memory 201688 kb
Host smart-ea3b12ae-2a07-4178-b3d2-e28cd983e5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306236201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3306236201
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2468771478
Short name T460
Test name
Test status
Simulation time 32670212692 ps
CPU time 38.45 seconds
Started Jul 25 06:41:22 PM PDT 24
Finished Jul 25 06:42:01 PM PDT 24
Peak memory 201092 kb
Host smart-2403ac24-5cd5-41de-a717-601b5021eee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468771478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2468771478
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.303050426
Short name T707
Test name
Test status
Simulation time 4805327101 ps
CPU time 12.18 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:41:36 PM PDT 24
Peak memory 201096 kb
Host smart-0f4a6a1c-4146-4255-9196-2259b9deeeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303050426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.303050426
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.478137289
Short name T433
Test name
Test status
Simulation time 6052432181 ps
CPU time 2.13 seconds
Started Jul 25 06:41:24 PM PDT 24
Finished Jul 25 06:41:26 PM PDT 24
Peak memory 201108 kb
Host smart-813f41a1-1071-47bb-8754-818183e4d9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478137289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.478137289
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2234486284
Short name T759
Test name
Test status
Simulation time 1505847332190 ps
CPU time 562.26 seconds
Started Jul 25 06:41:25 PM PDT 24
Finished Jul 25 06:50:47 PM PDT 24
Peak memory 212044 kb
Host smart-7cc68cfc-9ad5-44c3-895c-7badbe7d93bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234486284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2234486284
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2066870458
Short name T245
Test name
Test status
Simulation time 928141260724 ps
CPU time 629.87 seconds
Started Jul 25 06:41:20 PM PDT 24
Finished Jul 25 06:51:50 PM PDT 24
Peak memory 209968 kb
Host smart-cd5dce78-fbec-45f1-bd4e-e590c6a8f7f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066870458 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2066870458
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3681028301
Short name T585
Test name
Test status
Simulation time 417729727 ps
CPU time 1.05 seconds
Started Jul 25 06:41:30 PM PDT 24
Finished Jul 25 06:41:31 PM PDT 24
Peak memory 201032 kb
Host smart-d319b072-cc3d-4cff-b648-245c94ccc010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681028301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3681028301
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2306657640
Short name T251
Test name
Test status
Simulation time 167371953886 ps
CPU time 106.91 seconds
Started Jul 25 06:41:34 PM PDT 24
Finished Jul 25 06:43:21 PM PDT 24
Peak memory 201232 kb
Host smart-b1668646-4602-422c-85be-af9502d7b0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306657640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2306657640
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2951494996
Short name T268
Test name
Test status
Simulation time 167564787930 ps
CPU time 109.37 seconds
Started Jul 25 06:41:31 PM PDT 24
Finished Jul 25 06:43:20 PM PDT 24
Peak memory 201244 kb
Host smart-858bcac6-0936-4305-8d34-6b1b33579c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951494996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2951494996
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1933071181
Short name T416
Test name
Test status
Simulation time 167166186264 ps
CPU time 105.97 seconds
Started Jul 25 06:41:33 PM PDT 24
Finished Jul 25 06:43:19 PM PDT 24
Peak memory 201288 kb
Host smart-c13ac1e3-6f95-4b5d-ae7f-6de8ca4b50de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933071181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1933071181
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1914848675
Short name T152
Test name
Test status
Simulation time 319630035930 ps
CPU time 185.48 seconds
Started Jul 25 06:41:25 PM PDT 24
Finished Jul 25 06:44:31 PM PDT 24
Peak memory 201248 kb
Host smart-184dee7b-c749-402a-8d0e-62beb0c71404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914848675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1914848675
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.574523344
Short name T555
Test name
Test status
Simulation time 329746139117 ps
CPU time 353.8 seconds
Started Jul 25 06:41:28 PM PDT 24
Finished Jul 25 06:47:22 PM PDT 24
Peak memory 201200 kb
Host smart-54581686-7770-4ad0-8392-b567d2a49f63
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=574523344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.574523344
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.4025138582
Short name T212
Test name
Test status
Simulation time 202647974740 ps
CPU time 112.88 seconds
Started Jul 25 06:41:31 PM PDT 24
Finished Jul 25 06:43:24 PM PDT 24
Peak memory 201292 kb
Host smart-decf091d-9972-48e6-9696-f62b28465baa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025138582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.4025138582
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.123092524
Short name T640
Test name
Test status
Simulation time 611574677053 ps
CPU time 1495.02 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 07:06:22 PM PDT 24
Peak memory 201172 kb
Host smart-39af7b28-c954-4907-b4aa-754d39f4ed22
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123092524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.123092524
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3407185953
Short name T697
Test name
Test status
Simulation time 97020855931 ps
CPU time 374.85 seconds
Started Jul 25 06:41:34 PM PDT 24
Finished Jul 25 06:47:49 PM PDT 24
Peak memory 201732 kb
Host smart-70df56ed-75d3-4e2d-8000-6879793fc0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407185953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3407185953
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.4027115127
Short name T467
Test name
Test status
Simulation time 25567897928 ps
CPU time 4.53 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 06:41:31 PM PDT 24
Peak memory 201088 kb
Host smart-7c2c5632-1a6c-4838-a1df-b806d62b4a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027115127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4027115127
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1234044109
Short name T385
Test name
Test status
Simulation time 4613969286 ps
CPU time 4.56 seconds
Started Jul 25 06:41:30 PM PDT 24
Finished Jul 25 06:41:34 PM PDT 24
Peak memory 201064 kb
Host smart-dc8edcb2-e1e5-44d5-8c7d-6611c9cc79ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234044109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1234044109
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.189179188
Short name T732
Test name
Test status
Simulation time 6076517464 ps
CPU time 5.83 seconds
Started Jul 25 06:41:23 PM PDT 24
Finished Jul 25 06:41:29 PM PDT 24
Peak memory 201156 kb
Host smart-47216dd9-5d4e-4426-918c-277c82263acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189179188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.189179188
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.876113783
Short name T427
Test name
Test status
Simulation time 96031497118 ps
CPU time 473.7 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 06:49:21 PM PDT 24
Peak memory 217480 kb
Host smart-991d8a66-8efe-4239-9299-4595837f7023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876113783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
876113783
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3664389904
Short name T20
Test name
Test status
Simulation time 57710110875 ps
CPU time 73.49 seconds
Started Jul 25 06:41:34 PM PDT 24
Finished Jul 25 06:42:47 PM PDT 24
Peak memory 210036 kb
Host smart-13b7bcc4-41b2-4486-bcd8-d2bedb95d289
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664389904 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3664389904
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2222038804
Short name T486
Test name
Test status
Simulation time 488420813 ps
CPU time 0.88 seconds
Started Jul 25 06:41:29 PM PDT 24
Finished Jul 25 06:41:30 PM PDT 24
Peak memory 201036 kb
Host smart-d1e449de-3332-456b-83e4-6d5eb3d40ad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222038804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2222038804
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2178403342
Short name T280
Test name
Test status
Simulation time 180351844880 ps
CPU time 410.66 seconds
Started Jul 25 06:41:30 PM PDT 24
Finished Jul 25 06:48:21 PM PDT 24
Peak memory 201292 kb
Host smart-3e0ae5ac-8bc5-490b-b2c4-de55e7b11e38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178403342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2178403342
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.118083094
Short name T182
Test name
Test status
Simulation time 323310400653 ps
CPU time 201.68 seconds
Started Jul 25 06:41:34 PM PDT 24
Finished Jul 25 06:44:55 PM PDT 24
Peak memory 201220 kb
Host smart-766493f1-5721-43b6-88b6-03a3abfedb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118083094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.118083094
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1991009591
Short name T741
Test name
Test status
Simulation time 164691184265 ps
CPU time 398.1 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 06:48:05 PM PDT 24
Peak memory 201304 kb
Host smart-99997fb0-e481-48a7-b861-8350b441972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991009591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1991009591
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1037156622
Short name T665
Test name
Test status
Simulation time 337183754444 ps
CPU time 665.31 seconds
Started Jul 25 06:41:30 PM PDT 24
Finished Jul 25 06:52:35 PM PDT 24
Peak memory 201092 kb
Host smart-05132276-3a32-4225-a17d-ad070f3de7c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037156622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1037156622
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.4053641547
Short name T136
Test name
Test status
Simulation time 319739704561 ps
CPU time 784.14 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 06:54:31 PM PDT 24
Peak memory 201300 kb
Host smart-b98e2637-3d8d-4b6a-a1b4-1d69210a368c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053641547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4053641547
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2095448661
Short name T680
Test name
Test status
Simulation time 331930707189 ps
CPU time 409.58 seconds
Started Jul 25 06:41:25 PM PDT 24
Finished Jul 25 06:48:15 PM PDT 24
Peak memory 201240 kb
Host smart-871630a7-bf3f-4afd-909e-231dbd4e40e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095448661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2095448661
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.101621259
Short name T472
Test name
Test status
Simulation time 634324903497 ps
CPU time 359.74 seconds
Started Jul 25 06:41:32 PM PDT 24
Finished Jul 25 06:47:32 PM PDT 24
Peak memory 201208 kb
Host smart-e3888257-d1a1-415f-8093-61c7b8a37038
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101621259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.101621259
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2467729511
Short name T514
Test name
Test status
Simulation time 405266751392 ps
CPU time 1022.89 seconds
Started Jul 25 06:41:30 PM PDT 24
Finished Jul 25 06:58:33 PM PDT 24
Peak memory 201108 kb
Host smart-1a1c1a6b-dfb5-4c95-8455-26ea06ad7384
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467729511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2467729511
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2996402724
Short name T646
Test name
Test status
Simulation time 109825203832 ps
CPU time 532.13 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 06:50:20 PM PDT 24
Peak memory 201692 kb
Host smart-a5b0df32-7581-453d-afe9-a91367f9733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996402724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2996402724
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2297057994
Short name T379
Test name
Test status
Simulation time 39154760602 ps
CPU time 20.57 seconds
Started Jul 25 06:41:28 PM PDT 24
Finished Jul 25 06:41:49 PM PDT 24
Peak memory 201064 kb
Host smart-b2d9bbcc-e6ca-4577-84b3-d6698eb0d6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297057994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2297057994
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2122551228
Short name T130
Test name
Test status
Simulation time 4421152230 ps
CPU time 5.97 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 06:41:33 PM PDT 24
Peak memory 201024 kb
Host smart-b1ccf86b-d1e0-4ee7-b60f-d1bc118e6357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122551228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2122551228
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2050314924
Short name T541
Test name
Test status
Simulation time 5904894122 ps
CPU time 7.72 seconds
Started Jul 25 06:41:28 PM PDT 24
Finished Jul 25 06:41:36 PM PDT 24
Peak memory 201116 kb
Host smart-26bea328-9cd4-4af1-a638-9a57047742f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050314924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2050314924
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3050292603
Short name T690
Test name
Test status
Simulation time 90782448216 ps
CPU time 357.88 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 06:47:25 PM PDT 24
Peak memory 201672 kb
Host smart-7e6d9e17-4261-4422-ba82-9a2b8d264f9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050292603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3050292603
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1519873121
Short name T635
Test name
Test status
Simulation time 556279650 ps
CPU time 0.88 seconds
Started Jul 25 06:41:33 PM PDT 24
Finished Jul 25 06:41:34 PM PDT 24
Peak memory 201028 kb
Host smart-c0a2a1b9-3e9e-45ba-82b6-c268089df8d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519873121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1519873121
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2331535854
Short name T320
Test name
Test status
Simulation time 547842338299 ps
CPU time 152.77 seconds
Started Jul 25 06:41:30 PM PDT 24
Finished Jul 25 06:44:03 PM PDT 24
Peak memory 201276 kb
Host smart-d56fea62-fc12-4ce5-8e07-39b92ecd672f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331535854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2331535854
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3739091887
Short name T160
Test name
Test status
Simulation time 328503524630 ps
CPU time 191.34 seconds
Started Jul 25 06:41:28 PM PDT 24
Finished Jul 25 06:44:40 PM PDT 24
Peak memory 201300 kb
Host smart-53845328-9599-4241-a2ce-1e3770b24291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739091887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3739091887
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1683242863
Short name T768
Test name
Test status
Simulation time 164395039732 ps
CPU time 185.61 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 06:44:33 PM PDT 24
Peak memory 201260 kb
Host smart-760ca461-5a1b-4789-9ed1-ab7b8c5deaa1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683242863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1683242863
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3404371686
Short name T185
Test name
Test status
Simulation time 333906724656 ps
CPU time 202.73 seconds
Started Jul 25 06:41:26 PM PDT 24
Finished Jul 25 06:44:49 PM PDT 24
Peak memory 201240 kb
Host smart-d6622872-54be-4b38-bc0c-cdc24ce0fc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404371686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3404371686
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.544698666
Short name T406
Test name
Test status
Simulation time 493737330284 ps
CPU time 295.08 seconds
Started Jul 25 06:41:29 PM PDT 24
Finished Jul 25 06:46:24 PM PDT 24
Peak memory 201256 kb
Host smart-9bcd5c5d-2243-4557-8e3f-71600d292474
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=544698666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.544698666
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3496848378
Short name T776
Test name
Test status
Simulation time 608038655844 ps
CPU time 697.68 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 06:53:05 PM PDT 24
Peak memory 201228 kb
Host smart-1674e38c-02b3-43f5-a102-8fa6928e07e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496848378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3496848378
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1484184940
Short name T158
Test name
Test status
Simulation time 195272341702 ps
CPU time 122.29 seconds
Started Jul 25 06:41:29 PM PDT 24
Finished Jul 25 06:43:31 PM PDT 24
Peak memory 201264 kb
Host smart-83570752-7239-4994-a77a-09a3e0d7dabb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484184940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1484184940
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4126713262
Short name T46
Test name
Test status
Simulation time 121604065289 ps
CPU time 475.84 seconds
Started Jul 25 06:41:34 PM PDT 24
Finished Jul 25 06:49:30 PM PDT 24
Peak memory 201728 kb
Host smart-b2962899-788b-46ac-a51f-6597afabb515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126713262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4126713262
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2820198201
Short name T607
Test name
Test status
Simulation time 36884011169 ps
CPU time 22.07 seconds
Started Jul 25 06:41:34 PM PDT 24
Finished Jul 25 06:41:56 PM PDT 24
Peak memory 201088 kb
Host smart-1fc09da1-9e08-4dd2-bdd8-d840a59089fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820198201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2820198201
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2570198064
Short name T404
Test name
Test status
Simulation time 4556322256 ps
CPU time 6.43 seconds
Started Jul 25 06:41:27 PM PDT 24
Finished Jul 25 06:41:34 PM PDT 24
Peak memory 201084 kb
Host smart-8a6f4af5-980c-4468-8b7f-84f0aa0a679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570198064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2570198064
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.408127950
Short name T466
Test name
Test status
Simulation time 5893847031 ps
CPU time 3.2 seconds
Started Jul 25 06:41:28 PM PDT 24
Finished Jul 25 06:41:32 PM PDT 24
Peak memory 201128 kb
Host smart-f25c78ce-0d7d-484b-a4a6-67caa814e500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408127950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.408127950
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3516605741
Short name T316
Test name
Test status
Simulation time 491567936356 ps
CPU time 552.35 seconds
Started Jul 25 06:41:33 PM PDT 24
Finished Jul 25 06:50:46 PM PDT 24
Peak memory 201296 kb
Host smart-78171f4a-a0a8-41a7-8493-e9dde7f3eb9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516605741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3516605741
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.605791546
Short name T19
Test name
Test status
Simulation time 85801011234 ps
CPU time 187.46 seconds
Started Jul 25 06:41:35 PM PDT 24
Finished Jul 25 06:44:42 PM PDT 24
Peak memory 209624 kb
Host smart-a6f856dc-5c0a-414a-ab09-9f3b6276bea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605791546 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.605791546
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1774168644
Short name T553
Test name
Test status
Simulation time 445939623 ps
CPU time 1.1 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:40:48 PM PDT 24
Peak memory 201040 kb
Host smart-2498e5ce-ea68-4e6e-b7db-4590f22d9862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774168644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1774168644
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2376842876
Short name T260
Test name
Test status
Simulation time 160909971716 ps
CPU time 169.27 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:43:36 PM PDT 24
Peak memory 201296 kb
Host smart-48e83775-ca00-4cd0-9836-1a35cdd3c1d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376842876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2376842876
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2938649323
Short name T305
Test name
Test status
Simulation time 494946928258 ps
CPU time 325.58 seconds
Started Jul 25 06:40:48 PM PDT 24
Finished Jul 25 06:46:14 PM PDT 24
Peak memory 201236 kb
Host smart-0780642d-53b3-429b-af92-94943bf16fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938649323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2938649323
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3718405682
Short name T542
Test name
Test status
Simulation time 319834805012 ps
CPU time 317.42 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:46:05 PM PDT 24
Peak memory 201220 kb
Host smart-d0830283-7c50-4111-9d1c-0553aeabc3a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718405682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3718405682
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1554407818
Short name T149
Test name
Test status
Simulation time 488664103317 ps
CPU time 669.47 seconds
Started Jul 25 06:40:50 PM PDT 24
Finished Jul 25 06:52:00 PM PDT 24
Peak memory 201216 kb
Host smart-53242234-ad4a-4b19-b5f2-b327cec726bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554407818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1554407818
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3742337312
Short name T355
Test name
Test status
Simulation time 482732544991 ps
CPU time 290.47 seconds
Started Jul 25 06:40:51 PM PDT 24
Finished Jul 25 06:45:42 PM PDT 24
Peak memory 201220 kb
Host smart-3a535244-cf3b-4ea9-a4ff-656570267bef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742337312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3742337312
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2359698433
Short name T649
Test name
Test status
Simulation time 396773155671 ps
CPU time 454.92 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:48:22 PM PDT 24
Peak memory 201224 kb
Host smart-15e50ba8-26fc-4442-845c-eabc772bd452
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359698433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2359698433
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1940970860
Short name T563
Test name
Test status
Simulation time 88067484985 ps
CPU time 275.52 seconds
Started Jul 25 06:40:52 PM PDT 24
Finished Jul 25 06:45:28 PM PDT 24
Peak memory 201724 kb
Host smart-6b2097d7-064c-42a9-9f30-9c342250de79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940970860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1940970860
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.37794234
Short name T457
Test name
Test status
Simulation time 30273927949 ps
CPU time 9.27 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:40:56 PM PDT 24
Peak memory 201088 kb
Host smart-16781c31-e1e7-441b-ac18-8722c76f83f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37794234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.37794234
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3734519860
Short name T90
Test name
Test status
Simulation time 5535155211 ps
CPU time 1.4 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:40:48 PM PDT 24
Peak memory 200992 kb
Host smart-82cf26ca-e0f2-4c07-b7c2-de4ad4ca8666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734519860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3734519860
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2529584545
Short name T76
Test name
Test status
Simulation time 4225451584 ps
CPU time 9.88 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:40:56 PM PDT 24
Peak memory 216872 kb
Host smart-ba8e7599-98f9-4663-9a66-9b2508505280
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529584545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2529584545
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3745448481
Short name T469
Test name
Test status
Simulation time 6048637734 ps
CPU time 15.87 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:41:03 PM PDT 24
Peak memory 201108 kb
Host smart-4e0813d0-eacf-4035-b3c0-b6126fd9a5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745448481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3745448481
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2200590517
Short name T589
Test name
Test status
Simulation time 360980522152 ps
CPU time 758.07 seconds
Started Jul 25 06:40:50 PM PDT 24
Finished Jul 25 06:53:28 PM PDT 24
Peak memory 201220 kb
Host smart-a18469f9-1e48-48ec-aa5f-496f54a03d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200590517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2200590517
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.4262426973
Short name T295
Test name
Test status
Simulation time 28042132006 ps
CPU time 62.14 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:41:50 PM PDT 24
Peak memory 212220 kb
Host smart-620c8e64-58d4-479c-8d32-1a773e236602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262426973 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.4262426973
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2912798353
Short name T434
Test name
Test status
Simulation time 381194252 ps
CPU time 0.83 seconds
Started Jul 25 06:41:34 PM PDT 24
Finished Jul 25 06:41:35 PM PDT 24
Peak memory 201044 kb
Host smart-a66b54cd-2c99-4bc4-8f99-f65164d132fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912798353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2912798353
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3480218108
Short name T562
Test name
Test status
Simulation time 367368313141 ps
CPU time 794.3 seconds
Started Jul 25 06:41:33 PM PDT 24
Finished Jul 25 06:54:47 PM PDT 24
Peak memory 201220 kb
Host smart-8b19bc12-9666-4296-bd50-de034374619d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480218108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3480218108
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1183562571
Short name T101
Test name
Test status
Simulation time 166111878284 ps
CPU time 203.2 seconds
Started Jul 25 06:41:33 PM PDT 24
Finished Jul 25 06:44:57 PM PDT 24
Peak memory 201256 kb
Host smart-1cf89412-d484-41a4-b19a-5952d783e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183562571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1183562571
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.4290816206
Short name T173
Test name
Test status
Simulation time 323074251797 ps
CPU time 694.22 seconds
Started Jul 25 06:41:32 PM PDT 24
Finished Jul 25 06:53:06 PM PDT 24
Peak memory 201236 kb
Host smart-e15071f7-1393-457d-bc43-c0c84047be47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290816206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.4290816206
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3345165513
Short name T274
Test name
Test status
Simulation time 490616405287 ps
CPU time 528.09 seconds
Started Jul 25 06:41:33 PM PDT 24
Finished Jul 25 06:50:21 PM PDT 24
Peak memory 201296 kb
Host smart-e0d74073-16d0-410b-a42b-5de82f476eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345165513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3345165513
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.392632641
Short name T449
Test name
Test status
Simulation time 161480699561 ps
CPU time 42.96 seconds
Started Jul 25 06:41:32 PM PDT 24
Finished Jul 25 06:42:15 PM PDT 24
Peak memory 201244 kb
Host smart-b7f56835-d269-453f-8a7b-aa7165d5e878
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=392632641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.392632641
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3452243134
Short name T8
Test name
Test status
Simulation time 180164343195 ps
CPU time 217.44 seconds
Started Jul 25 06:41:34 PM PDT 24
Finished Jul 25 06:45:12 PM PDT 24
Peak memory 201300 kb
Host smart-c2a9cfc1-452f-4b0f-931e-bebe205e1279
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452243134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3452243134
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2939198081
Short name T396
Test name
Test status
Simulation time 590537733340 ps
CPU time 1425.85 seconds
Started Jul 25 06:41:34 PM PDT 24
Finished Jul 25 07:05:20 PM PDT 24
Peak memory 201240 kb
Host smart-1d529d4e-2f40-4cb7-b101-dd9a99ca1cf4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939198081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2939198081
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.4028676555
Short name T414
Test name
Test status
Simulation time 122742846220 ps
CPU time 554.53 seconds
Started Jul 25 06:41:35 PM PDT 24
Finished Jul 25 06:50:49 PM PDT 24
Peak memory 201616 kb
Host smart-1a551b16-4c96-400b-a81f-c7a2c6dea62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028676555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.4028676555
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2327287479
Short name T345
Test name
Test status
Simulation time 40480441014 ps
CPU time 91.34 seconds
Started Jul 25 06:41:33 PM PDT 24
Finished Jul 25 06:43:04 PM PDT 24
Peak memory 201032 kb
Host smart-ed30870c-4be2-4def-911a-48f3e198050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327287479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2327287479
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2976674713
Short name T487
Test name
Test status
Simulation time 5023161923 ps
CPU time 2.05 seconds
Started Jul 25 06:41:33 PM PDT 24
Finished Jul 25 06:41:35 PM PDT 24
Peak memory 201132 kb
Host smart-6ac12e31-9318-4dc4-b771-4effe008f1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976674713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2976674713
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.396861326
Short name T166
Test name
Test status
Simulation time 5677260284 ps
CPU time 3.34 seconds
Started Jul 25 06:41:34 PM PDT 24
Finished Jul 25 06:41:38 PM PDT 24
Peak memory 201108 kb
Host smart-ed648cc1-5b04-4c36-a769-3765231467b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396861326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.396861326
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2106685749
Short name T79
Test name
Test status
Simulation time 197561782439 ps
CPU time 483.15 seconds
Started Jul 25 06:41:33 PM PDT 24
Finished Jul 25 06:49:37 PM PDT 24
Peak memory 201284 kb
Host smart-be50ec98-0324-4f92-b816-acf1c34d4812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106685749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2106685749
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1991146877
Short name T735
Test name
Test status
Simulation time 53174011105 ps
CPU time 176.46 seconds
Started Jul 25 06:41:35 PM PDT 24
Finished Jul 25 06:44:32 PM PDT 24
Peak memory 217372 kb
Host smart-fe45861b-cd15-45e3-b247-e04bf1942df1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991146877 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1991146877
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3292022336
Short name T740
Test name
Test status
Simulation time 315481143 ps
CPU time 0.81 seconds
Started Jul 25 06:41:39 PM PDT 24
Finished Jul 25 06:41:40 PM PDT 24
Peak memory 201024 kb
Host smart-04b05a47-d32f-478f-b2c1-98843f03dc7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292022336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3292022336
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2611692516
Short name T39
Test name
Test status
Simulation time 339482276042 ps
CPU time 360.74 seconds
Started Jul 25 06:41:41 PM PDT 24
Finished Jul 25 06:47:42 PM PDT 24
Peak memory 201220 kb
Host smart-f850b173-45ad-4dbd-9d61-484f566b6181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611692516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2611692516
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.4122754908
Short name T131
Test name
Test status
Simulation time 503912813624 ps
CPU time 668.4 seconds
Started Jul 25 06:41:39 PM PDT 24
Finished Jul 25 06:52:47 PM PDT 24
Peak memory 201252 kb
Host smart-4530cb0a-4cd0-468a-9d3f-ca00f79b5bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122754908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.4122754908
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2418151781
Short name T659
Test name
Test status
Simulation time 159750503922 ps
CPU time 181.15 seconds
Started Jul 25 06:41:43 PM PDT 24
Finished Jul 25 06:44:45 PM PDT 24
Peak memory 201220 kb
Host smart-ff7e3519-e080-4b82-b5ef-b25165a9f2e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418151781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2418151781
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.975359967
Short name T254
Test name
Test status
Simulation time 328996020882 ps
CPU time 387.48 seconds
Started Jul 25 06:41:40 PM PDT 24
Finished Jul 25 06:48:07 PM PDT 24
Peak memory 201296 kb
Host smart-56f3f295-a34b-43af-8582-bd62dc608d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975359967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.975359967
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3054219792
Short name T442
Test name
Test status
Simulation time 326043132046 ps
CPU time 137.75 seconds
Started Jul 25 06:41:40 PM PDT 24
Finished Jul 25 06:43:58 PM PDT 24
Peak memory 201220 kb
Host smart-f1f03ff7-68b3-46cd-8760-3795a3277d84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054219792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3054219792
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.761567907
Short name T299
Test name
Test status
Simulation time 563771168647 ps
CPU time 255.17 seconds
Started Jul 25 06:41:41 PM PDT 24
Finished Jul 25 06:45:56 PM PDT 24
Peak memory 201224 kb
Host smart-41377df6-b075-41ec-8064-57d068b911c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761567907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.761567907
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2538474595
Short name T159
Test name
Test status
Simulation time 401405629087 ps
CPU time 239.41 seconds
Started Jul 25 06:41:41 PM PDT 24
Finished Jul 25 06:45:40 PM PDT 24
Peak memory 201300 kb
Host smart-c29cbe14-e607-4dd3-b2d1-e24d67934dc8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538474595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2538474595
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1664765701
Short name T48
Test name
Test status
Simulation time 105588094885 ps
CPU time 527.35 seconds
Started Jul 25 06:41:40 PM PDT 24
Finished Jul 25 06:50:27 PM PDT 24
Peak memory 201684 kb
Host smart-c4639359-fa07-42d9-bd50-b196072a3220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664765701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1664765701
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.603750062
Short name T6
Test name
Test status
Simulation time 36842252807 ps
CPU time 41.65 seconds
Started Jul 25 06:41:40 PM PDT 24
Finished Jul 25 06:42:22 PM PDT 24
Peak memory 201080 kb
Host smart-d0986963-ead1-4989-9037-f29eda7b8040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603750062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.603750062
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3344123877
Short name T10
Test name
Test status
Simulation time 2932779508 ps
CPU time 5.66 seconds
Started Jul 25 06:41:40 PM PDT 24
Finished Jul 25 06:41:45 PM PDT 24
Peak memory 201092 kb
Host smart-eb5941b5-02e2-4b71-886c-33343ea723a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344123877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3344123877
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2952258784
Short name T718
Test name
Test status
Simulation time 5812137791 ps
CPU time 7.76 seconds
Started Jul 25 06:41:40 PM PDT 24
Finished Jul 25 06:41:48 PM PDT 24
Peak memory 201128 kb
Host smart-72ebde83-503e-40ac-bdb3-0d6a7bf64bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952258784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2952258784
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.66579112
Short name T321
Test name
Test status
Simulation time 506589076207 ps
CPU time 631.16 seconds
Started Jul 25 06:41:41 PM PDT 24
Finished Jul 25 06:52:12 PM PDT 24
Peak memory 201240 kb
Host smart-0b10e9ed-3fe8-4636-8507-49a28883cb15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66579112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.66579112
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.584954064
Short name T528
Test name
Test status
Simulation time 56742638490 ps
CPU time 250.76 seconds
Started Jul 25 06:41:40 PM PDT 24
Finished Jul 25 06:45:51 PM PDT 24
Peak memory 216376 kb
Host smart-6677cc35-cfbc-4a1f-bea1-2c20aa05fea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584954064 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.584954064
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2911249481
Short name T757
Test name
Test status
Simulation time 428015423 ps
CPU time 0.67 seconds
Started Jul 25 06:41:49 PM PDT 24
Finished Jul 25 06:41:50 PM PDT 24
Peak memory 200956 kb
Host smart-2399a8a4-039f-4837-afaa-c74f9bea26fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911249481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2911249481
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3633567098
Short name T147
Test name
Test status
Simulation time 527924748982 ps
CPU time 422.3 seconds
Started Jul 25 06:41:46 PM PDT 24
Finished Jul 25 06:48:48 PM PDT 24
Peak memory 201200 kb
Host smart-6193ab36-54cc-4e29-826f-f26822609cfa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633567098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3633567098
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3498762883
Short name T332
Test name
Test status
Simulation time 164271109013 ps
CPU time 404.22 seconds
Started Jul 25 06:41:48 PM PDT 24
Finished Jul 25 06:48:33 PM PDT 24
Peak memory 201248 kb
Host smart-ba41f1c4-335f-4568-977c-6315765285e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498762883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3498762883
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.939216009
Short name T676
Test name
Test status
Simulation time 491135070943 ps
CPU time 1210.55 seconds
Started Jul 25 06:41:53 PM PDT 24
Finished Jul 25 07:02:04 PM PDT 24
Peak memory 201220 kb
Host smart-70c05f41-f8ee-4e5c-8ecf-33d9a1685a17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=939216009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.939216009
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.593251041
Short name T187
Test name
Test status
Simulation time 505171438821 ps
CPU time 305.24 seconds
Started Jul 25 06:41:40 PM PDT 24
Finished Jul 25 06:46:46 PM PDT 24
Peak memory 201212 kb
Host smart-fead10b8-a30c-457e-9469-db385b2059a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593251041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.593251041
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.4225345821
Short name T767
Test name
Test status
Simulation time 164375908883 ps
CPU time 276.48 seconds
Started Jul 25 06:41:40 PM PDT 24
Finished Jul 25 06:46:16 PM PDT 24
Peak memory 201232 kb
Host smart-b241fc7b-92b2-4ebc-91f3-dd28f63f7aa1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225345821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.4225345821
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.241386349
Short name T236
Test name
Test status
Simulation time 372844938096 ps
CPU time 779.88 seconds
Started Jul 25 06:41:47 PM PDT 24
Finished Jul 25 06:54:47 PM PDT 24
Peak memory 201224 kb
Host smart-cf3729a8-ae1c-40a3-a49b-88bbf442a66c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241386349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.241386349
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2886861523
Short name T361
Test name
Test status
Simulation time 193821050056 ps
CPU time 120.92 seconds
Started Jul 25 06:41:48 PM PDT 24
Finished Jul 25 06:43:49 PM PDT 24
Peak memory 201228 kb
Host smart-df9e4c63-a42d-450a-a4dc-22d96ec62f62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886861523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2886861523
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.253640177
Short name T781
Test name
Test status
Simulation time 37538814489 ps
CPU time 80.84 seconds
Started Jul 25 06:41:47 PM PDT 24
Finished Jul 25 06:43:08 PM PDT 24
Peak memory 201044 kb
Host smart-ec777d99-c328-483f-bbb7-d93cedd68dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253640177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.253640177
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2293645469
Short name T436
Test name
Test status
Simulation time 3111788179 ps
CPU time 1.19 seconds
Started Jul 25 06:41:49 PM PDT 24
Finished Jul 25 06:41:50 PM PDT 24
Peak memory 201012 kb
Host smart-38d1d88d-4e0d-4804-afb0-406e5aa24fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293645469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2293645469
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3474410914
Short name T516
Test name
Test status
Simulation time 5705315302 ps
CPU time 7.02 seconds
Started Jul 25 06:41:40 PM PDT 24
Finished Jul 25 06:41:47 PM PDT 24
Peak memory 201108 kb
Host smart-490ec83d-a356-4451-8e9b-d1ab871dc059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474410914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3474410914
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1580774789
Short name T283
Test name
Test status
Simulation time 164431104991 ps
CPU time 171.58 seconds
Started Jul 25 06:41:44 PM PDT 24
Finished Jul 25 06:44:36 PM PDT 24
Peak memory 201284 kb
Host smart-6a957694-5618-4e6e-83cf-8f249ead5e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580774789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1580774789
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1537745691
Short name T34
Test name
Test status
Simulation time 107480399066 ps
CPU time 196.32 seconds
Started Jul 25 06:41:47 PM PDT 24
Finished Jul 25 06:45:04 PM PDT 24
Peak memory 209988 kb
Host smart-7e756f8f-0904-483a-8a47-80c163f0b0b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537745691 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1537745691
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.512653010
Short name T424
Test name
Test status
Simulation time 475481171 ps
CPU time 0.71 seconds
Started Jul 25 06:41:53 PM PDT 24
Finished Jul 25 06:41:54 PM PDT 24
Peak memory 201032 kb
Host smart-f62963a6-706f-47aa-97da-a9295cb5b732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512653010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.512653010
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.55691994
Short name T565
Test name
Test status
Simulation time 348434889670 ps
CPU time 412.16 seconds
Started Jul 25 06:43:08 PM PDT 24
Finished Jul 25 06:50:00 PM PDT 24
Peak memory 201256 kb
Host smart-f0507aef-bf50-487b-a224-a26a35cdcec6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55691994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gatin
g.55691994
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.964205053
Short name T279
Test name
Test status
Simulation time 165292563991 ps
CPU time 203.47 seconds
Started Jul 25 06:42:02 PM PDT 24
Finished Jul 25 06:45:26 PM PDT 24
Peak memory 201240 kb
Host smart-cf2131b9-2b44-44cb-bfc9-ccc823c597ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964205053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.964205053
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.258381657
Short name T778
Test name
Test status
Simulation time 161344736592 ps
CPU time 49.33 seconds
Started Jul 25 06:41:52 PM PDT 24
Finished Jul 25 06:42:41 PM PDT 24
Peak memory 201296 kb
Host smart-c1872f59-d2e3-4bf2-8f52-cf18b26c9a17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=258381657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.258381657
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3488052544
Short name T246
Test name
Test status
Simulation time 328343633793 ps
CPU time 197.45 seconds
Started Jul 25 06:41:46 PM PDT 24
Finished Jul 25 06:45:04 PM PDT 24
Peak memory 201276 kb
Host smart-8c70d094-626c-42e5-bf39-69cac93523f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488052544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3488052544
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2627469434
Short name T619
Test name
Test status
Simulation time 492001843691 ps
CPU time 1130.4 seconds
Started Jul 25 06:41:49 PM PDT 24
Finished Jul 25 07:00:39 PM PDT 24
Peak memory 201232 kb
Host smart-763722a3-c120-4a15-9bde-ca4667fbd88f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627469434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2627469434
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1536904371
Short name T658
Test name
Test status
Simulation time 399833710665 ps
CPU time 69.57 seconds
Started Jul 25 06:41:56 PM PDT 24
Finished Jul 25 06:43:05 PM PDT 24
Peak memory 201224 kb
Host smart-1300b1c0-37eb-4cb3-81d3-b9321bd47c35
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536904371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1536904371
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2068524361
Short name T639
Test name
Test status
Simulation time 107352861782 ps
CPU time 468 seconds
Started Jul 25 06:41:53 PM PDT 24
Finished Jul 25 06:49:41 PM PDT 24
Peak memory 201660 kb
Host smart-5f7f7a8b-75ed-4c6d-9d32-89599269b42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068524361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2068524361
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1250309788
Short name T527
Test name
Test status
Simulation time 42290558640 ps
CPU time 95.38 seconds
Started Jul 25 06:41:53 PM PDT 24
Finished Jul 25 06:43:29 PM PDT 24
Peak memory 201084 kb
Host smart-d01cd6ce-ab76-4a82-b9b9-e9b12556ddd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250309788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1250309788
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.4077317615
Short name T522
Test name
Test status
Simulation time 5390326048 ps
CPU time 12.69 seconds
Started Jul 25 06:41:53 PM PDT 24
Finished Jul 25 06:42:06 PM PDT 24
Peak memory 201104 kb
Host smart-fa4e27a7-9e5c-4560-a32d-557f389fdec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077317615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.4077317615
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.300203133
Short name T763
Test name
Test status
Simulation time 5570227034 ps
CPU time 4.03 seconds
Started Jul 25 06:41:55 PM PDT 24
Finished Jul 25 06:41:59 PM PDT 24
Peak memory 201108 kb
Host smart-74fed6c8-5775-4a0a-b09d-77eb3019ab90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300203133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.300203133
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.461770879
Short name T67
Test name
Test status
Simulation time 171410373354 ps
CPU time 357.28 seconds
Started Jul 25 06:42:02 PM PDT 24
Finished Jul 25 06:47:59 PM PDT 24
Peak memory 201240 kb
Host smart-14fd4712-4342-4cbf-b72a-f916bdd2cb0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461770879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
461770879
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.460142713
Short name T464
Test name
Test status
Simulation time 325816353 ps
CPU time 0.8 seconds
Started Jul 25 06:42:01 PM PDT 24
Finished Jul 25 06:42:02 PM PDT 24
Peak memory 201028 kb
Host smart-afcf2129-e594-42b0-a344-eab3488f10a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460142713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.460142713
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2476296525
Short name T603
Test name
Test status
Simulation time 317391473154 ps
CPU time 28.03 seconds
Started Jul 25 06:42:00 PM PDT 24
Finished Jul 25 06:42:29 PM PDT 24
Peak memory 201228 kb
Host smart-bf4f687d-b594-4d1f-98d7-a4334b778361
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476296525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2476296525
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3899631860
Short name T601
Test name
Test status
Simulation time 332475968182 ps
CPU time 797.63 seconds
Started Jul 25 06:41:53 PM PDT 24
Finished Jul 25 06:55:10 PM PDT 24
Peak memory 201180 kb
Host smart-893ef98d-fbd2-41ce-9676-5f90af20539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899631860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3899631860
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2923040565
Short name T750
Test name
Test status
Simulation time 328696851071 ps
CPU time 208.02 seconds
Started Jul 25 06:42:02 PM PDT 24
Finished Jul 25 06:45:30 PM PDT 24
Peak memory 201220 kb
Host smart-d355736e-4660-4754-85af-9e0a2c83266d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923040565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2923040565
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2689618143
Short name T752
Test name
Test status
Simulation time 322740148134 ps
CPU time 794.84 seconds
Started Jul 25 06:41:56 PM PDT 24
Finished Jul 25 06:55:11 PM PDT 24
Peak memory 201304 kb
Host smart-4adcfeb7-c002-44c5-929b-16a15882b682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689618143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2689618143
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3174021536
Short name T369
Test name
Test status
Simulation time 162679594093 ps
CPU time 101.39 seconds
Started Jul 25 06:41:53 PM PDT 24
Finished Jul 25 06:43:34 PM PDT 24
Peak memory 201268 kb
Host smart-6122e5e8-f938-448b-b598-2c1c720a65e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174021536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3174021536
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2500492623
Short name T779
Test name
Test status
Simulation time 204288515615 ps
CPU time 121.61 seconds
Started Jul 25 06:42:01 PM PDT 24
Finished Jul 25 06:44:03 PM PDT 24
Peak memory 201228 kb
Host smart-b4b04bab-9f4e-4fdc-80e7-5cd54b65023d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500492623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2500492623
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2845789522
Short name T491
Test name
Test status
Simulation time 69954904872 ps
CPU time 225.68 seconds
Started Jul 25 06:42:03 PM PDT 24
Finished Jul 25 06:45:49 PM PDT 24
Peak memory 201684 kb
Host smart-8ad3d5b0-96ce-4785-9a61-fef02c4ca711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845789522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2845789522
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3432647872
Short name T194
Test name
Test status
Simulation time 32270778615 ps
CPU time 23.59 seconds
Started Jul 25 06:42:02 PM PDT 24
Finished Jul 25 06:42:26 PM PDT 24
Peak memory 201088 kb
Host smart-90c5ad4c-1742-400d-9c1e-dddd24eabb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432647872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3432647872
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1655287894
Short name T733
Test name
Test status
Simulation time 2944858556 ps
CPU time 7.37 seconds
Started Jul 25 06:42:00 PM PDT 24
Finished Jul 25 06:42:08 PM PDT 24
Peak memory 201112 kb
Host smart-8b982cac-2999-46bc-a4e3-0c8d79e444ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655287894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1655287894
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3361455875
Short name T511
Test name
Test status
Simulation time 5725207545 ps
CPU time 7.95 seconds
Started Jul 25 06:41:53 PM PDT 24
Finished Jul 25 06:42:01 PM PDT 24
Peak memory 201100 kb
Host smart-307e8aee-2941-46fd-a47b-c981b2b8f1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361455875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3361455875
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.4242776472
Short name T595
Test name
Test status
Simulation time 11003553470 ps
CPU time 7.94 seconds
Started Jul 25 06:42:04 PM PDT 24
Finished Jul 25 06:42:12 PM PDT 24
Peak memory 201104 kb
Host smart-4159c2c9-0e3b-47c9-92b5-c8059683dba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242776472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.4242776472
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1686354068
Short name T255
Test name
Test status
Simulation time 310835637189 ps
CPU time 521.9 seconds
Started Jul 25 06:43:14 PM PDT 24
Finished Jul 25 06:51:56 PM PDT 24
Peak memory 210144 kb
Host smart-04630fde-5507-4d81-b78b-5835b2c316f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686354068 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1686354068
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.967979119
Short name T669
Test name
Test status
Simulation time 422499912 ps
CPU time 0.77 seconds
Started Jul 25 06:42:05 PM PDT 24
Finished Jul 25 06:42:06 PM PDT 24
Peak memory 201004 kb
Host smart-5bcda282-33b3-4d38-a1ee-6b8a3fac05a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967979119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.967979119
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3747130448
Short name T717
Test name
Test status
Simulation time 345940427308 ps
CPU time 89.21 seconds
Started Jul 25 06:42:02 PM PDT 24
Finished Jul 25 06:43:32 PM PDT 24
Peak memory 201228 kb
Host smart-96991579-c513-432f-a2ef-08f783b17bc5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747130448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3747130448
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2577642521
Short name T78
Test name
Test status
Simulation time 494041208144 ps
CPU time 279.91 seconds
Started Jul 25 06:42:01 PM PDT 24
Finished Jul 25 06:46:41 PM PDT 24
Peak memory 201316 kb
Host smart-38469956-3abe-4fa3-b22b-2887a971aa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577642521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2577642521
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1754359106
Short name T713
Test name
Test status
Simulation time 157926673971 ps
CPU time 190.07 seconds
Started Jul 25 06:42:03 PM PDT 24
Finished Jul 25 06:45:14 PM PDT 24
Peak memory 201208 kb
Host smart-a4ed3f7b-a1c4-4a04-a9f2-ae8089bee271
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754359106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1754359106
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2088535320
Short name T627
Test name
Test status
Simulation time 167765625729 ps
CPU time 392.68 seconds
Started Jul 25 06:42:00 PM PDT 24
Finished Jul 25 06:48:33 PM PDT 24
Peak memory 201204 kb
Host smart-1281ee83-c568-4e08-8d3b-e989ded7474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088535320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2088535320
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3034856799
Short name T357
Test name
Test status
Simulation time 168183976920 ps
CPU time 89.92 seconds
Started Jul 25 06:42:04 PM PDT 24
Finished Jul 25 06:43:35 PM PDT 24
Peak memory 201200 kb
Host smart-fd92a621-fb46-4c79-8ee5-a86f14de5887
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034856799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3034856799
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1795661568
Short name T728
Test name
Test status
Simulation time 408595935127 ps
CPU time 242.38 seconds
Started Jul 25 06:42:02 PM PDT 24
Finished Jul 25 06:46:04 PM PDT 24
Peak memory 201232 kb
Host smart-49c30630-24fb-436d-b643-60c9dcc01c5d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795661568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1795661568
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2732615514
Short name T599
Test name
Test status
Simulation time 66066600148 ps
CPU time 344.42 seconds
Started Jul 25 06:42:06 PM PDT 24
Finished Jul 25 06:47:51 PM PDT 24
Peak memory 201740 kb
Host smart-ee036fe9-776d-459a-9791-135ed52827cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732615514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2732615514
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.491969368
Short name T346
Test name
Test status
Simulation time 30026031732 ps
CPU time 63.57 seconds
Started Jul 25 06:42:05 PM PDT 24
Finished Jul 25 06:43:09 PM PDT 24
Peak memory 201084 kb
Host smart-9d7d6d96-3eda-4894-b5e9-6dd00dc1a6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491969368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.491969368
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.362661689
Short name T372
Test name
Test status
Simulation time 3716796607 ps
CPU time 9.17 seconds
Started Jul 25 06:42:00 PM PDT 24
Finished Jul 25 06:42:09 PM PDT 24
Peak memory 201068 kb
Host smart-548ad922-a429-49a4-aa2f-af5c2add85c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362661689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.362661689
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1105556118
Short name T656
Test name
Test status
Simulation time 5670267515 ps
CPU time 4.18 seconds
Started Jul 25 06:42:03 PM PDT 24
Finished Jul 25 06:42:08 PM PDT 24
Peak memory 201104 kb
Host smart-3be42696-1513-4cd6-8203-277dbbefa36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105556118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1105556118
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.7417859
Short name T303
Test name
Test status
Simulation time 331860503208 ps
CPU time 182.31 seconds
Started Jul 25 06:42:10 PM PDT 24
Finished Jul 25 06:45:12 PM PDT 24
Peak memory 209600 kb
Host smart-8a8db4db-d4f4-4da8-a172-35338ea06f9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7417859 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.7417859
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1902727117
Short name T103
Test name
Test status
Simulation time 317851775 ps
CPU time 1 seconds
Started Jul 25 06:42:15 PM PDT 24
Finished Jul 25 06:42:16 PM PDT 24
Peak memory 201032 kb
Host smart-76e4088b-2cd4-47d4-9719-96ea5bd53362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902727117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1902727117
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3295812480
Short name T306
Test name
Test status
Simulation time 533071301589 ps
CPU time 534.09 seconds
Started Jul 25 06:42:06 PM PDT 24
Finished Jul 25 06:51:00 PM PDT 24
Peak memory 201216 kb
Host smart-5a226ae8-faf1-4c8a-8f36-0d35247d79a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295812480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3295812480
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.463291995
Short name T190
Test name
Test status
Simulation time 355256943702 ps
CPU time 200.52 seconds
Started Jul 25 06:42:06 PM PDT 24
Finished Jul 25 06:45:27 PM PDT 24
Peak memory 201204 kb
Host smart-8cc7c41a-9291-4d37-9497-d06411ed7588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463291995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.463291995
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.4117780076
Short name T284
Test name
Test status
Simulation time 334656602172 ps
CPU time 393.77 seconds
Started Jul 25 06:42:07 PM PDT 24
Finished Jul 25 06:48:41 PM PDT 24
Peak memory 201248 kb
Host smart-66ef1fac-495e-419b-a4c1-ad8e221608eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117780076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.4117780076
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2029055226
Short name T630
Test name
Test status
Simulation time 478610511664 ps
CPU time 1203.57 seconds
Started Jul 25 06:42:06 PM PDT 24
Finished Jul 25 07:02:10 PM PDT 24
Peak memory 201192 kb
Host smart-0ce45dab-3a02-4fa1-9bf9-10925235edaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029055226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2029055226
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1247955995
Short name T309
Test name
Test status
Simulation time 328883720393 ps
CPU time 768.33 seconds
Started Jul 25 06:42:07 PM PDT 24
Finished Jul 25 06:54:56 PM PDT 24
Peak memory 201216 kb
Host smart-58b1dbbe-d75d-4a53-9c13-83b6bfb5a1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247955995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1247955995
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3502573813
Short name T648
Test name
Test status
Simulation time 321677433270 ps
CPU time 393.66 seconds
Started Jul 25 06:42:13 PM PDT 24
Finished Jul 25 06:48:47 PM PDT 24
Peak memory 201260 kb
Host smart-8ac66236-3231-4ac2-b623-707ae9495ebc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502573813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3502573813
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2947343159
Short name T495
Test name
Test status
Simulation time 401999746093 ps
CPU time 285.01 seconds
Started Jul 25 06:42:06 PM PDT 24
Finished Jul 25 06:46:51 PM PDT 24
Peak memory 201208 kb
Host smart-a1607f69-4f50-413f-9e16-087203100094
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947343159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2947343159
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2367682301
Short name T421
Test name
Test status
Simulation time 105478607395 ps
CPU time 570.35 seconds
Started Jul 25 06:42:05 PM PDT 24
Finished Jul 25 06:51:36 PM PDT 24
Peak memory 201752 kb
Host smart-cb8b16d2-f0c7-4cb0-95e5-d8eac4362bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367682301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2367682301
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3948726503
Short name T617
Test name
Test status
Simulation time 33873633126 ps
CPU time 76.14 seconds
Started Jul 25 06:42:06 PM PDT 24
Finished Jul 25 06:43:22 PM PDT 24
Peak memory 201096 kb
Host smart-3658c981-33ba-4ae9-97b8-c9222280ecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948726503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3948726503
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2253057182
Short name T413
Test name
Test status
Simulation time 3984515175 ps
CPU time 1.24 seconds
Started Jul 25 06:42:03 PM PDT 24
Finished Jul 25 06:42:04 PM PDT 24
Peak memory 201104 kb
Host smart-ece316f6-dc10-41b3-a44a-2f31bd6b9c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253057182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2253057182
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2600671256
Short name T590
Test name
Test status
Simulation time 5910374769 ps
CPU time 14.67 seconds
Started Jul 25 06:42:12 PM PDT 24
Finished Jul 25 06:42:27 PM PDT 24
Peak memory 201116 kb
Host smart-c86b3d66-b8dc-4f1e-a142-7520d6e7680c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600671256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2600671256
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.859473893
Short name T788
Test name
Test status
Simulation time 434075496 ps
CPU time 1.66 seconds
Started Jul 25 06:42:13 PM PDT 24
Finished Jul 25 06:42:14 PM PDT 24
Peak memory 201032 kb
Host smart-bf23ba2a-570e-4b6f-970f-dacde1dd229f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859473893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.859473893
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2195679445
Short name T653
Test name
Test status
Simulation time 498545195915 ps
CPU time 305.86 seconds
Started Jul 25 06:42:12 PM PDT 24
Finished Jul 25 06:47:18 PM PDT 24
Peak memory 201228 kb
Host smart-5cdb2356-a03f-453d-87db-d96cd58078f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195679445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2195679445
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.985692933
Short name T451
Test name
Test status
Simulation time 173790668314 ps
CPU time 192.49 seconds
Started Jul 25 06:42:11 PM PDT 24
Finished Jul 25 06:45:24 PM PDT 24
Peak memory 201208 kb
Host smart-469c0583-6036-4bc9-a3a6-8a626acaf73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985692933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.985692933
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.774357409
Short name T474
Test name
Test status
Simulation time 163093601405 ps
CPU time 37.77 seconds
Started Jul 25 06:42:10 PM PDT 24
Finished Jul 25 06:42:48 PM PDT 24
Peak memory 201304 kb
Host smart-e7b34be0-9720-4bb1-a86d-072da6bc281e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774357409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.774357409
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3190815089
Short name T672
Test name
Test status
Simulation time 336482668154 ps
CPU time 144.83 seconds
Started Jul 25 06:42:13 PM PDT 24
Finished Jul 25 06:44:38 PM PDT 24
Peak memory 201200 kb
Host smart-d317a65c-8893-47c2-88f9-6ef6c663537d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190815089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3190815089
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.720017280
Short name T181
Test name
Test status
Simulation time 477966207519 ps
CPU time 292.81 seconds
Started Jul 25 06:42:12 PM PDT 24
Finished Jul 25 06:47:05 PM PDT 24
Peak memory 201288 kb
Host smart-562ee665-34a0-4f1d-9304-d3a38007a418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720017280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.720017280
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1400255055
Short name T745
Test name
Test status
Simulation time 482196670428 ps
CPU time 999.75 seconds
Started Jul 25 06:42:13 PM PDT 24
Finished Jul 25 06:58:53 PM PDT 24
Peak memory 201216 kb
Host smart-6fee61e6-ff8b-40e1-b156-af4c9b84fbd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400255055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1400255055
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2704265789
Short name T235
Test name
Test status
Simulation time 558421899704 ps
CPU time 582.46 seconds
Started Jul 25 06:42:12 PM PDT 24
Finished Jul 25 06:51:55 PM PDT 24
Peak memory 201244 kb
Host smart-6966b295-850e-4d88-b473-c88f82a3cec5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704265789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2704265789
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3604981797
Short name T98
Test name
Test status
Simulation time 203622932723 ps
CPU time 118.42 seconds
Started Jul 25 06:42:16 PM PDT 24
Finished Jul 25 06:44:15 PM PDT 24
Peak memory 201236 kb
Host smart-ab9b8840-3094-471c-9b2d-0e2639d989df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604981797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3604981797
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.4286843025
Short name T485
Test name
Test status
Simulation time 83933078726 ps
CPU time 326.4 seconds
Started Jul 25 06:42:12 PM PDT 24
Finished Jul 25 06:47:38 PM PDT 24
Peak memory 201760 kb
Host smart-16cdcb41-b47f-4097-8cdf-7408044a6b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286843025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.4286843025
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2593803060
Short name T403
Test name
Test status
Simulation time 44644459683 ps
CPU time 96.25 seconds
Started Jul 25 06:42:11 PM PDT 24
Finished Jul 25 06:43:48 PM PDT 24
Peak memory 201072 kb
Host smart-5fb0464f-f59b-4fd0-bfb2-18d4ad59b790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593803060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2593803060
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4076933086
Short name T109
Test name
Test status
Simulation time 5325852722 ps
CPU time 2.9 seconds
Started Jul 25 06:42:11 PM PDT 24
Finished Jul 25 06:42:14 PM PDT 24
Peak memory 201112 kb
Host smart-f2601adb-e15c-41e1-82e2-31a56c83e336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076933086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4076933086
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3864217263
Short name T429
Test name
Test status
Simulation time 5870837739 ps
CPU time 14.56 seconds
Started Jul 25 06:42:11 PM PDT 24
Finished Jul 25 06:42:26 PM PDT 24
Peak memory 201096 kb
Host smart-c1758a5b-8929-48d0-9825-4b31d99b223a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864217263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3864217263
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1284765273
Short name T250
Test name
Test status
Simulation time 667773912105 ps
CPU time 239.42 seconds
Started Jul 25 06:42:13 PM PDT 24
Finished Jul 25 06:46:13 PM PDT 24
Peak memory 201288 kb
Host smart-6828969c-ca1c-4072-bb8a-44c4d54f68bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284765273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1284765273
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3014164227
Short name T18
Test name
Test status
Simulation time 560796969876 ps
CPU time 1304.86 seconds
Started Jul 25 06:42:13 PM PDT 24
Finished Jul 25 07:03:59 PM PDT 24
Peak memory 210080 kb
Host smart-e9b61e3c-69b6-40ba-b5d4-b1de8eb71670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014164227 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3014164227
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3088799334
Short name T670
Test name
Test status
Simulation time 407401281 ps
CPU time 1.1 seconds
Started Jul 25 06:42:19 PM PDT 24
Finished Jul 25 06:42:20 PM PDT 24
Peak memory 201048 kb
Host smart-cc491e4b-8a6c-4d1d-95f0-872c5ba007cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088799334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3088799334
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3530175995
Short name T520
Test name
Test status
Simulation time 196546415208 ps
CPU time 89.11 seconds
Started Jul 25 06:42:18 PM PDT 24
Finished Jul 25 06:43:47 PM PDT 24
Peak memory 201280 kb
Host smart-89e8425c-8374-4308-a33f-7bc7c87c0eb7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530175995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3530175995
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.954727584
Short name T238
Test name
Test status
Simulation time 540880265052 ps
CPU time 1013.32 seconds
Started Jul 25 06:42:24 PM PDT 24
Finished Jul 25 06:59:18 PM PDT 24
Peak memory 201220 kb
Host smart-aec9064c-41d8-4d2e-b368-22ffccff0eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954727584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.954727584
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2926027349
Short name T706
Test name
Test status
Simulation time 503202620202 ps
CPU time 629.92 seconds
Started Jul 25 06:42:15 PM PDT 24
Finished Jul 25 06:52:45 PM PDT 24
Peak memory 201312 kb
Host smart-f4ca30ae-33a7-40b7-99bb-437145cf7bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926027349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2926027349
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1196447932
Short name T625
Test name
Test status
Simulation time 327364242503 ps
CPU time 197.89 seconds
Started Jul 25 06:42:11 PM PDT 24
Finished Jul 25 06:45:29 PM PDT 24
Peak memory 201276 kb
Host smart-85c70176-26ce-4567-a349-4aca927df0ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196447932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1196447932
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3049710780
Short name T489
Test name
Test status
Simulation time 167836683702 ps
CPU time 133.77 seconds
Started Jul 25 06:42:12 PM PDT 24
Finished Jul 25 06:44:26 PM PDT 24
Peak memory 201220 kb
Host smart-d8240d04-5663-47f3-a0dc-d0273868219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049710780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3049710780
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2495359663
Short name T722
Test name
Test status
Simulation time 162628683420 ps
CPU time 93.46 seconds
Started Jul 25 06:42:13 PM PDT 24
Finished Jul 25 06:43:47 PM PDT 24
Peak memory 201248 kb
Host smart-c7d5f807-0c39-43c9-9e8a-e40d2d821c75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495359663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2495359663
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3528509300
Short name T171
Test name
Test status
Simulation time 536243580327 ps
CPU time 303 seconds
Started Jul 25 06:42:11 PM PDT 24
Finished Jul 25 06:47:14 PM PDT 24
Peak memory 201284 kb
Host smart-4e660601-fef2-4eb9-b918-27d164a10f4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528509300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3528509300
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1605559744
Short name T367
Test name
Test status
Simulation time 610365055123 ps
CPU time 737.1 seconds
Started Jul 25 06:42:11 PM PDT 24
Finished Jul 25 06:54:28 PM PDT 24
Peak memory 201200 kb
Host smart-1dc625f4-c2ec-4a29-bb75-ea02295e1c9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605559744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1605559744
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1857129570
Short name T531
Test name
Test status
Simulation time 86092843990 ps
CPU time 329.43 seconds
Started Jul 25 06:42:17 PM PDT 24
Finished Jul 25 06:47:47 PM PDT 24
Peak memory 201676 kb
Host smart-cfd959b7-c31c-4e9f-9213-82dfb3c7408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857129570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1857129570
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3086312435
Short name T650
Test name
Test status
Simulation time 26643304425 ps
CPU time 30.2 seconds
Started Jul 25 06:42:20 PM PDT 24
Finished Jul 25 06:42:51 PM PDT 24
Peak memory 201048 kb
Host smart-253b146b-90fe-4a4c-bc98-b260ff6d7cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086312435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3086312435
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2081060764
Short name T350
Test name
Test status
Simulation time 3330768143 ps
CPU time 4.41 seconds
Started Jul 25 06:42:20 PM PDT 24
Finished Jul 25 06:42:24 PM PDT 24
Peak memory 201060 kb
Host smart-8530bdfb-ccf3-4dac-a2e4-d55f16db35c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081060764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2081060764
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2501276183
Short name T408
Test name
Test status
Simulation time 5720307511 ps
CPU time 6.57 seconds
Started Jul 25 06:42:13 PM PDT 24
Finished Jul 25 06:42:20 PM PDT 24
Peak memory 201160 kb
Host smart-bfd6f456-e6de-40be-9c27-b07e4354449a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501276183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2501276183
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.765743515
Short name T742
Test name
Test status
Simulation time 11009326355 ps
CPU time 13.22 seconds
Started Jul 25 06:42:16 PM PDT 24
Finished Jul 25 06:42:30 PM PDT 24
Peak memory 201120 kb
Host smart-e2572603-aae6-40c4-943d-5400b0ffbfa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765743515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
765743515
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1827213339
Short name T213
Test name
Test status
Simulation time 101629636397 ps
CPU time 112.77 seconds
Started Jul 25 06:42:19 PM PDT 24
Finished Jul 25 06:44:12 PM PDT 24
Peak memory 209648 kb
Host smart-05224a9c-ca76-40b4-97e2-5e59421b694b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827213339 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1827213339
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3191134285
Short name T771
Test name
Test status
Simulation time 431259600 ps
CPU time 0.77 seconds
Started Jul 25 06:42:24 PM PDT 24
Finished Jul 25 06:42:25 PM PDT 24
Peak memory 201056 kb
Host smart-87a3ec1e-64f0-4e7e-9b42-c8e3fab23090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191134285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3191134285
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.285721668
Short name T249
Test name
Test status
Simulation time 376121636492 ps
CPU time 874.9 seconds
Started Jul 25 06:42:24 PM PDT 24
Finished Jul 25 06:56:59 PM PDT 24
Peak memory 201248 kb
Host smart-89c7e0e9-349c-443f-ab6c-f29827f08166
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285721668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.285721668
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1042230485
Short name T294
Test name
Test status
Simulation time 498109568329 ps
CPU time 619.6 seconds
Started Jul 25 06:42:26 PM PDT 24
Finished Jul 25 06:52:46 PM PDT 24
Peak memory 201252 kb
Host smart-50b7e575-daf9-46c3-9c46-36a48c604c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042230485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1042230485
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1102706928
Short name T11
Test name
Test status
Simulation time 165401299613 ps
CPU time 340.65 seconds
Started Jul 25 06:42:25 PM PDT 24
Finished Jul 25 06:48:06 PM PDT 24
Peak memory 201296 kb
Host smart-56f1b378-616b-472d-80ea-edc1abea6d59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102706928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1102706928
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3973212466
Short name T296
Test name
Test status
Simulation time 491935161623 ps
CPU time 301.13 seconds
Started Jul 25 06:42:18 PM PDT 24
Finished Jul 25 06:47:19 PM PDT 24
Peak memory 201232 kb
Host smart-a25f9b4c-d243-4d8d-ad74-57d51bc5e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973212466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3973212466
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1546254564
Short name T401
Test name
Test status
Simulation time 502917859116 ps
CPU time 108.53 seconds
Started Jul 25 06:42:18 PM PDT 24
Finished Jul 25 06:44:06 PM PDT 24
Peak memory 201236 kb
Host smart-82efc327-61a1-48d7-8717-64d342d412aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546254564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1546254564
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3800030510
Short name T612
Test name
Test status
Simulation time 349953442770 ps
CPU time 395.91 seconds
Started Jul 25 06:42:27 PM PDT 24
Finished Jul 25 06:49:03 PM PDT 24
Peak memory 201228 kb
Host smart-30354608-1cb2-438c-8e92-823462ebcc37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800030510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3800030510
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1433279314
Short name T647
Test name
Test status
Simulation time 376891827708 ps
CPU time 173.93 seconds
Started Jul 25 06:42:25 PM PDT 24
Finished Jul 25 06:45:19 PM PDT 24
Peak memory 201252 kb
Host smart-5256d33c-d167-469a-a3c5-1a6683e70d04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433279314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1433279314
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4131896134
Short name T709
Test name
Test status
Simulation time 105422783372 ps
CPU time 521.6 seconds
Started Jul 25 06:42:26 PM PDT 24
Finished Jul 25 06:51:08 PM PDT 24
Peak memory 201748 kb
Host smart-51b2c1ed-e057-4da6-9786-b9cddd550dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131896134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4131896134
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2463885669
Short name T508
Test name
Test status
Simulation time 32045013851 ps
CPU time 14.78 seconds
Started Jul 25 06:42:23 PM PDT 24
Finished Jul 25 06:42:38 PM PDT 24
Peak memory 201096 kb
Host smart-2de97af4-0096-4501-94bd-63ac129571bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463885669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2463885669
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2606160744
Short name T729
Test name
Test status
Simulation time 3932393247 ps
CPU time 5.67 seconds
Started Jul 25 06:42:24 PM PDT 24
Finished Jul 25 06:42:30 PM PDT 24
Peak memory 201108 kb
Host smart-823b6547-43bf-4388-b9bd-42f9d4b37b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606160744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2606160744
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2632212759
Short name T537
Test name
Test status
Simulation time 5613789381 ps
CPU time 4.44 seconds
Started Jul 25 06:42:16 PM PDT 24
Finished Jul 25 06:42:21 PM PDT 24
Peak memory 201116 kb
Host smart-39fca9a7-5c7f-4d8c-a106-81f96f442734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632212759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2632212759
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3116872721
Short name T104
Test name
Test status
Simulation time 521410810716 ps
CPU time 466.7 seconds
Started Jul 25 06:42:24 PM PDT 24
Finished Jul 25 06:50:11 PM PDT 24
Peak memory 201248 kb
Host smart-cf0e479a-d4b9-4d4b-be3b-b5c42b0fa245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116872721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3116872721
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.665544043
Short name T668
Test name
Test status
Simulation time 10542381354 ps
CPU time 37.52 seconds
Started Jul 25 06:42:24 PM PDT 24
Finished Jul 25 06:43:02 PM PDT 24
Peak memory 209880 kb
Host smart-aa25bf9a-1b37-4959-aa1d-d2f09587a431
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665544043 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.665544043
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2340459194
Short name T399
Test name
Test status
Simulation time 528128726 ps
CPU time 1.22 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:40:48 PM PDT 24
Peak memory 201004 kb
Host smart-fb115bba-804a-45d1-a0c8-7b8f16cd35ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340459194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2340459194
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3634859890
Short name T231
Test name
Test status
Simulation time 168367361026 ps
CPU time 100.68 seconds
Started Jul 25 06:40:48 PM PDT 24
Finished Jul 25 06:42:29 PM PDT 24
Peak memory 201228 kb
Host smart-e5401fb9-1c32-4754-82a4-18b8a1cac6cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634859890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3634859890
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3891383959
Short name T214
Test name
Test status
Simulation time 324230229495 ps
CPU time 740.63 seconds
Started Jul 25 06:40:48 PM PDT 24
Finished Jul 25 06:53:08 PM PDT 24
Peak memory 201308 kb
Host smart-ad9e0508-4e4e-40cd-aee0-b7f9c90028e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891383959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3891383959
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.487903244
Short name T454
Test name
Test status
Simulation time 162891567427 ps
CPU time 76.95 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:42:03 PM PDT 24
Peak memory 201288 kb
Host smart-771b8512-2726-4b7b-b3fe-c863d1c1cae1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=487903244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.487903244
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.666959463
Short name T618
Test name
Test status
Simulation time 163550342154 ps
CPU time 399.19 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:47:26 PM PDT 24
Peak memory 201240 kb
Host smart-fc0599e1-69c6-4fbb-ac37-a7cafd2e03fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=666959463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.666959463
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.400572041
Short name T335
Test name
Test status
Simulation time 455405426501 ps
CPU time 252.48 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:45:00 PM PDT 24
Peak memory 201172 kb
Host smart-734b7959-16d7-44d2-b03d-5c59815d94d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400572041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.400572041
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.81518079
Short name T681
Test name
Test status
Simulation time 203468667023 ps
CPU time 228.05 seconds
Started Jul 25 06:40:48 PM PDT 24
Finished Jul 25 06:44:36 PM PDT 24
Peak memory 201236 kb
Host smart-6d89fba8-4231-414c-8ba3-9d2542ceda9d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81518079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.ad
c_ctrl_filters_wakeup_fixed.81518079
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.4153742517
Short name T586
Test name
Test status
Simulation time 93611228501 ps
CPU time 530.73 seconds
Started Jul 25 06:40:45 PM PDT 24
Finished Jul 25 06:49:36 PM PDT 24
Peak memory 201748 kb
Host smart-72ebbdbd-f379-4d15-97ed-d635a3bd9d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153742517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.4153742517
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2437161752
Short name T499
Test name
Test status
Simulation time 24283451270 ps
CPU time 4.34 seconds
Started Jul 25 06:40:45 PM PDT 24
Finished Jul 25 06:40:50 PM PDT 24
Peak memory 201056 kb
Host smart-070739d1-ed53-41c2-8636-f6e76f38f880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437161752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2437161752
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1451225350
Short name T764
Test name
Test status
Simulation time 4355552613 ps
CPU time 11.36 seconds
Started Jul 25 06:40:47 PM PDT 24
Finished Jul 25 06:40:59 PM PDT 24
Peak memory 201080 kb
Host smart-78d7ff41-5258-4915-9fcb-f6f6c97c1232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451225350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1451225350
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3318939798
Short name T77
Test name
Test status
Simulation time 4207898809 ps
CPU time 10.45 seconds
Started Jul 25 06:40:46 PM PDT 24
Finished Jul 25 06:40:56 PM PDT 24
Peak memory 216976 kb
Host smart-21aef52f-a0ca-4198-8a7b-4d0a2cc9b606
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318939798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3318939798
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.636083202
Short name T558
Test name
Test status
Simulation time 5789064687 ps
CPU time 13.6 seconds
Started Jul 25 06:40:49 PM PDT 24
Finished Jul 25 06:41:02 PM PDT 24
Peak memory 201084 kb
Host smart-2228e7ea-51d4-45b5-86b6-f529f6b282dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636083202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.636083202
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.4101982287
Short name T195
Test name
Test status
Simulation time 163400792921 ps
CPU time 47.76 seconds
Started Jul 25 06:40:50 PM PDT 24
Finished Jul 25 06:41:38 PM PDT 24
Peak memory 201224 kb
Host smart-9fda75ec-a0d7-43a9-8af8-8e2ef477331c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101982287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
4101982287
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1910708142
Short name T388
Test name
Test status
Simulation time 413776128 ps
CPU time 0.87 seconds
Started Jul 25 06:42:39 PM PDT 24
Finished Jul 25 06:42:40 PM PDT 24
Peak memory 201044 kb
Host smart-4a34e6e2-a994-488c-a6c9-f3322032544f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910708142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1910708142
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1103534681
Short name T794
Test name
Test status
Simulation time 189647513474 ps
CPU time 114.3 seconds
Started Jul 25 06:42:38 PM PDT 24
Finished Jul 25 06:44:32 PM PDT 24
Peak memory 201308 kb
Host smart-d2874d69-2acb-4493-ab37-1d6e4076ed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103534681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1103534681
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2134166821
Short name T93
Test name
Test status
Simulation time 333020807596 ps
CPU time 190.33 seconds
Started Jul 25 06:42:33 PM PDT 24
Finished Jul 25 06:45:44 PM PDT 24
Peak memory 201252 kb
Host smart-b53be549-0ae9-4389-86a6-27e892fd8050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134166821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2134166821
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1685343090
Short name T692
Test name
Test status
Simulation time 489948030991 ps
CPU time 151.9 seconds
Started Jul 25 06:42:32 PM PDT 24
Finished Jul 25 06:45:04 PM PDT 24
Peak memory 201228 kb
Host smart-a86d8581-66d6-4686-bbd2-7b606b741558
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685343090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1685343090
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3819626346
Short name T566
Test name
Test status
Simulation time 495112527372 ps
CPU time 1137.61 seconds
Started Jul 25 06:42:32 PM PDT 24
Finished Jul 25 07:01:30 PM PDT 24
Peak memory 201288 kb
Host smart-4dc2efc8-73eb-4ee9-92e0-bf15e9338d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819626346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3819626346
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1385534365
Short name T393
Test name
Test status
Simulation time 166804972953 ps
CPU time 122.64 seconds
Started Jul 25 06:42:38 PM PDT 24
Finished Jul 25 06:44:41 PM PDT 24
Peak memory 201240 kb
Host smart-b73523d2-9bd5-4016-9ae2-1ed7fcdae835
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385534365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1385534365
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2083750828
Short name T523
Test name
Test status
Simulation time 366889285787 ps
CPU time 851.66 seconds
Started Jul 25 06:42:33 PM PDT 24
Finished Jul 25 06:56:44 PM PDT 24
Peak memory 201208 kb
Host smart-1c499ce5-845a-434f-afc0-760f43a886cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083750828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2083750828
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3122713943
Short name T348
Test name
Test status
Simulation time 199704388545 ps
CPU time 132.21 seconds
Started Jul 25 06:42:37 PM PDT 24
Finished Jul 25 06:44:49 PM PDT 24
Peak memory 201304 kb
Host smart-d8658851-76aa-4074-91a3-8bc945e224d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122713943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3122713943
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3838754008
Short name T664
Test name
Test status
Simulation time 131469625885 ps
CPU time 460.56 seconds
Started Jul 25 06:42:33 PM PDT 24
Finished Jul 25 06:50:14 PM PDT 24
Peak memory 201708 kb
Host smart-955bfa69-9511-4c2e-9f6b-c1778b53f5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838754008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3838754008
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.4266882392
Short name T739
Test name
Test status
Simulation time 30138896365 ps
CPU time 35.16 seconds
Started Jul 25 06:42:37 PM PDT 24
Finished Jul 25 06:43:12 PM PDT 24
Peak memory 201088 kb
Host smart-61eedac1-6352-49eb-953e-494a173d2381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266882392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.4266882392
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.254799897
Short name T760
Test name
Test status
Simulation time 3347762210 ps
CPU time 4.52 seconds
Started Jul 25 06:42:37 PM PDT 24
Finished Jul 25 06:42:42 PM PDT 24
Peak memory 201092 kb
Host smart-f800807d-af23-4d18-aedc-b3196b1c10d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254799897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.254799897
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1929483594
Short name T773
Test name
Test status
Simulation time 6004048068 ps
CPU time 14.67 seconds
Started Jul 25 06:42:24 PM PDT 24
Finished Jul 25 06:42:39 PM PDT 24
Peak memory 201100 kb
Host smart-7921b414-59ac-4da3-ad49-f4c18ada3f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929483594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1929483594
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2023012547
Short name T468
Test name
Test status
Simulation time 44505968181 ps
CPU time 31.17 seconds
Started Jul 25 06:42:39 PM PDT 24
Finished Jul 25 06:43:10 PM PDT 24
Peak memory 201104 kb
Host smart-6b79862c-d9cd-4660-a22d-4bfb1c327bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023012547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2023012547
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1310682993
Short name T342
Test name
Test status
Simulation time 65665627333 ps
CPU time 214.57 seconds
Started Jul 25 06:42:39 PM PDT 24
Finished Jul 25 06:46:13 PM PDT 24
Peak memory 210076 kb
Host smart-18c17c76-1e2b-4173-9951-ca9a33eda7b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310682993 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1310682993
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2569001572
Short name T570
Test name
Test status
Simulation time 402205239 ps
CPU time 0.81 seconds
Started Jul 25 06:42:45 PM PDT 24
Finished Jul 25 06:42:46 PM PDT 24
Peak memory 200956 kb
Host smart-b864545f-2219-4c98-bd2d-8101e5ad5877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569001572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2569001572
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1203796203
Short name T726
Test name
Test status
Simulation time 330105851638 ps
CPU time 222.17 seconds
Started Jul 25 06:42:38 PM PDT 24
Finished Jul 25 06:46:20 PM PDT 24
Peak memory 201268 kb
Host smart-02c58358-fcfc-44af-9610-a8c09ff0486d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203796203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1203796203
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3967581955
Short name T179
Test name
Test status
Simulation time 511149859676 ps
CPU time 216.84 seconds
Started Jul 25 06:42:41 PM PDT 24
Finished Jul 25 06:46:18 PM PDT 24
Peak memory 201204 kb
Host smart-5d21194f-364d-41cb-866b-1708e21930df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967581955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3967581955
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.228899454
Short name T450
Test name
Test status
Simulation time 493158641128 ps
CPU time 123.76 seconds
Started Jul 25 06:42:38 PM PDT 24
Finished Jul 25 06:44:42 PM PDT 24
Peak memory 201240 kb
Host smart-0bb42600-83e0-4c0b-a5b5-62c381051261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228899454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.228899454
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2901597050
Short name T478
Test name
Test status
Simulation time 498883100672 ps
CPU time 1247.65 seconds
Started Jul 25 06:42:39 PM PDT 24
Finished Jul 25 07:03:27 PM PDT 24
Peak memory 201272 kb
Host smart-89fbb54e-0869-4c52-b4c5-624d269de056
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901597050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2901597050
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.218808045
Short name T512
Test name
Test status
Simulation time 330916477051 ps
CPU time 789.83 seconds
Started Jul 25 06:42:39 PM PDT 24
Finished Jul 25 06:55:49 PM PDT 24
Peak memory 201232 kb
Host smart-73368db4-10ea-492c-a2b9-3226a3190c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218808045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.218808045
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.458263079
Short name T525
Test name
Test status
Simulation time 331323606639 ps
CPU time 577.39 seconds
Started Jul 25 06:42:38 PM PDT 24
Finished Jul 25 06:52:15 PM PDT 24
Peak memory 201192 kb
Host smart-6c47c122-625a-4330-876b-90a033ccdbe4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=458263079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.458263079
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1937198657
Short name T557
Test name
Test status
Simulation time 198164599833 ps
CPU time 211.55 seconds
Started Jul 25 06:42:39 PM PDT 24
Finished Jul 25 06:46:11 PM PDT 24
Peak memory 201212 kb
Host smart-9cb3f4c6-60fc-4747-8114-efb7e3631aca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937198657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1937198657
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3992311655
Short name T207
Test name
Test status
Simulation time 102671720281 ps
CPU time 343.95 seconds
Started Jul 25 06:42:45 PM PDT 24
Finished Jul 25 06:48:29 PM PDT 24
Peak memory 201696 kb
Host smart-5f422719-40f3-4880-aed8-54c0cdb884dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992311655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3992311655
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1113711992
Short name T517
Test name
Test status
Simulation time 28866184450 ps
CPU time 68.02 seconds
Started Jul 25 06:42:44 PM PDT 24
Finished Jul 25 06:43:52 PM PDT 24
Peak memory 201068 kb
Host smart-4664fa33-be7b-4c2e-a2c7-f78889ddabcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113711992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1113711992
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3116689031
Short name T432
Test name
Test status
Simulation time 4623619266 ps
CPU time 3.33 seconds
Started Jul 25 06:42:39 PM PDT 24
Finished Jul 25 06:42:42 PM PDT 24
Peak memory 201056 kb
Host smart-c0ef0f04-0190-4308-a0cc-2b5bc33dcc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116689031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3116689031
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.4043989348
Short name T708
Test name
Test status
Simulation time 5818278786 ps
CPU time 7.33 seconds
Started Jul 25 06:42:38 PM PDT 24
Finished Jul 25 06:42:46 PM PDT 24
Peak memory 201056 kb
Host smart-97dec2ba-c6d0-475b-b1a5-9957da6a68ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043989348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.4043989348
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1248211449
Short name T787
Test name
Test status
Simulation time 482359450 ps
CPU time 1.69 seconds
Started Jul 25 06:42:51 PM PDT 24
Finished Jul 25 06:42:53 PM PDT 24
Peak memory 201040 kb
Host smart-1517e2fb-b3e7-4daa-b2b5-ac2cabcdd3cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248211449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1248211449
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3916363903
Short name T248
Test name
Test status
Simulation time 166270368962 ps
CPU time 105.14 seconds
Started Jul 25 06:42:51 PM PDT 24
Finished Jul 25 06:44:36 PM PDT 24
Peak memory 201292 kb
Host smart-0d234cf3-7c91-4cf7-9130-57b2b2e1d0fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916363903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3916363903
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3890243174
Short name T323
Test name
Test status
Simulation time 169441799769 ps
CPU time 381.87 seconds
Started Jul 25 06:42:53 PM PDT 24
Finished Jul 25 06:49:15 PM PDT 24
Peak memory 201220 kb
Host smart-1a6cc4d5-128a-45f5-a59c-1946f8ebb4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890243174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3890243174
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1202865605
Short name T324
Test name
Test status
Simulation time 159985529574 ps
CPU time 48.05 seconds
Started Jul 25 06:42:47 PM PDT 24
Finished Jul 25 06:43:35 PM PDT 24
Peak memory 201312 kb
Host smart-10d6ad95-8cf7-4515-90d3-fb43da3b98f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202865605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1202865605
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3696534186
Short name T2
Test name
Test status
Simulation time 162897388492 ps
CPU time 107.16 seconds
Started Jul 25 06:42:44 PM PDT 24
Finished Jul 25 06:44:32 PM PDT 24
Peak memory 201332 kb
Host smart-a1ba8cb6-7b26-4b36-9070-ac0196f0dc92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696534186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3696534186
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3240797912
Short name T3
Test name
Test status
Simulation time 479739207457 ps
CPU time 1119.96 seconds
Started Jul 25 06:42:47 PM PDT 24
Finished Jul 25 07:01:27 PM PDT 24
Peak memory 201216 kb
Host smart-2043dfb2-ec5b-4790-85af-f8250505592a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240797912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3240797912
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1662934552
Short name T407
Test name
Test status
Simulation time 319356333412 ps
CPU time 367.2 seconds
Started Jul 25 06:42:43 PM PDT 24
Finished Jul 25 06:48:50 PM PDT 24
Peak memory 201200 kb
Host smart-f7f58375-5e59-473b-9866-562855b85428
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662934552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1662934552
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.657285629
Short name T304
Test name
Test status
Simulation time 430497584693 ps
CPU time 838.39 seconds
Started Jul 25 06:42:44 PM PDT 24
Finished Jul 25 06:56:43 PM PDT 24
Peak memory 201208 kb
Host smart-1833f9be-4226-4f44-9094-718a7ac803ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657285629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.657285629
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1990377461
Short name T725
Test name
Test status
Simulation time 588500701369 ps
CPU time 689.68 seconds
Started Jul 25 06:42:47 PM PDT 24
Finished Jul 25 06:54:17 PM PDT 24
Peak memory 201300 kb
Host smart-dd229ad7-e2c0-44a0-99dc-5215b846350a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990377461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1990377461
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3846302875
Short name T688
Test name
Test status
Simulation time 126730266873 ps
CPU time 484.77 seconds
Started Jul 25 06:42:54 PM PDT 24
Finished Jul 25 06:50:59 PM PDT 24
Peak memory 201692 kb
Host smart-ae8177f5-d999-4605-acda-7576ba12942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846302875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3846302875
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2064232082
Short name T193
Test name
Test status
Simulation time 44486013649 ps
CPU time 23.18 seconds
Started Jul 25 06:42:55 PM PDT 24
Finished Jul 25 06:43:19 PM PDT 24
Peak memory 201100 kb
Host smart-e1d60336-6f55-4b55-ab74-ec385d75ae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064232082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2064232082
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.237924451
Short name T673
Test name
Test status
Simulation time 4426742471 ps
CPU time 11.06 seconds
Started Jul 25 06:42:55 PM PDT 24
Finished Jul 25 06:43:06 PM PDT 24
Peak memory 201060 kb
Host smart-95df65bb-b366-414a-bfaf-0a979051f4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237924451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.237924451
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3569687
Short name T373
Test name
Test status
Simulation time 5702852566 ps
CPU time 13.47 seconds
Started Jul 25 06:42:46 PM PDT 24
Finished Jul 25 06:42:59 PM PDT 24
Peak memory 201040 kb
Host smart-47feb6a1-35d9-4336-9e54-786c34c6f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3569687
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2547163136
Short name T371
Test name
Test status
Simulation time 37671517675 ps
CPU time 77.83 seconds
Started Jul 25 06:42:52 PM PDT 24
Finished Jul 25 06:44:10 PM PDT 24
Peak memory 201112 kb
Host smart-66def24c-8f4e-4cbb-9661-629e0228bb89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547163136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2547163136
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.385804701
Short name T87
Test name
Test status
Simulation time 426079064069 ps
CPU time 235.87 seconds
Started Jul 25 06:42:52 PM PDT 24
Finished Jul 25 06:46:48 PM PDT 24
Peak memory 209596 kb
Host smart-d0b9806c-13e5-435d-913c-c7f387647a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385804701 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.385804701
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3196232182
Short name T583
Test name
Test status
Simulation time 356321735 ps
CPU time 1.43 seconds
Started Jul 25 06:43:03 PM PDT 24
Finished Jul 25 06:43:04 PM PDT 24
Peak memory 201036 kb
Host smart-1ade5b35-4b76-4ada-a238-f91abe0ca648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196232182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3196232182
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1777437580
Short name T82
Test name
Test status
Simulation time 199716662571 ps
CPU time 435.66 seconds
Started Jul 25 06:42:59 PM PDT 24
Finished Jul 25 06:50:15 PM PDT 24
Peak memory 201224 kb
Host smart-796ddbe5-bf98-4418-8ebd-d0b4ea75e943
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777437580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1777437580
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.409479212
Short name T170
Test name
Test status
Simulation time 340525986410 ps
CPU time 193.66 seconds
Started Jul 25 06:42:59 PM PDT 24
Finished Jul 25 06:46:13 PM PDT 24
Peak memory 201256 kb
Host smart-f339d439-c374-478d-9b9c-06bfcebfceec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409479212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.409479212
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.4008762578
Short name T724
Test name
Test status
Simulation time 494004440622 ps
CPU time 231.25 seconds
Started Jul 25 06:42:53 PM PDT 24
Finished Jul 25 06:46:45 PM PDT 24
Peak memory 201268 kb
Host smart-1b52f74b-eb38-42ce-99d6-f375c8c28649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008762578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4008762578
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3386146543
Short name T573
Test name
Test status
Simulation time 493598534063 ps
CPU time 317.82 seconds
Started Jul 25 06:42:52 PM PDT 24
Finished Jul 25 06:48:10 PM PDT 24
Peak memory 201216 kb
Host smart-f1bb1c04-1e4a-48b2-9900-9b7dba8cb4d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386146543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3386146543
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3568224799
Short name T679
Test name
Test status
Simulation time 165943138591 ps
CPU time 381.15 seconds
Started Jul 25 06:42:54 PM PDT 24
Finished Jul 25 06:49:15 PM PDT 24
Peak memory 201252 kb
Host smart-dc61e745-1ab1-4682-b2dc-ebffdf6b1ebc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568224799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3568224799
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1808150927
Short name T606
Test name
Test status
Simulation time 178791925470 ps
CPU time 440.46 seconds
Started Jul 25 06:42:57 PM PDT 24
Finished Jul 25 06:50:18 PM PDT 24
Peak memory 201252 kb
Host smart-698adea5-2222-4eaf-9549-4c575d9d142c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808150927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1808150927
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3374311033
Short name T504
Test name
Test status
Simulation time 611921777772 ps
CPU time 353.84 seconds
Started Jul 25 06:42:58 PM PDT 24
Finished Jul 25 06:48:52 PM PDT 24
Peak memory 201280 kb
Host smart-3ff0859d-1c7f-415b-b08b-0fcd0f995627
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374311033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3374311033
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1030715337
Short name T47
Test name
Test status
Simulation time 107828376552 ps
CPU time 416.71 seconds
Started Jul 25 06:42:57 PM PDT 24
Finished Jul 25 06:49:54 PM PDT 24
Peak memory 201640 kb
Host smart-79799ee4-7ca3-48ca-ae54-8a3704f6fa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030715337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1030715337
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1133073553
Short name T715
Test name
Test status
Simulation time 24897631278 ps
CPU time 29.69 seconds
Started Jul 25 06:42:56 PM PDT 24
Finished Jul 25 06:43:26 PM PDT 24
Peak memory 201104 kb
Host smart-2016c9c6-a28e-44a3-b564-0fc74474baf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133073553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1133073553
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1473950136
Short name T611
Test name
Test status
Simulation time 3401776084 ps
CPU time 2.93 seconds
Started Jul 25 06:42:58 PM PDT 24
Finished Jul 25 06:43:01 PM PDT 24
Peak memory 201080 kb
Host smart-11cf3413-4b91-48bf-8d6c-dc62b95d8b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473950136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1473950136
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.551963665
Short name T483
Test name
Test status
Simulation time 5952695027 ps
CPU time 4.3 seconds
Started Jul 25 06:42:51 PM PDT 24
Finished Jul 25 06:42:56 PM PDT 24
Peak memory 201088 kb
Host smart-0851fa76-370c-4311-a5b4-fc3f2b4b171b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551963665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.551963665
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2848552551
Short name T370
Test name
Test status
Simulation time 281078978 ps
CPU time 1.28 seconds
Started Jul 25 06:43:10 PM PDT 24
Finished Jul 25 06:43:11 PM PDT 24
Peak memory 201040 kb
Host smart-9f7787b5-98a7-4ac8-92e3-509e2e710d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848552551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2848552551
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.384428154
Short name T225
Test name
Test status
Simulation time 544448365911 ps
CPU time 606.28 seconds
Started Jul 25 06:43:03 PM PDT 24
Finished Jul 25 06:53:10 PM PDT 24
Peak memory 201240 kb
Host smart-752376ce-6f35-4322-92e1-c961f1a3b447
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384428154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.384428154
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2369363010
Short name T183
Test name
Test status
Simulation time 322814855556 ps
CPU time 103.55 seconds
Started Jul 25 06:43:01 PM PDT 24
Finished Jul 25 06:44:45 PM PDT 24
Peak memory 201244 kb
Host smart-35e5489f-6bea-44fa-b8cf-8c9143cbad42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369363010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2369363010
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1556778864
Short name T144
Test name
Test status
Simulation time 497167666221 ps
CPU time 104.95 seconds
Started Jul 25 06:43:03 PM PDT 24
Finished Jul 25 06:44:48 PM PDT 24
Peak memory 201204 kb
Host smart-265f615d-a024-409f-afbf-2fb19a0c0619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556778864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1556778864
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.470116658
Short name T386
Test name
Test status
Simulation time 161405837442 ps
CPU time 178.55 seconds
Started Jul 25 06:43:05 PM PDT 24
Finished Jul 25 06:46:04 PM PDT 24
Peak memory 201224 kb
Host smart-0f443873-4afa-4644-bcb8-0b0200e1ce6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=470116658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.470116658
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.970173651
Short name T308
Test name
Test status
Simulation time 325087833279 ps
CPU time 178.6 seconds
Started Jul 25 06:43:03 PM PDT 24
Finished Jul 25 06:46:02 PM PDT 24
Peak memory 201332 kb
Host smart-d7b68fd0-9d84-4fdf-acad-f212ed549a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970173651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.970173651
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.4082239981
Short name T365
Test name
Test status
Simulation time 168547891563 ps
CPU time 181.37 seconds
Started Jul 25 06:43:03 PM PDT 24
Finished Jul 25 06:46:04 PM PDT 24
Peak memory 201272 kb
Host smart-0958cada-d2c4-4b66-abc7-6088bab29253
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082239981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.4082239981
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1764059969
Short name T300
Test name
Test status
Simulation time 656019189298 ps
CPU time 1512.6 seconds
Started Jul 25 06:43:04 PM PDT 24
Finished Jul 25 07:08:17 PM PDT 24
Peak memory 201308 kb
Host smart-54376192-0bc8-47b8-a1e0-83269d3c1d4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764059969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1764059969
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.199140817
Short name T727
Test name
Test status
Simulation time 392275131514 ps
CPU time 193.7 seconds
Started Jul 25 06:43:04 PM PDT 24
Finished Jul 25 06:46:18 PM PDT 24
Peak memory 201244 kb
Host smart-c2d6ea24-00a2-4de8-82df-1eacb63cbd34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199140817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.199140817
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1065276354
Short name T701
Test name
Test status
Simulation time 107417057878 ps
CPU time 320.57 seconds
Started Jul 25 06:43:03 PM PDT 24
Finished Jul 25 06:48:24 PM PDT 24
Peak memory 201684 kb
Host smart-07564e86-9faf-4409-b83d-93b59c776048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065276354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1065276354
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1009139596
Short name T430
Test name
Test status
Simulation time 42012732674 ps
CPU time 97.48 seconds
Started Jul 25 06:43:06 PM PDT 24
Finished Jul 25 06:44:44 PM PDT 24
Peak memory 201056 kb
Host smart-e1ced91e-b2f8-47ec-9469-3600c428cdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009139596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1009139596
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2080711905
Short name T366
Test name
Test status
Simulation time 4930442431 ps
CPU time 3.4 seconds
Started Jul 25 06:43:05 PM PDT 24
Finished Jul 25 06:43:08 PM PDT 24
Peak memory 201056 kb
Host smart-a3d226cc-f982-455b-9f14-9f9af4a2783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080711905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2080711905
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2095457157
Short name T602
Test name
Test status
Simulation time 5668939111 ps
CPU time 13.76 seconds
Started Jul 25 06:43:05 PM PDT 24
Finished Jul 25 06:43:19 PM PDT 24
Peak memory 201096 kb
Host smart-f94d4c86-deda-40b9-90d6-ec43fc0cc275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095457157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2095457157
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.4119206072
Short name T582
Test name
Test status
Simulation time 336059706425 ps
CPU time 154.86 seconds
Started Jul 25 06:43:12 PM PDT 24
Finished Jul 25 06:45:47 PM PDT 24
Peak memory 201220 kb
Host smart-cd30c7c0-8c04-4fcf-8d70-1ad8df6ede80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119206072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.4119206072
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3835127049
Short name T33
Test name
Test status
Simulation time 228275664160 ps
CPU time 88.62 seconds
Started Jul 25 06:43:04 PM PDT 24
Finished Jul 25 06:44:32 PM PDT 24
Peak memory 209600 kb
Host smart-76987bb3-3df1-41b8-8e01-ebd61a6e28b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835127049 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3835127049
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2192848474
Short name T418
Test name
Test status
Simulation time 356414564 ps
CPU time 0.82 seconds
Started Jul 25 06:43:17 PM PDT 24
Finished Jul 25 06:43:18 PM PDT 24
Peak memory 200976 kb
Host smart-07f38697-d1eb-4142-8a81-0ce952401cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192848474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2192848474
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3779162411
Short name T276
Test name
Test status
Simulation time 162867585597 ps
CPU time 369.84 seconds
Started Jul 25 06:43:17 PM PDT 24
Finished Jul 25 06:49:27 PM PDT 24
Peak memory 201372 kb
Host smart-e357c9f8-0737-4546-bc72-44debc9299cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779162411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3779162411
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2019974034
Short name T215
Test name
Test status
Simulation time 496757129890 ps
CPU time 140.04 seconds
Started Jul 25 06:43:10 PM PDT 24
Finished Jul 25 06:45:30 PM PDT 24
Peak memory 201304 kb
Host smart-bbcbdf4f-08a8-4c43-bb6a-367a92d30cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019974034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2019974034
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1569577205
Short name T655
Test name
Test status
Simulation time 321110112109 ps
CPU time 184.23 seconds
Started Jul 25 06:43:12 PM PDT 24
Finished Jul 25 06:46:16 PM PDT 24
Peak memory 201208 kb
Host smart-7a6e39a4-a9ea-4adf-8f3c-9d5224df065c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569577205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1569577205
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3341518465
Short name T328
Test name
Test status
Simulation time 330176975973 ps
CPU time 715.21 seconds
Started Jul 25 06:43:10 PM PDT 24
Finished Jul 25 06:55:06 PM PDT 24
Peak memory 201284 kb
Host smart-75b53789-dcbb-4a32-9ac3-e37a97aad91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341518465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3341518465
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.192731917
Short name T417
Test name
Test status
Simulation time 159583798632 ps
CPU time 176.08 seconds
Started Jul 25 06:43:10 PM PDT 24
Finished Jul 25 06:46:06 PM PDT 24
Peak memory 201252 kb
Host smart-6366a9de-699b-4155-b907-260b45c75942
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=192731917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.192731917
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1079107246
Short name T252
Test name
Test status
Simulation time 247213713396 ps
CPU time 78.31 seconds
Started Jul 25 06:43:10 PM PDT 24
Finished Jul 25 06:44:29 PM PDT 24
Peak memory 201228 kb
Host smart-3a8a30a0-88ca-47be-b77a-205387b3a900
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079107246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1079107246
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3232569006
Short name T734
Test name
Test status
Simulation time 411438911502 ps
CPU time 236.05 seconds
Started Jul 25 06:43:16 PM PDT 24
Finished Jul 25 06:47:13 PM PDT 24
Peak memory 201252 kb
Host smart-84f481d9-eeca-4efe-a302-6cc5b6638e09
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232569006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3232569006
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.968510266
Short name T471
Test name
Test status
Simulation time 76003153044 ps
CPU time 387.87 seconds
Started Jul 25 06:43:16 PM PDT 24
Finished Jul 25 06:49:44 PM PDT 24
Peak memory 201688 kb
Host smart-b463bd06-d4d1-479b-a19f-16e250e64b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968510266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.968510266
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.671765206
Short name T479
Test name
Test status
Simulation time 41960169056 ps
CPU time 24.73 seconds
Started Jul 25 06:43:17 PM PDT 24
Finished Jul 25 06:43:42 PM PDT 24
Peak memory 201100 kb
Host smart-065210c8-a97a-4639-9040-f7dce5335554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671765206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.671765206
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.4184436015
Short name T108
Test name
Test status
Simulation time 5012220813 ps
CPU time 6.7 seconds
Started Jul 25 06:43:17 PM PDT 24
Finished Jul 25 06:43:24 PM PDT 24
Peak memory 201004 kb
Host smart-be47b491-925e-4ea2-8fcf-15c86438fc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184436015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.4184436015
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.171275959
Short name T496
Test name
Test status
Simulation time 5803994273 ps
CPU time 4.14 seconds
Started Jul 25 06:43:09 PM PDT 24
Finished Jul 25 06:43:13 PM PDT 24
Peak memory 201092 kb
Host smart-fc06fc1c-d7fd-4ac9-ba79-23ef9ef16836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171275959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.171275959
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3755444354
Short name T530
Test name
Test status
Simulation time 440260247676 ps
CPU time 820.47 seconds
Started Jul 25 06:43:17 PM PDT 24
Finished Jul 25 06:56:57 PM PDT 24
Peak memory 209848 kb
Host smart-06d68fb6-0681-4981-923c-969c1a2c59c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755444354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3755444354
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3895946283
Short name T363
Test name
Test status
Simulation time 286285561 ps
CPU time 0.95 seconds
Started Jul 25 06:43:22 PM PDT 24
Finished Jul 25 06:43:23 PM PDT 24
Peak memory 201012 kb
Host smart-a984052a-2974-4666-b659-7e02f994d2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895946283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3895946283
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2845710511
Short name T493
Test name
Test status
Simulation time 198867343480 ps
CPU time 224.36 seconds
Started Jul 25 06:43:24 PM PDT 24
Finished Jul 25 06:47:08 PM PDT 24
Peak memory 201284 kb
Host smart-17b4ebfe-3526-4473-8f3c-6951d3bbebf6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845710511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2845710511
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1865806591
Short name T241
Test name
Test status
Simulation time 160075602538 ps
CPU time 106.05 seconds
Started Jul 25 06:43:24 PM PDT 24
Finished Jul 25 06:45:10 PM PDT 24
Peak memory 201268 kb
Host smart-8e92b13e-c134-40c2-bce3-f41cc96bcb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865806591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1865806591
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1759465624
Short name T509
Test name
Test status
Simulation time 167294906129 ps
CPU time 389.52 seconds
Started Jul 25 06:43:24 PM PDT 24
Finished Jul 25 06:49:54 PM PDT 24
Peak memory 201240 kb
Host smart-21ded47f-91e5-493d-a38c-0098bd8d1e86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759465624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1759465624
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.478317150
Short name T256
Test name
Test status
Simulation time 332262819166 ps
CPU time 195.6 seconds
Started Jul 25 06:43:17 PM PDT 24
Finished Jul 25 06:46:33 PM PDT 24
Peak memory 201216 kb
Host smart-20461054-c0fe-4f27-b927-aba011aebd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478317150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.478317150
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.655448571
Short name T569
Test name
Test status
Simulation time 164456309253 ps
CPU time 25.97 seconds
Started Jul 25 06:43:24 PM PDT 24
Finished Jul 25 06:43:50 PM PDT 24
Peak memory 201220 kb
Host smart-2317a408-98b4-4024-a43d-0d17e3e66083
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=655448571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.655448571
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1453828167
Short name T545
Test name
Test status
Simulation time 388793902280 ps
CPU time 826.85 seconds
Started Jul 25 06:43:22 PM PDT 24
Finished Jul 25 06:57:09 PM PDT 24
Peak memory 201240 kb
Host smart-72ef3af9-ea3a-43fa-a3ee-dcd1cf1759b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453828167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1453828167
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2637676413
Short name T476
Test name
Test status
Simulation time 409776232994 ps
CPU time 864.84 seconds
Started Jul 25 06:43:22 PM PDT 24
Finished Jul 25 06:57:47 PM PDT 24
Peak memory 201212 kb
Host smart-32bd8a70-c319-4b10-935f-19c7bffaa4f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637676413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2637676413
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1677226289
Short name T341
Test name
Test status
Simulation time 87280276711 ps
CPU time 291.83 seconds
Started Jul 25 06:43:21 PM PDT 24
Finished Jul 25 06:48:13 PM PDT 24
Peak memory 201664 kb
Host smart-788d03ec-2c97-469d-9546-d94254ff5e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677226289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1677226289
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.939362497
Short name T513
Test name
Test status
Simulation time 26446012009 ps
CPU time 7.57 seconds
Started Jul 25 06:43:22 PM PDT 24
Finished Jul 25 06:43:30 PM PDT 24
Peak memory 201064 kb
Host smart-c3df0322-bd3e-44e9-9add-ab7ac041cc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939362497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.939362497
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.390302405
Short name T695
Test name
Test status
Simulation time 5350179057 ps
CPU time 12.61 seconds
Started Jul 25 06:43:22 PM PDT 24
Finished Jul 25 06:43:35 PM PDT 24
Peak memory 201052 kb
Host smart-7973975d-2ff3-491e-b901-b94442cb14aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390302405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.390302405
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2280118704
Short name T577
Test name
Test status
Simulation time 5714714661 ps
CPU time 14.23 seconds
Started Jul 25 06:43:17 PM PDT 24
Finished Jul 25 06:43:31 PM PDT 24
Peak memory 201076 kb
Host smart-7f4b7840-159d-4db9-9ae8-435fbacb186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280118704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2280118704
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.589274109
Short name T687
Test name
Test status
Simulation time 205134748167 ps
CPU time 234.48 seconds
Started Jul 25 06:43:22 PM PDT 24
Finished Jul 25 06:47:17 PM PDT 24
Peak memory 201272 kb
Host smart-3a0a072c-a44b-4a2f-9b23-d05aefc25c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589274109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
589274109
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3040566142
Short name T22
Test name
Test status
Simulation time 188744613188 ps
CPU time 96.94 seconds
Started Jul 25 06:43:23 PM PDT 24
Finished Jul 25 06:45:00 PM PDT 24
Peak memory 209528 kb
Host smart-91bd3c45-43b1-49ab-b84e-28930c3e6062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040566142 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3040566142
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3060984249
Short name T358
Test name
Test status
Simulation time 340331080 ps
CPU time 1.34 seconds
Started Jul 25 06:43:37 PM PDT 24
Finished Jul 25 06:43:38 PM PDT 24
Peak memory 201028 kb
Host smart-d68dcbe4-a182-41fe-8092-11561c4998e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060984249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3060984249
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4057620083
Short name T315
Test name
Test status
Simulation time 334957263311 ps
CPU time 410.87 seconds
Started Jul 25 06:43:31 PM PDT 24
Finished Jul 25 06:50:22 PM PDT 24
Peak memory 201244 kb
Host smart-edfdc2b4-0cab-470b-b93f-99bfa3ae9e2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057620083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4057620083
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1845762127
Short name T307
Test name
Test status
Simulation time 183483896211 ps
CPU time 42.56 seconds
Started Jul 25 06:43:31 PM PDT 24
Finished Jul 25 06:44:13 PM PDT 24
Peak memory 201256 kb
Host smart-3ebb4a17-f1ff-42ac-875e-d5e2f9e565b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845762127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1845762127
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1995957403
Short name T12
Test name
Test status
Simulation time 163993179350 ps
CPU time 366.96 seconds
Started Jul 25 06:43:31 PM PDT 24
Finished Jul 25 06:49:38 PM PDT 24
Peak memory 201240 kb
Host smart-72c95ee8-4da9-468d-8d81-bfe32685df3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995957403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1995957403
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.95891050
Short name T645
Test name
Test status
Simulation time 161588556688 ps
CPU time 383.98 seconds
Started Jul 25 06:43:32 PM PDT 24
Finished Jul 25 06:49:56 PM PDT 24
Peak memory 201204 kb
Host smart-e02ee8e8-4c38-4155-b7c7-b1d3e3513bf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=95891050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt
_fixed.95891050
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.925291589
Short name T325
Test name
Test status
Simulation time 491973506773 ps
CPU time 1184.13 seconds
Started Jul 25 06:43:22 PM PDT 24
Finished Jul 25 07:03:06 PM PDT 24
Peak memory 201168 kb
Host smart-65f9f7a9-4fee-4920-8a0f-cda964f00d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925291589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.925291589
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.4212515883
Short name T141
Test name
Test status
Simulation time 485782450232 ps
CPU time 208.37 seconds
Started Jul 25 06:43:33 PM PDT 24
Finished Jul 25 06:47:01 PM PDT 24
Peak memory 201224 kb
Host smart-b8d76cf8-cfa4-4e47-a1a0-738ada698645
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212515883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.4212515883
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3816155336
Short name T720
Test name
Test status
Simulation time 573433336377 ps
CPU time 691.94 seconds
Started Jul 25 06:43:30 PM PDT 24
Finished Jul 25 06:55:03 PM PDT 24
Peak memory 201156 kb
Host smart-0997a789-9770-4dd3-bcdd-3db990a5b103
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816155336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3816155336
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2986467946
Short name T41
Test name
Test status
Simulation time 601388028035 ps
CPU time 190.33 seconds
Started Jul 25 06:43:31 PM PDT 24
Finished Jul 25 06:46:42 PM PDT 24
Peak memory 201280 kb
Host smart-9e909e92-9df8-4d0b-afbd-4e2ae33b81db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986467946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2986467946
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3306640831
Short name T636
Test name
Test status
Simulation time 66223383314 ps
CPU time 215.08 seconds
Started Jul 25 06:43:38 PM PDT 24
Finished Jul 25 06:47:13 PM PDT 24
Peak memory 201736 kb
Host smart-da56d447-3125-4eb6-a7a9-56c9ec7c1ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306640831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3306640831
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3480962918
Short name T490
Test name
Test status
Simulation time 32583386733 ps
CPU time 21.98 seconds
Started Jul 25 06:43:37 PM PDT 24
Finished Jul 25 06:43:59 PM PDT 24
Peak memory 201044 kb
Host smart-cfd91c5f-3683-48aa-8268-165c54811db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480962918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3480962918
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1731925802
Short name T383
Test name
Test status
Simulation time 4736704136 ps
CPU time 11.91 seconds
Started Jul 25 06:43:31 PM PDT 24
Finished Jul 25 06:43:43 PM PDT 24
Peak memory 201104 kb
Host smart-37e373ae-2373-4a27-9df2-ad56bb6a0241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731925802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1731925802
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1636222576
Short name T426
Test name
Test status
Simulation time 5904882328 ps
CPU time 2.5 seconds
Started Jul 25 06:43:59 PM PDT 24
Finished Jul 25 06:44:02 PM PDT 24
Peak memory 201036 kb
Host smart-aa2773af-55b1-42de-99a3-654f50e792f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636222576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1636222576
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2956695507
Short name T201
Test name
Test status
Simulation time 114582630082 ps
CPU time 447.26 seconds
Started Jul 25 06:43:37 PM PDT 24
Finished Jul 25 06:51:04 PM PDT 24
Peak memory 209808 kb
Host smart-cce26f3d-8ba0-4146-8cb1-cd023b0ba4c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956695507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2956695507
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1819274796
Short name T628
Test name
Test status
Simulation time 174964965115 ps
CPU time 166.24 seconds
Started Jul 25 06:43:38 PM PDT 24
Finished Jul 25 06:46:24 PM PDT 24
Peak memory 210048 kb
Host smart-3f79137f-8618-4616-8bbc-51d80671b49c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819274796 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1819274796
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.119631466
Short name T470
Test name
Test status
Simulation time 527056831 ps
CPU time 1.23 seconds
Started Jul 25 06:43:43 PM PDT 24
Finished Jul 25 06:43:44 PM PDT 24
Peak memory 201012 kb
Host smart-0b64d2b0-a9a6-440d-9259-0636f8b159cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119631466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.119631466
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.812764491
Short name T660
Test name
Test status
Simulation time 166177836560 ps
CPU time 359.63 seconds
Started Jul 25 06:43:45 PM PDT 24
Finished Jul 25 06:49:45 PM PDT 24
Peak memory 201216 kb
Host smart-733538a7-804b-4c96-b40b-1c3887c2b786
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812764491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.812764491
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1950185383
Short name T683
Test name
Test status
Simulation time 167193847603 ps
CPU time 102.14 seconds
Started Jul 25 06:43:45 PM PDT 24
Finished Jul 25 06:45:27 PM PDT 24
Peak memory 201220 kb
Host smart-d41f20f0-6337-49f2-b443-3f0b9612f56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950185383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1950185383
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.34410255
Short name T317
Test name
Test status
Simulation time 326071671917 ps
CPU time 794.87 seconds
Started Jul 25 06:43:36 PM PDT 24
Finished Jul 25 06:56:51 PM PDT 24
Peak memory 201228 kb
Host smart-fd6c4eee-66e7-4928-b83d-ef78172e5041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34410255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.34410255
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3709332056
Short name T497
Test name
Test status
Simulation time 503165946672 ps
CPU time 1193.29 seconds
Started Jul 25 06:43:39 PM PDT 24
Finished Jul 25 07:03:33 PM PDT 24
Peak memory 201268 kb
Host smart-91a55690-f9e2-424a-9490-685a859d7ab7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709332056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3709332056
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2089468734
Short name T568
Test name
Test status
Simulation time 326224362465 ps
CPU time 379.03 seconds
Started Jul 25 06:43:37 PM PDT 24
Finished Jul 25 06:49:57 PM PDT 24
Peak memory 201220 kb
Host smart-68cc277d-44fe-4727-a53b-d0780a30ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089468734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2089468734
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1984999053
Short name T623
Test name
Test status
Simulation time 496652169980 ps
CPU time 648.93 seconds
Started Jul 25 06:43:38 PM PDT 24
Finished Jul 25 06:54:27 PM PDT 24
Peak memory 201220 kb
Host smart-eb274886-9892-416c-bfa8-8ae679ddbd71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984999053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1984999053
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3321273656
Short name T233
Test name
Test status
Simulation time 178222944059 ps
CPU time 392.22 seconds
Started Jul 25 06:43:37 PM PDT 24
Finished Jul 25 06:50:10 PM PDT 24
Peak memory 201244 kb
Host smart-3c1f71cc-8815-4aa1-b042-bdeed423bf97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321273656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3321273656
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3089425133
Short name T638
Test name
Test status
Simulation time 598083021778 ps
CPU time 745.27 seconds
Started Jul 25 06:43:36 PM PDT 24
Finished Jul 25 06:56:02 PM PDT 24
Peak memory 201208 kb
Host smart-282d60ca-9f0a-4533-9362-506d54634201
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089425133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3089425133
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3431024371
Short name T425
Test name
Test status
Simulation time 91045592552 ps
CPU time 387.16 seconds
Started Jul 25 06:43:44 PM PDT 24
Finished Jul 25 06:50:11 PM PDT 24
Peak memory 201688 kb
Host smart-0b230888-e6b8-4733-a04a-673b3c5deff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431024371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3431024371
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2514509497
Short name T747
Test name
Test status
Simulation time 24399819081 ps
CPU time 11.99 seconds
Started Jul 25 06:43:45 PM PDT 24
Finished Jul 25 06:43:57 PM PDT 24
Peak memory 201104 kb
Host smart-09aae7d5-5be0-415d-a5a9-16c5eb78d8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514509497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2514509497
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.332333672
Short name T774
Test name
Test status
Simulation time 3600231237 ps
CPU time 8.81 seconds
Started Jul 25 06:43:44 PM PDT 24
Finished Jul 25 06:43:53 PM PDT 24
Peak memory 200988 kb
Host smart-36780bc3-821b-47e6-b15a-2170add18a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332333672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.332333672
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.577078500
Short name T438
Test name
Test status
Simulation time 5756568145 ps
CPU time 14.92 seconds
Started Jul 25 06:43:38 PM PDT 24
Finished Jul 25 06:43:53 PM PDT 24
Peak memory 201100 kb
Host smart-b7f56ed5-e0f4-482a-bc0d-abedee400995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577078500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.577078500
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.18113164
Short name T94
Test name
Test status
Simulation time 222656888434 ps
CPU time 469.24 seconds
Started Jul 25 06:43:45 PM PDT 24
Finished Jul 25 06:51:35 PM PDT 24
Peak memory 201296 kb
Host smart-8df4423d-b1ed-497e-95dd-4296b2883d0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18113164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.18113164
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1130929760
Short name T431
Test name
Test status
Simulation time 394802544 ps
CPU time 1.49 seconds
Started Jul 25 06:43:50 PM PDT 24
Finished Jul 25 06:43:51 PM PDT 24
Peak memory 201028 kb
Host smart-03b770f2-d115-491c-ac57-c51bc93155a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130929760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1130929760
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.441327980
Short name T86
Test name
Test status
Simulation time 371119505630 ps
CPU time 407.23 seconds
Started Jul 25 06:43:43 PM PDT 24
Finished Jul 25 06:50:31 PM PDT 24
Peak memory 201216 kb
Host smart-4e92c1c0-88bf-49d6-9547-2824b94b1166
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441327980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.441327980
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2277876503
Short name T329
Test name
Test status
Simulation time 496800267979 ps
CPU time 1148.53 seconds
Started Jul 25 06:43:43 PM PDT 24
Finished Jul 25 07:02:52 PM PDT 24
Peak memory 201240 kb
Host smart-513f9b77-99d3-4657-9788-5c580735037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277876503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2277876503
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3445018787
Short name T227
Test name
Test status
Simulation time 334112670022 ps
CPU time 210.79 seconds
Started Jul 25 06:43:43 PM PDT 24
Finished Jul 25 06:47:14 PM PDT 24
Peak memory 201304 kb
Host smart-3a1bb65d-fc23-4a3c-8e3a-b28109786ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445018787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3445018787
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1756351647
Short name T637
Test name
Test status
Simulation time 499227056336 ps
CPU time 211.5 seconds
Started Jul 25 06:43:43 PM PDT 24
Finished Jul 25 06:47:15 PM PDT 24
Peak memory 201236 kb
Host smart-3cff821b-d55f-4251-a709-50bf95ecb2eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756351647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1756351647
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1512749236
Short name T459
Test name
Test status
Simulation time 163685195417 ps
CPU time 202.9 seconds
Started Jul 25 06:43:45 PM PDT 24
Finished Jul 25 06:47:08 PM PDT 24
Peak memory 201220 kb
Host smart-8af0d30b-be00-4562-b01b-98e9d8e6b578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512749236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1512749236
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2974234155
Short name T682
Test name
Test status
Simulation time 325309856051 ps
CPU time 685.44 seconds
Started Jul 25 06:43:43 PM PDT 24
Finished Jul 25 06:55:08 PM PDT 24
Peak memory 201232 kb
Host smart-f0c52756-4fd9-42a5-bd6e-2f1a0ddbaa29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974234155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2974234155
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3760389910
Short name T100
Test name
Test status
Simulation time 632156439370 ps
CPU time 360.65 seconds
Started Jul 25 06:43:46 PM PDT 24
Finished Jul 25 06:49:46 PM PDT 24
Peak memory 201228 kb
Host smart-ba11816d-ddb4-43d7-b904-20b227be4496
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760389910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3760389910
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2028685867
Short name T584
Test name
Test status
Simulation time 385798280559 ps
CPU time 111.87 seconds
Started Jul 25 06:43:45 PM PDT 24
Finished Jul 25 06:45:37 PM PDT 24
Peak memory 201228 kb
Host smart-227c2fac-ce90-4dde-84bf-8d188c14d885
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028685867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2028685867
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3017309239
Short name T730
Test name
Test status
Simulation time 91821491445 ps
CPU time 505.64 seconds
Started Jul 25 06:43:49 PM PDT 24
Finished Jul 25 06:52:15 PM PDT 24
Peak memory 201668 kb
Host smart-76dc895b-f28b-4382-b114-8ba658839abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017309239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3017309239
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3253199002
Short name T420
Test name
Test status
Simulation time 38388732637 ps
CPU time 16.86 seconds
Started Jul 25 06:43:50 PM PDT 24
Finished Jul 25 06:44:07 PM PDT 24
Peak memory 201088 kb
Host smart-7a66d07f-f501-4f34-9754-cc73bad1503b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253199002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3253199002
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1087080650
Short name T353
Test name
Test status
Simulation time 4576099510 ps
CPU time 2.39 seconds
Started Jul 25 06:43:43 PM PDT 24
Finished Jul 25 06:43:46 PM PDT 24
Peak memory 201028 kb
Host smart-46af8dc3-a98e-4c50-a8f9-36bc88d8954b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087080650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1087080650
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2296806927
Short name T174
Test name
Test status
Simulation time 6058641148 ps
CPU time 15.31 seconds
Started Jul 25 06:43:46 PM PDT 24
Finished Jul 25 06:44:01 PM PDT 24
Peak memory 201108 kb
Host smart-d97abefc-6e59-4591-a6e7-41dd863dfa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296806927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2296806927
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3058155213
Short name T560
Test name
Test status
Simulation time 491823560 ps
CPU time 0.87 seconds
Started Jul 25 06:40:54 PM PDT 24
Finished Jul 25 06:40:55 PM PDT 24
Peak memory 201036 kb
Host smart-e769d9e6-519a-4c1d-a71a-3cefa16a899b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058155213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3058155213
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3976811503
Short name T334
Test name
Test status
Simulation time 380370906634 ps
CPU time 307.04 seconds
Started Jul 25 06:40:49 PM PDT 24
Finished Jul 25 06:45:57 PM PDT 24
Peak memory 201196 kb
Host smart-d038d1fd-52ac-4720-944c-c8788f242ef1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976811503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3976811503
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2056740942
Short name T314
Test name
Test status
Simulation time 334014717696 ps
CPU time 96.76 seconds
Started Jul 25 06:40:51 PM PDT 24
Finished Jul 25 06:42:28 PM PDT 24
Peak memory 201224 kb
Host smart-36a8f631-15a9-44d8-aeb9-6032395202ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056740942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2056740942
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1295567332
Short name T140
Test name
Test status
Simulation time 335331130223 ps
CPU time 126.04 seconds
Started Jul 25 06:40:50 PM PDT 24
Finished Jul 25 06:42:56 PM PDT 24
Peak memory 201300 kb
Host smart-ba41a896-e619-4bdb-ba72-b91f02fe104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295567332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1295567332
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2740921348
Short name T269
Test name
Test status
Simulation time 491922214873 ps
CPU time 1067.68 seconds
Started Jul 25 06:40:50 PM PDT 24
Finished Jul 25 06:58:38 PM PDT 24
Peak memory 201192 kb
Host smart-8afaa3e5-755e-437b-ad28-9bc0b1604d03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740921348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2740921348
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3299004663
Short name T138
Test name
Test status
Simulation time 327473173463 ps
CPU time 62.04 seconds
Started Jul 25 06:40:48 PM PDT 24
Finished Jul 25 06:41:50 PM PDT 24
Peak memory 201220 kb
Host smart-01685e73-1498-47c0-8271-e0ef6602ef86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299004663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3299004663
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1940189837
Short name T543
Test name
Test status
Simulation time 612626098597 ps
CPU time 1368.03 seconds
Started Jul 25 06:40:49 PM PDT 24
Finished Jul 25 07:03:37 PM PDT 24
Peak memory 201216 kb
Host smart-7faf0b4e-aa59-4446-b5d4-f05b41261232
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940189837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1940189837
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3614649082
Short name T756
Test name
Test status
Simulation time 77228667390 ps
CPU time 305.71 seconds
Started Jul 25 06:40:56 PM PDT 24
Finished Jul 25 06:46:01 PM PDT 24
Peak memory 201696 kb
Host smart-17f2815e-ab7b-4e2a-b83c-3a1f8d511b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614649082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3614649082
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.527853933
Short name T380
Test name
Test status
Simulation time 44034999297 ps
CPU time 102.19 seconds
Started Jul 25 06:40:58 PM PDT 24
Finished Jul 25 06:42:40 PM PDT 24
Peak memory 201068 kb
Host smart-e23ad92b-3f2f-4e0f-a3be-3e1ffc6a3e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527853933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.527853933
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.4116088345
Short name T435
Test name
Test status
Simulation time 4937562969 ps
CPU time 3.85 seconds
Started Jul 25 06:40:53 PM PDT 24
Finished Jul 25 06:40:57 PM PDT 24
Peak memory 201064 kb
Host smart-7ab61007-7f31-49c5-a9c9-e6027c5370a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116088345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.4116088345
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.4141901833
Short name T62
Test name
Test status
Simulation time 7386309501 ps
CPU time 9.25 seconds
Started Jul 25 06:40:54 PM PDT 24
Finished Jul 25 06:41:03 PM PDT 24
Peak memory 218076 kb
Host smart-6ff23e2f-d249-48b0-8d14-1feae3c533ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141901833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.4141901833
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2721611462
Short name T381
Test name
Test status
Simulation time 5884117110 ps
CPU time 14.65 seconds
Started Jul 25 06:40:50 PM PDT 24
Finished Jul 25 06:41:05 PM PDT 24
Peak memory 201072 kb
Host smart-ae6ec6c3-5abb-45c7-932c-7d16f6c3f1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721611462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2721611462
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2363795594
Short name T492
Test name
Test status
Simulation time 667233508049 ps
CPU time 1450.38 seconds
Started Jul 25 06:40:53 PM PDT 24
Finished Jul 25 07:05:03 PM PDT 24
Peak memory 201280 kb
Host smart-2ca87ead-7bc7-4b60-94d9-6d4f70ec0d50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363795594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2363795594
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3705687353
Short name T311
Test name
Test status
Simulation time 63568563370 ps
CPU time 119.06 seconds
Started Jul 25 06:40:56 PM PDT 24
Finished Jul 25 06:42:55 PM PDT 24
Peak memory 218116 kb
Host smart-4e044185-8dc8-414d-8aae-d2049f871176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705687353 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3705687353
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.498918425
Short name T440
Test name
Test status
Simulation time 410721034 ps
CPU time 0.8 seconds
Started Jul 25 06:43:59 PM PDT 24
Finished Jul 25 06:44:00 PM PDT 24
Peak memory 201044 kb
Host smart-b7003124-e165-4f31-ba51-04117ee31a89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498918425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.498918425
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3766264248
Short name T326
Test name
Test status
Simulation time 352317727639 ps
CPU time 376.92 seconds
Started Jul 25 06:43:55 PM PDT 24
Finished Jul 25 06:50:12 PM PDT 24
Peak memory 201300 kb
Host smart-eedf9a1e-f6e8-455f-b7f4-6bb168c85b27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766264248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3766264248
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3555515643
Short name T242
Test name
Test status
Simulation time 335372613883 ps
CPU time 187.72 seconds
Started Jul 25 06:43:50 PM PDT 24
Finished Jul 25 06:46:58 PM PDT 24
Peak memory 201304 kb
Host smart-1ad9d92a-b571-4fff-a8de-ba45dab3052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555515643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3555515643
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.26683282
Short name T83
Test name
Test status
Simulation time 486717812231 ps
CPU time 1075.26 seconds
Started Jul 25 06:43:50 PM PDT 24
Finished Jul 25 07:01:45 PM PDT 24
Peak memory 201236 kb
Host smart-50fdaf54-6a00-4e95-92ef-44105a617e7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=26683282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt
_fixed.26683282
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.85825132
Short name T458
Test name
Test status
Simulation time 168767522049 ps
CPU time 95.92 seconds
Started Jul 25 06:43:51 PM PDT 24
Finished Jul 25 06:45:27 PM PDT 24
Peak memory 201300 kb
Host smart-7dc4db97-2f14-4334-b456-e9d986c72a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85825132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.85825132
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3993827348
Short name T751
Test name
Test status
Simulation time 163773169800 ps
CPU time 195.6 seconds
Started Jul 25 06:43:52 PM PDT 24
Finished Jul 25 06:47:08 PM PDT 24
Peak memory 201232 kb
Host smart-a940e15a-9b30-4446-bd78-c90c7fa355c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993827348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3993827348
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3991833758
Short name T675
Test name
Test status
Simulation time 190028842065 ps
CPU time 430.96 seconds
Started Jul 25 06:43:56 PM PDT 24
Finished Jul 25 06:51:07 PM PDT 24
Peak memory 201220 kb
Host smart-65afd13b-142b-4167-b3e6-49994842337a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991833758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3991833758
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1093926322
Short name T716
Test name
Test status
Simulation time 609975648300 ps
CPU time 665.13 seconds
Started Jul 25 06:43:56 PM PDT 24
Finished Jul 25 06:55:02 PM PDT 24
Peak memory 201176 kb
Host smart-96880c1c-e3d0-4f1f-952b-b2367aae63b6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093926322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1093926322
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4154438939
Short name T377
Test name
Test status
Simulation time 91190741056 ps
CPU time 403.45 seconds
Started Jul 25 06:43:56 PM PDT 24
Finished Jul 25 06:50:40 PM PDT 24
Peak memory 201736 kb
Host smart-cafeac1a-62f1-4d91-ad58-8b30c13a6000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154438939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4154438939
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1707092982
Short name T447
Test name
Test status
Simulation time 31080037343 ps
CPU time 21.55 seconds
Started Jul 25 06:43:58 PM PDT 24
Finished Jul 25 06:44:20 PM PDT 24
Peak memory 201104 kb
Host smart-8753cbae-fe17-48b9-896e-59604600b56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707092982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1707092982
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.155302182
Short name T538
Test name
Test status
Simulation time 5319030666 ps
CPU time 7.5 seconds
Started Jul 25 06:44:00 PM PDT 24
Finished Jul 25 06:44:08 PM PDT 24
Peak memory 201060 kb
Host smart-5679c39d-f2df-4d8a-be13-8ec31443032d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155302182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.155302182
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1480732050
Short name T626
Test name
Test status
Simulation time 6007803027 ps
CPU time 13.8 seconds
Started Jul 25 06:43:50 PM PDT 24
Finished Jul 25 06:44:04 PM PDT 24
Peak memory 201092 kb
Host smart-ca760930-7bfd-48dd-847d-c4027f5ba145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480732050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1480732050
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2651811422
Short name T199
Test name
Test status
Simulation time 311142620867 ps
CPU time 1057.44 seconds
Started Jul 25 06:43:57 PM PDT 24
Finished Jul 25 07:01:35 PM PDT 24
Peak memory 218036 kb
Host smart-536cf397-c4f9-456f-93f5-b646bb5284dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651811422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2651811422
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1377095191
Short name T719
Test name
Test status
Simulation time 372900492 ps
CPU time 0.8 seconds
Started Jul 25 06:44:23 PM PDT 24
Finished Jul 25 06:44:24 PM PDT 24
Peak memory 201016 kb
Host smart-7f1afcda-7f1f-4f69-a398-4ec5097a7a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377095191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1377095191
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2533800805
Short name T518
Test name
Test status
Simulation time 171705740716 ps
CPU time 417.96 seconds
Started Jul 25 06:44:06 PM PDT 24
Finished Jul 25 06:51:04 PM PDT 24
Peak memory 201224 kb
Host smart-4b83c05e-08bc-4466-a28c-370c77c68da1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533800805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2533800805
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2037510663
Short name T544
Test name
Test status
Simulation time 164709380026 ps
CPU time 104.43 seconds
Started Jul 25 06:44:04 PM PDT 24
Finished Jul 25 06:45:49 PM PDT 24
Peak memory 201236 kb
Host smart-f4727e2d-b428-4842-8137-bcf78324c10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037510663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2037510663
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1234169786
Short name T624
Test name
Test status
Simulation time 499901079750 ps
CPU time 294.38 seconds
Started Jul 25 06:43:58 PM PDT 24
Finished Jul 25 06:48:52 PM PDT 24
Peak memory 201252 kb
Host smart-088ea290-521d-478b-83bc-533aa19e3cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234169786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1234169786
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.4046951084
Short name T772
Test name
Test status
Simulation time 488239945079 ps
CPU time 1099.26 seconds
Started Jul 25 06:44:04 PM PDT 24
Finished Jul 25 07:02:24 PM PDT 24
Peak memory 201224 kb
Host smart-f656b543-61f2-4def-906e-963353b62d08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046951084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.4046951084
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1590241442
Short name T731
Test name
Test status
Simulation time 168906959611 ps
CPU time 194.63 seconds
Started Jul 25 06:43:56 PM PDT 24
Finished Jul 25 06:47:11 PM PDT 24
Peak memory 201276 kb
Host smart-975d58d0-d514-4fbf-abca-480005574efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590241442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1590241442
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.4095246656
Short name T591
Test name
Test status
Simulation time 325921355420 ps
CPU time 347.37 seconds
Started Jul 25 06:43:56 PM PDT 24
Finished Jul 25 06:49:43 PM PDT 24
Peak memory 201236 kb
Host smart-45fdede8-077f-4bce-a4dd-e85c09dd34ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095246656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.4095246656
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1430683317
Short name T237
Test name
Test status
Simulation time 349443627954 ps
CPU time 207.6 seconds
Started Jul 25 06:44:03 PM PDT 24
Finished Jul 25 06:47:30 PM PDT 24
Peak memory 201232 kb
Host smart-55eba854-eeb9-4731-86c0-fadfff74d99c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430683317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1430683317
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3692682230
Short name T382
Test name
Test status
Simulation time 604463492887 ps
CPU time 1341.54 seconds
Started Jul 25 06:44:03 PM PDT 24
Finished Jul 25 07:06:25 PM PDT 24
Peak memory 201280 kb
Host smart-9bef3e1b-fec7-4546-8c95-23b5cbc67dae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692682230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3692682230
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.4232713027
Short name T200
Test name
Test status
Simulation time 121710555634 ps
CPU time 628.73 seconds
Started Jul 25 06:44:05 PM PDT 24
Finished Jul 25 06:54:34 PM PDT 24
Peak memory 201616 kb
Host smart-32e6ab60-c240-4c87-8e35-303481996608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232713027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.4232713027
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1101480973
Short name T405
Test name
Test status
Simulation time 35819671572 ps
CPU time 22.35 seconds
Started Jul 25 06:44:06 PM PDT 24
Finished Jul 25 06:44:28 PM PDT 24
Peak memory 201080 kb
Host smart-af614270-836c-45e8-9495-dc4f348a133a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101480973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1101480973
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3969191998
Short name T192
Test name
Test status
Simulation time 3371679009 ps
CPU time 5.44 seconds
Started Jul 25 06:44:05 PM PDT 24
Finished Jul 25 06:44:10 PM PDT 24
Peak memory 201104 kb
Host smart-37781f6e-83d7-405c-8d57-9004209c432a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969191998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3969191998
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1506752658
Short name T129
Test name
Test status
Simulation time 5898916150 ps
CPU time 3.16 seconds
Started Jul 25 06:43:58 PM PDT 24
Finished Jul 25 06:44:01 PM PDT 24
Peak memory 201096 kb
Host smart-18ec45c8-fa05-4d80-a19c-e1d41da88e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506752658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1506752658
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2995319354
Short name T777
Test name
Test status
Simulation time 167132504186 ps
CPU time 73.85 seconds
Started Jul 25 06:44:05 PM PDT 24
Finished Jul 25 06:45:18 PM PDT 24
Peak memory 201252 kb
Host smart-d48bfa72-bc79-4af2-af0d-7c080abad529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995319354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2995319354
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1194337474
Short name T793
Test name
Test status
Simulation time 216512765893 ps
CPU time 200.64 seconds
Started Jul 25 06:44:04 PM PDT 24
Finished Jul 25 06:47:25 PM PDT 24
Peak memory 210012 kb
Host smart-ee2d2828-2751-4ab6-8c26-bf7af804bcbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194337474 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1194337474
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2103036353
Short name T26
Test name
Test status
Simulation time 390279401 ps
CPU time 0.74 seconds
Started Jul 25 06:44:15 PM PDT 24
Finished Jul 25 06:44:16 PM PDT 24
Peak memory 201036 kb
Host smart-2590be34-4c61-447d-9ff5-5ef771e1055b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103036353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2103036353
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1944038686
Short name T575
Test name
Test status
Simulation time 185593208763 ps
CPU time 374.65 seconds
Started Jul 25 06:44:13 PM PDT 24
Finished Jul 25 06:50:27 PM PDT 24
Peak memory 201204 kb
Host smart-c43b7ae7-910a-4c52-9881-f9db1dbc52c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944038686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1944038686
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2904669390
Short name T43
Test name
Test status
Simulation time 332141098339 ps
CPU time 336.3 seconds
Started Jul 25 06:44:14 PM PDT 24
Finished Jul 25 06:49:51 PM PDT 24
Peak memory 201248 kb
Host smart-afcc3219-ce25-4727-a040-66d47913ba0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904669390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2904669390
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3257199721
Short name T494
Test name
Test status
Simulation time 486169107160 ps
CPU time 120.34 seconds
Started Jul 25 06:44:11 PM PDT 24
Finished Jul 25 06:46:11 PM PDT 24
Peak memory 201232 kb
Host smart-0f0203e6-ab13-4f0b-8a65-82848e090aa8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257199721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3257199721
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1702118434
Short name T615
Test name
Test status
Simulation time 160594348628 ps
CPU time 56.53 seconds
Started Jul 25 06:44:13 PM PDT 24
Finished Jul 25 06:45:09 PM PDT 24
Peak memory 201220 kb
Host smart-55b51697-9307-4997-8542-5d2cf7c74403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702118434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1702118434
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2482788489
Short name T657
Test name
Test status
Simulation time 480614727793 ps
CPU time 277.45 seconds
Started Jul 25 06:44:11 PM PDT 24
Finished Jul 25 06:48:49 PM PDT 24
Peak memory 201292 kb
Host smart-f7bafc37-bddf-4409-ba94-55e0ce401175
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482788489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2482788489
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1140677530
Short name T178
Test name
Test status
Simulation time 634942165779 ps
CPU time 454.79 seconds
Started Jul 25 06:44:21 PM PDT 24
Finished Jul 25 06:51:56 PM PDT 24
Peak memory 201232 kb
Host smart-7078d471-4701-4e2f-9a04-ca59150863d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140677530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1140677530
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.938039113
Short name T643
Test name
Test status
Simulation time 398090226105 ps
CPU time 242.85 seconds
Started Jul 25 06:44:11 PM PDT 24
Finished Jul 25 06:48:14 PM PDT 24
Peak memory 201228 kb
Host smart-c1220664-0e4d-4450-935b-da6cb951e320
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938039113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.938039113
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.76065958
Short name T446
Test name
Test status
Simulation time 79809093828 ps
CPU time 406.16 seconds
Started Jul 25 06:44:14 PM PDT 24
Finished Jul 25 06:51:01 PM PDT 24
Peak memory 201668 kb
Host smart-12056044-b07f-4ef7-a623-2dbdf1d93d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76065958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.76065958
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2230192071
Short name T723
Test name
Test status
Simulation time 30097132390 ps
CPU time 73.98 seconds
Started Jul 25 06:44:11 PM PDT 24
Finished Jul 25 06:45:25 PM PDT 24
Peak memory 201120 kb
Host smart-46bcdd4a-1135-4a74-bf0e-3b3c9fa3dc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230192071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2230192071
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2740352621
Short name T376
Test name
Test status
Simulation time 4232536432 ps
CPU time 10.69 seconds
Started Jul 25 06:44:11 PM PDT 24
Finished Jul 25 06:44:22 PM PDT 24
Peak memory 201032 kb
Host smart-2cb52f7f-56df-4e86-afc9-3d22c9900468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740352621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2740352621
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1235531513
Short name T632
Test name
Test status
Simulation time 5994101733 ps
CPU time 15.79 seconds
Started Jul 25 06:44:12 PM PDT 24
Finished Jul 25 06:44:28 PM PDT 24
Peak memory 201080 kb
Host smart-97612252-241d-4d75-8933-01e61e071f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235531513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1235531513
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.411621308
Short name T292
Test name
Test status
Simulation time 175991325967 ps
CPU time 208.35 seconds
Started Jul 25 06:44:13 PM PDT 24
Finished Jul 25 06:47:42 PM PDT 24
Peak memory 201300 kb
Host smart-83ca94a4-931a-4886-aecc-ed08d711bccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411621308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
411621308
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3833683815
Short name T347
Test name
Test status
Simulation time 519106493 ps
CPU time 0.88 seconds
Started Jul 25 06:44:26 PM PDT 24
Finished Jul 25 06:44:27 PM PDT 24
Peak memory 201004 kb
Host smart-bda6b486-fc63-4fe9-9bfc-0db51b089e53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833683815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3833683815
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1998290166
Short name T579
Test name
Test status
Simulation time 201665690418 ps
CPU time 487.78 seconds
Started Jul 25 06:44:19 PM PDT 24
Finished Jul 25 06:52:27 PM PDT 24
Peak memory 201232 kb
Host smart-6945ca8b-e4a0-40e2-89eb-d89f569913fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998290166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1998290166
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1199983940
Short name T270
Test name
Test status
Simulation time 158561200397 ps
CPU time 73.99 seconds
Started Jul 25 06:44:25 PM PDT 24
Finished Jul 25 06:45:39 PM PDT 24
Peak memory 201180 kb
Host smart-38fc5252-ccff-4b22-a8e5-797071ae21d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199983940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1199983940
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1555598763
Short name T564
Test name
Test status
Simulation time 490318213563 ps
CPU time 1079.04 seconds
Started Jul 25 06:44:18 PM PDT 24
Finished Jul 25 07:02:18 PM PDT 24
Peak memory 201300 kb
Host smart-257ac334-9d2d-4ca6-a31f-b0450382c2ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555598763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1555598763
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1579351938
Short name T85
Test name
Test status
Simulation time 320000233868 ps
CPU time 201.88 seconds
Started Jul 25 06:44:18 PM PDT 24
Finished Jul 25 06:47:40 PM PDT 24
Peak memory 201220 kb
Host smart-7530d02a-5dd5-47e8-915e-11fe5faa46c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579351938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1579351938
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.4205524487
Short name T184
Test name
Test status
Simulation time 320747319583 ps
CPU time 189.68 seconds
Started Jul 25 06:44:25 PM PDT 24
Finished Jul 25 06:47:34 PM PDT 24
Peak memory 201124 kb
Host smart-c126410e-07cd-41fe-9579-4c3d83f2f78b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205524487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.4205524487
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2840994973
Short name T313
Test name
Test status
Simulation time 375179436395 ps
CPU time 215.59 seconds
Started Jul 25 06:44:25 PM PDT 24
Finished Jul 25 06:48:01 PM PDT 24
Peak memory 201120 kb
Host smart-e8a82f0b-138b-4d9f-8c4f-82f387e34d96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840994973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2840994973
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1910526932
Short name T766
Test name
Test status
Simulation time 398955974614 ps
CPU time 526.9 seconds
Started Jul 25 06:44:19 PM PDT 24
Finished Jul 25 06:53:06 PM PDT 24
Peak memory 201232 kb
Host smart-3a41eca3-b2e6-47ad-924b-464280eab6c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910526932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1910526932
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3634066059
Short name T44
Test name
Test status
Simulation time 93125328112 ps
CPU time 452.97 seconds
Started Jul 25 06:44:27 PM PDT 24
Finished Jul 25 06:52:00 PM PDT 24
Peak memory 201704 kb
Host smart-440c5a6c-dcac-4c1d-9c89-c8e57ad9af4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634066059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3634066059
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1837526339
Short name T754
Test name
Test status
Simulation time 26543819590 ps
CPU time 32.79 seconds
Started Jul 25 06:44:25 PM PDT 24
Finished Jul 25 06:44:58 PM PDT 24
Peak memory 200964 kb
Host smart-79a7c847-f241-4e56-90e3-fd0d61866c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837526339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1837526339
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.895971568
Short name T580
Test name
Test status
Simulation time 4610143740 ps
CPU time 1.63 seconds
Started Jul 25 06:44:20 PM PDT 24
Finished Jul 25 06:44:21 PM PDT 24
Peak memory 201024 kb
Host smart-70afeeb3-a57c-498b-b036-014620fd9e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895971568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.895971568
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1895743878
Short name T550
Test name
Test status
Simulation time 5747025469 ps
CPU time 8.5 seconds
Started Jul 25 06:45:42 PM PDT 24
Finished Jul 25 06:45:50 PM PDT 24
Peak memory 201112 kb
Host smart-3525495c-8a1b-48c7-a9dd-24d7786b7858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895743878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1895743878
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1202214273
Short name T694
Test name
Test status
Simulation time 329944381153 ps
CPU time 196.91 seconds
Started Jul 25 06:44:27 PM PDT 24
Finished Jul 25 06:47:44 PM PDT 24
Peak memory 201196 kb
Host smart-14a432fd-752b-4dd5-9bea-a181135786b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202214273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1202214273
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2038635700
Short name T526
Test name
Test status
Simulation time 539967224 ps
CPU time 0.95 seconds
Started Jul 25 06:44:31 PM PDT 24
Finished Jul 25 06:44:32 PM PDT 24
Peak memory 201008 kb
Host smart-fe2fad91-30f7-4ad6-bc61-191893869c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038635700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2038635700
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3041324954
Short name T539
Test name
Test status
Simulation time 328778886879 ps
CPU time 481.2 seconds
Started Jul 25 06:44:25 PM PDT 24
Finished Jul 25 06:52:26 PM PDT 24
Peak memory 201236 kb
Host smart-ef5a444b-19d6-4338-9bbe-46c8004223c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041324954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3041324954
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2919485694
Short name T789
Test name
Test status
Simulation time 171139203525 ps
CPU time 72.35 seconds
Started Jul 25 06:44:27 PM PDT 24
Finished Jul 25 06:45:40 PM PDT 24
Peak memory 201196 kb
Host smart-7a80b462-448c-4baa-872e-d114c0d4035e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919485694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2919485694
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.380408374
Short name T29
Test name
Test status
Simulation time 161139129263 ps
CPU time 92.65 seconds
Started Jul 25 06:44:28 PM PDT 24
Finished Jul 25 06:46:01 PM PDT 24
Peak memory 201300 kb
Host smart-7f318fc9-834b-4798-887a-d89793cfad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380408374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.380408374
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.13241280
Short name T535
Test name
Test status
Simulation time 171830834274 ps
CPU time 375.53 seconds
Started Jul 25 06:44:27 PM PDT 24
Finished Jul 25 06:50:42 PM PDT 24
Peak memory 201200 kb
Host smart-edb93dbe-3a48-4a76-a096-0c24cdd67193
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=13241280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed
.13241280
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3815699060
Short name T608
Test name
Test status
Simulation time 170493809807 ps
CPU time 108.34 seconds
Started Jul 25 06:44:26 PM PDT 24
Finished Jul 25 06:46:14 PM PDT 24
Peak memory 201236 kb
Host smart-3a5f35e5-4252-44e5-b178-ad79e0c86c88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815699060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3815699060
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3655027458
Short name T392
Test name
Test status
Simulation time 413772440512 ps
CPU time 245.76 seconds
Started Jul 25 06:44:32 PM PDT 24
Finished Jul 25 06:48:38 PM PDT 24
Peak memory 201308 kb
Host smart-0832c9fb-ed72-4bea-b6b3-1841a12f335b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655027458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3655027458
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1076811977
Short name T344
Test name
Test status
Simulation time 138896864419 ps
CPU time 459.8 seconds
Started Jul 25 06:44:33 PM PDT 24
Finished Jul 25 06:52:13 PM PDT 24
Peak memory 201704 kb
Host smart-f1633be0-9e61-48fe-ad78-6d669dc74bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076811977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1076811977
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2614889565
Short name T700
Test name
Test status
Simulation time 41354965012 ps
CPU time 16.1 seconds
Started Jul 25 06:44:32 PM PDT 24
Finished Jul 25 06:44:48 PM PDT 24
Peak memory 201104 kb
Host smart-1c0d2432-5d44-48b4-a28b-15ecf4bee898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614889565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2614889565
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3895733032
Short name T620
Test name
Test status
Simulation time 2721469121 ps
CPU time 3.73 seconds
Started Jul 25 06:44:34 PM PDT 24
Finished Jul 25 06:44:38 PM PDT 24
Peak memory 201132 kb
Host smart-99f3f1d9-e3c8-4947-91ed-4a5575e6025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895733032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3895733032
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.638944273
Short name T622
Test name
Test status
Simulation time 6085581472 ps
CPU time 7.66 seconds
Started Jul 25 06:44:30 PM PDT 24
Finished Jul 25 06:44:38 PM PDT 24
Peak memory 201092 kb
Host smart-e306e4d7-1ae8-4b0b-81d6-d7832141f660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638944273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.638944273
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3044696630
Short name T448
Test name
Test status
Simulation time 482684905253 ps
CPU time 464.28 seconds
Started Jul 25 06:44:34 PM PDT 24
Finished Jul 25 06:52:18 PM PDT 24
Peak memory 209916 kb
Host smart-4dd9785a-64df-4672-ada6-4adbbdd1e0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044696630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3044696630
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.4011899258
Short name T297
Test name
Test status
Simulation time 230215292637 ps
CPU time 186.03 seconds
Started Jul 25 06:44:34 PM PDT 24
Finished Jul 25 06:47:40 PM PDT 24
Peak memory 217792 kb
Host smart-2681c198-57a9-4ac0-b966-1a432177708d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011899258 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.4011899258
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3347989286
Short name T662
Test name
Test status
Simulation time 423712757 ps
CPU time 0.86 seconds
Started Jul 25 06:44:39 PM PDT 24
Finished Jul 25 06:44:40 PM PDT 24
Peak memory 200956 kb
Host smart-d676bdba-7ab1-40ac-8a0e-835363bb3e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347989286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3347989286
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2564243575
Short name T262
Test name
Test status
Simulation time 197032767605 ps
CPU time 224.54 seconds
Started Jul 25 06:44:38 PM PDT 24
Finished Jul 25 06:48:23 PM PDT 24
Peak memory 201244 kb
Host smart-99be5c02-39ca-44c3-8249-57419147cc5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564243575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2564243575
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.867940708
Short name T240
Test name
Test status
Simulation time 466849553263 ps
CPU time 295.36 seconds
Started Jul 25 06:44:40 PM PDT 24
Finished Jul 25 06:49:35 PM PDT 24
Peak memory 201216 kb
Host smart-09729ba8-1755-4cf0-9da8-043a4e5bfbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867940708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.867940708
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2929333961
Short name T218
Test name
Test status
Simulation time 484254182735 ps
CPU time 297.78 seconds
Started Jul 25 06:44:33 PM PDT 24
Finished Jul 25 06:49:31 PM PDT 24
Peak memory 201240 kb
Host smart-429798d6-4d52-410f-913f-1aec4d029597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929333961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2929333961
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3835650604
Short name T596
Test name
Test status
Simulation time 173395849669 ps
CPU time 412.43 seconds
Started Jul 25 06:44:32 PM PDT 24
Finished Jul 25 06:51:25 PM PDT 24
Peak memory 201216 kb
Host smart-b4a44a87-14d4-4f31-b1e7-8c7c1c2203be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835650604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3835650604
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1797419384
Short name T415
Test name
Test status
Simulation time 168929357771 ps
CPU time 39.81 seconds
Started Jul 25 06:44:33 PM PDT 24
Finished Jul 25 06:45:13 PM PDT 24
Peak memory 201184 kb
Host smart-22a7587a-9ab4-4fbb-b921-fb05e7af2303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797419384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1797419384
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3892956211
Short name T410
Test name
Test status
Simulation time 499763902852 ps
CPU time 621.45 seconds
Started Jul 25 06:44:31 PM PDT 24
Finished Jul 25 06:54:53 PM PDT 24
Peak memory 201232 kb
Host smart-e41a93d5-410b-474e-86ed-45bb64cb7114
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892956211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3892956211
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2724967569
Short name T331
Test name
Test status
Simulation time 457214928420 ps
CPU time 1097.91 seconds
Started Jul 25 06:44:30 PM PDT 24
Finished Jul 25 07:02:48 PM PDT 24
Peak memory 201220 kb
Host smart-f33aa552-0f45-4d68-87f4-48dd709614e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724967569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2724967569
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3503017663
Short name T551
Test name
Test status
Simulation time 395307400034 ps
CPU time 105.92 seconds
Started Jul 25 06:44:31 PM PDT 24
Finished Jul 25 06:46:17 PM PDT 24
Peak memory 201236 kb
Host smart-a5526e35-ffa9-4f0a-b176-455b51856962
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503017663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3503017663
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3176134226
Short name T703
Test name
Test status
Simulation time 87983524424 ps
CPU time 379.78 seconds
Started Jul 25 06:44:38 PM PDT 24
Finished Jul 25 06:50:58 PM PDT 24
Peak memory 201708 kb
Host smart-fd390539-4cf6-4c95-bd13-f20e0621bd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176134226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3176134226
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.659228681
Short name T605
Test name
Test status
Simulation time 22921684256 ps
CPU time 28.1 seconds
Started Jul 25 06:44:38 PM PDT 24
Finished Jul 25 06:45:07 PM PDT 24
Peak memory 201080 kb
Host smart-1fa5a2cc-29a9-4dae-b296-af6d0faa4788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659228681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.659228681
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1021260632
Short name T81
Test name
Test status
Simulation time 2923603409 ps
CPU time 7.41 seconds
Started Jul 25 06:44:42 PM PDT 24
Finished Jul 25 06:44:50 PM PDT 24
Peak memory 201080 kb
Host smart-27ad1258-b540-484f-9327-622866d798b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021260632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1021260632
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.60537314
Short name T515
Test name
Test status
Simulation time 5985313708 ps
CPU time 2.06 seconds
Started Jul 25 06:44:32 PM PDT 24
Finished Jul 25 06:44:35 PM PDT 24
Peak memory 201124 kb
Host smart-4cf5e2ef-5715-4c9b-b945-d9797669c382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60537314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.60537314
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3902556777
Short name T216
Test name
Test status
Simulation time 326550391568 ps
CPU time 365.67 seconds
Started Jul 25 06:44:39 PM PDT 24
Finished Jul 25 06:50:45 PM PDT 24
Peak memory 201288 kb
Host smart-a372dcf5-2870-480d-915a-22692b19bc75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902556777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3902556777
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.4179817611
Short name T699
Test name
Test status
Simulation time 120180087052 ps
CPU time 255.08 seconds
Started Jul 25 06:44:39 PM PDT 24
Finished Jul 25 06:48:54 PM PDT 24
Peak memory 210052 kb
Host smart-1db1d84a-652e-472b-8e56-3a446d5b2c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179817611 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.4179817611
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.204152163
Short name T362
Test name
Test status
Simulation time 499238737 ps
CPU time 0.87 seconds
Started Jul 25 06:44:52 PM PDT 24
Finished Jul 25 06:44:53 PM PDT 24
Peak memory 201032 kb
Host smart-3e3ff24c-33a1-441e-b750-6b146714d7c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204152163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.204152163
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1533573794
Short name T684
Test name
Test status
Simulation time 516766215336 ps
CPU time 481.75 seconds
Started Jul 25 06:44:47 PM PDT 24
Finished Jul 25 06:52:49 PM PDT 24
Peak memory 201244 kb
Host smart-810b0376-9651-45c5-87ce-771bb58dac1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533573794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1533573794
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1906945860
Short name T549
Test name
Test status
Simulation time 199536537414 ps
CPU time 48.17 seconds
Started Jul 25 06:44:47 PM PDT 24
Finished Jul 25 06:45:35 PM PDT 24
Peak memory 201300 kb
Host smart-aec29556-457a-4c9c-b2c4-c85fad0e2ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906945860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1906945860
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.528389907
Short name T654
Test name
Test status
Simulation time 488717045179 ps
CPU time 1187.56 seconds
Started Jul 25 06:44:42 PM PDT 24
Finished Jul 25 07:04:29 PM PDT 24
Peak memory 201224 kb
Host smart-ffcc07cc-e0e1-4991-b8ec-29d64d2a4f33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=528389907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.528389907
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3584174507
Short name T743
Test name
Test status
Simulation time 491993203729 ps
CPU time 546.19 seconds
Started Jul 25 06:44:38 PM PDT 24
Finished Jul 25 06:53:45 PM PDT 24
Peak memory 201244 kb
Host smart-4a37879a-798e-483e-b02a-f965cfd76e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584174507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3584174507
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2565639243
Short name T456
Test name
Test status
Simulation time 484020285515 ps
CPU time 255.62 seconds
Started Jul 25 06:44:40 PM PDT 24
Finished Jul 25 06:48:56 PM PDT 24
Peak memory 201288 kb
Host smart-a8b7a197-2707-4eeb-b363-6e0ed5296702
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565639243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2565639243
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.4206861222
Short name T737
Test name
Test status
Simulation time 174749290918 ps
CPU time 385.52 seconds
Started Jul 25 06:44:46 PM PDT 24
Finished Jul 25 06:51:11 PM PDT 24
Peak memory 201284 kb
Host smart-915cf874-99f7-4271-b356-52f409eba79c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206861222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.4206861222
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3733491578
Short name T578
Test name
Test status
Simulation time 206664194435 ps
CPU time 54.17 seconds
Started Jul 25 06:44:47 PM PDT 24
Finished Jul 25 06:45:41 PM PDT 24
Peak memory 201232 kb
Host smart-407115db-3b2b-4f9a-8cfc-59b30050d638
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733491578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3733491578
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3293082916
Short name T502
Test name
Test status
Simulation time 112496371375 ps
CPU time 574.86 seconds
Started Jul 25 06:44:45 PM PDT 24
Finished Jul 25 06:54:21 PM PDT 24
Peak memory 201744 kb
Host smart-ac3ebca8-b4aa-4af0-afe9-7c41d6168b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293082916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3293082916
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4196123580
Short name T705
Test name
Test status
Simulation time 39488174208 ps
CPU time 20.58 seconds
Started Jul 25 06:44:44 PM PDT 24
Finished Jul 25 06:45:05 PM PDT 24
Peak memory 201068 kb
Host smart-197fb912-d1f6-49f9-9746-590c5a0e6cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196123580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4196123580
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1475587117
Short name T102
Test name
Test status
Simulation time 2621754045 ps
CPU time 6.08 seconds
Started Jul 25 06:44:45 PM PDT 24
Finished Jul 25 06:44:52 PM PDT 24
Peak memory 201088 kb
Host smart-afc8dc00-b77d-4004-ba81-60f9d1343f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475587117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1475587117
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.227012946
Short name T378
Test name
Test status
Simulation time 6005743753 ps
CPU time 4.72 seconds
Started Jul 25 06:44:39 PM PDT 24
Finished Jul 25 06:44:44 PM PDT 24
Peak memory 201060 kb
Host smart-310dea49-f479-4624-8e6d-90864a28c30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227012946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.227012946
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1129153894
Short name T106
Test name
Test status
Simulation time 20500777028 ps
CPU time 94.51 seconds
Started Jul 25 06:44:46 PM PDT 24
Finished Jul 25 06:46:20 PM PDT 24
Peak memory 218140 kb
Host smart-8ffea4f4-63ea-40b4-9de7-2f825e79fba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129153894 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1129153894
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1440215466
Short name T400
Test name
Test status
Simulation time 417931482 ps
CPU time 1.49 seconds
Started Jul 25 06:45:06 PM PDT 24
Finished Jul 25 06:45:07 PM PDT 24
Peak memory 201008 kb
Host smart-585d5405-69ff-440a-9a0d-53545a9e01ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440215466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1440215466
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2707793684
Short name T598
Test name
Test status
Simulation time 334949843783 ps
CPU time 118.96 seconds
Started Jul 25 06:44:53 PM PDT 24
Finished Jul 25 06:46:52 PM PDT 24
Peak memory 201176 kb
Host smart-b9ace980-b678-4dba-b3de-7ac2b41feb8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707793684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2707793684
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1517808011
Short name T257
Test name
Test status
Simulation time 169647676771 ps
CPU time 404.45 seconds
Started Jul 25 06:44:53 PM PDT 24
Finished Jul 25 06:51:37 PM PDT 24
Peak memory 201296 kb
Host smart-6b7db248-fc51-41e5-9c0c-9eefc368f7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517808011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1517808011
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2497395515
Short name T642
Test name
Test status
Simulation time 323880468286 ps
CPU time 781.07 seconds
Started Jul 25 06:44:53 PM PDT 24
Finished Jul 25 06:57:55 PM PDT 24
Peak memory 201228 kb
Host smart-943f48ac-8e55-4462-b844-de0ed50fab01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497395515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2497395515
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3395194090
Short name T135
Test name
Test status
Simulation time 165472653242 ps
CPU time 30.15 seconds
Started Jul 25 06:44:52 PM PDT 24
Finished Jul 25 06:45:22 PM PDT 24
Peak memory 201236 kb
Host smart-49409e54-ab0e-47cf-b15b-c9e502e1ca55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395194090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3395194090
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3079902240
Short name T402
Test name
Test status
Simulation time 158959826601 ps
CPU time 373.58 seconds
Started Jul 25 06:44:52 PM PDT 24
Finished Jul 25 06:51:06 PM PDT 24
Peak memory 201240 kb
Host smart-1c916b92-fcae-4ba7-a09f-a6eafa115d7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079902240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3079902240
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1126579401
Short name T156
Test name
Test status
Simulation time 573378031996 ps
CPU time 1394.66 seconds
Started Jul 25 06:44:53 PM PDT 24
Finished Jul 25 07:08:08 PM PDT 24
Peak memory 201196 kb
Host smart-66f9423d-0dac-4359-b43f-552db17a0a86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126579401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1126579401
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.4016259689
Short name T384
Test name
Test status
Simulation time 390094102060 ps
CPU time 951.71 seconds
Started Jul 25 06:44:52 PM PDT 24
Finished Jul 25 07:00:44 PM PDT 24
Peak memory 201244 kb
Host smart-04735eb0-1570-4427-997e-d4c752c8b9c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016259689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.4016259689
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2797939962
Short name T204
Test name
Test status
Simulation time 132642774279 ps
CPU time 449.81 seconds
Started Jul 25 06:45:00 PM PDT 24
Finished Jul 25 06:52:30 PM PDT 24
Peak memory 201620 kb
Host smart-94470ea9-715f-4184-ae46-ab2ecd647808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797939962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2797939962
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3183209130
Short name T412
Test name
Test status
Simulation time 22335266599 ps
CPU time 49.19 seconds
Started Jul 25 06:45:02 PM PDT 24
Finished Jul 25 06:45:51 PM PDT 24
Peak memory 201088 kb
Host smart-033740da-a63e-4dd2-a4ef-a95a27911b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183209130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3183209130
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3606146259
Short name T375
Test name
Test status
Simulation time 5231185541 ps
CPU time 3.41 seconds
Started Jul 25 06:45:01 PM PDT 24
Finished Jul 25 06:45:05 PM PDT 24
Peak memory 201100 kb
Host smart-60af1506-faca-4e33-bfda-8205be192fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606146259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3606146259
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.904836178
Short name T651
Test name
Test status
Simulation time 6126182349 ps
CPU time 2.86 seconds
Started Jul 25 06:44:54 PM PDT 24
Finished Jul 25 06:44:57 PM PDT 24
Peak memory 201108 kb
Host smart-753eadb3-6f57-4390-93d5-07b9a4fe0fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904836178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.904836178
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.388370144
Short name T712
Test name
Test status
Simulation time 81503879680 ps
CPU time 139.05 seconds
Started Jul 25 06:45:00 PM PDT 24
Finished Jul 25 06:47:19 PM PDT 24
Peak memory 217756 kb
Host smart-c946b174-42aa-434b-8f0a-568091a0f362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388370144 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.388370144
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.645736080
Short name T31
Test name
Test status
Simulation time 296212936 ps
CPU time 1.31 seconds
Started Jul 25 06:45:15 PM PDT 24
Finished Jul 25 06:45:17 PM PDT 24
Peak memory 201052 kb
Host smart-60aa8ca9-29b4-47de-9f92-d57a1d7be9a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645736080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.645736080
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2932315273
Short name T163
Test name
Test status
Simulation time 538021544994 ps
CPU time 307.39 seconds
Started Jul 25 06:45:07 PM PDT 24
Finished Jul 25 06:50:14 PM PDT 24
Peak memory 201236 kb
Host smart-560060d8-2bb6-44cb-814d-9c75b371b6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932315273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2932315273
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1838517541
Short name T689
Test name
Test status
Simulation time 163717310100 ps
CPU time 93.95 seconds
Started Jul 25 06:45:07 PM PDT 24
Finished Jul 25 06:46:41 PM PDT 24
Peak memory 201252 kb
Host smart-494c5565-ac8d-4d85-94ab-a463c8951aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838517541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1838517541
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3629427367
Short name T780
Test name
Test status
Simulation time 493600315342 ps
CPU time 1193.18 seconds
Started Jul 25 06:45:06 PM PDT 24
Finished Jul 25 07:05:00 PM PDT 24
Peak memory 201200 kb
Host smart-0f03c75f-4cf1-45d7-81d0-c7117a67d7e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629427367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3629427367
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2415987089
Short name T677
Test name
Test status
Simulation time 480039302163 ps
CPU time 896.77 seconds
Started Jul 25 06:45:04 PM PDT 24
Finished Jul 25 07:00:01 PM PDT 24
Peak memory 201272 kb
Host smart-f9b5d03b-b83a-4440-a57a-058a12c3e78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415987089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2415987089
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3626720666
Short name T588
Test name
Test status
Simulation time 320063957072 ps
CPU time 679.02 seconds
Started Jul 25 06:45:05 PM PDT 24
Finished Jul 25 06:56:25 PM PDT 24
Peak memory 201220 kb
Host smart-c3a7f7cc-c254-419d-a2c8-5ce13b8572cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626720666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3626720666
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3328961910
Short name T142
Test name
Test status
Simulation time 455161451938 ps
CPU time 491.15 seconds
Started Jul 25 06:45:06 PM PDT 24
Finished Jul 25 06:53:17 PM PDT 24
Peak memory 201256 kb
Host smart-b01cd953-5434-4940-b550-acc0ad412913
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328961910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3328961910
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2854248427
Short name T157
Test name
Test status
Simulation time 599358424405 ps
CPU time 1265.84 seconds
Started Jul 25 06:45:06 PM PDT 24
Finished Jul 25 07:06:12 PM PDT 24
Peak memory 201196 kb
Host smart-499776b9-1f2c-42c6-93f5-2e07fe623eac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854248427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2854248427
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.873304979
Short name T633
Test name
Test status
Simulation time 110414286298 ps
CPU time 406.2 seconds
Started Jul 25 06:45:14 PM PDT 24
Finished Jul 25 06:52:00 PM PDT 24
Peak memory 201684 kb
Host smart-c15541a0-4dbd-48ee-a93d-5fdeafc318ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873304979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.873304979
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2258677933
Short name T351
Test name
Test status
Simulation time 22552752499 ps
CPU time 14.08 seconds
Started Jul 25 06:45:13 PM PDT 24
Finished Jul 25 06:45:28 PM PDT 24
Peak memory 201056 kb
Host smart-9089ad95-749f-4640-8271-6d4e6e91dca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258677933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2258677933
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1072371003
Short name T42
Test name
Test status
Simulation time 4871851250 ps
CPU time 12.25 seconds
Started Jul 25 06:45:12 PM PDT 24
Finished Jul 25 06:45:25 PM PDT 24
Peak memory 201084 kb
Host smart-ecaf58db-4c1c-4191-88a2-400b68358c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072371003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1072371003
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1832056674
Short name T394
Test name
Test status
Simulation time 5938561471 ps
CPU time 4.06 seconds
Started Jul 25 06:45:06 PM PDT 24
Finished Jul 25 06:45:10 PM PDT 24
Peak memory 201104 kb
Host smart-169a4844-9ed6-4a8a-9553-9978b62f41f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832056674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1832056674
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1845230205
Short name T198
Test name
Test status
Simulation time 414489721486 ps
CPU time 489.43 seconds
Started Jul 25 06:45:12 PM PDT 24
Finished Jul 25 06:53:22 PM PDT 24
Peak memory 209840 kb
Host smart-09b497ee-19ab-42c8-83b6-753c2e10250c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845230205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1845230205
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1810417168
Short name T678
Test name
Test status
Simulation time 27646450328 ps
CPU time 47.52 seconds
Started Jul 25 06:45:17 PM PDT 24
Finished Jul 25 06:46:05 PM PDT 24
Peak memory 201380 kb
Host smart-9d504a19-8a85-4990-81dd-acd5f26626d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810417168 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1810417168
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1575778615
Short name T423
Test name
Test status
Simulation time 354879141 ps
CPU time 0.76 seconds
Started Jul 25 06:45:13 PM PDT 24
Finished Jul 25 06:45:14 PM PDT 24
Peak memory 201044 kb
Host smart-008cbfb8-5543-44d2-88ef-fd453d560945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575778615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1575778615
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3314082624
Short name T338
Test name
Test status
Simulation time 165270541766 ps
CPU time 139.74 seconds
Started Jul 25 06:45:16 PM PDT 24
Finished Jul 25 06:47:36 PM PDT 24
Peak memory 201276 kb
Host smart-eff4cddd-04fb-497a-b1fc-2c2f18fd48f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314082624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3314082624
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2976870566
Short name T748
Test name
Test status
Simulation time 158210110481 ps
CPU time 96.58 seconds
Started Jul 25 06:45:23 PM PDT 24
Finished Jul 25 06:46:59 PM PDT 24
Peak memory 201224 kb
Host smart-eeb23074-00e2-419a-a8b4-b45c19f3db60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976870566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2976870566
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.695002501
Short name T629
Test name
Test status
Simulation time 159703496385 ps
CPU time 67.6 seconds
Started Jul 25 06:45:12 PM PDT 24
Finished Jul 25 06:46:20 PM PDT 24
Peak memory 201240 kb
Host smart-b73fabc5-4d4a-4188-a766-c5bb1e7327f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695002501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.695002501
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1122551463
Short name T387
Test name
Test status
Simulation time 325285728605 ps
CPU time 180.13 seconds
Started Jul 25 06:45:16 PM PDT 24
Finished Jul 25 06:48:16 PM PDT 24
Peak memory 201212 kb
Host smart-dff2e208-5725-45da-9fdf-16072dbd2e93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122551463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1122551463
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.843830614
Short name T134
Test name
Test status
Simulation time 368489490975 ps
CPU time 757.95 seconds
Started Jul 25 06:45:23 PM PDT 24
Finished Jul 25 06:58:01 PM PDT 24
Peak memory 201316 kb
Host smart-17b1e5c0-07cb-41ba-bd02-795ac3063d38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843830614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.843830614
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2776463841
Short name T755
Test name
Test status
Simulation time 408662835331 ps
CPU time 948.9 seconds
Started Jul 25 06:45:22 PM PDT 24
Finished Jul 25 07:01:11 PM PDT 24
Peak memory 201220 kb
Host smart-90a023c0-7209-4dab-9b2f-3639b26e3caa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776463841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2776463841
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3723886224
Short name T761
Test name
Test status
Simulation time 112730296416 ps
CPU time 590.77 seconds
Started Jul 25 06:45:22 PM PDT 24
Finished Jul 25 06:55:13 PM PDT 24
Peak memory 201692 kb
Host smart-60a2ff61-e8f3-4968-8144-75677b410e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723886224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3723886224
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.4139801000
Short name T462
Test name
Test status
Simulation time 36322060925 ps
CPU time 56.15 seconds
Started Jul 25 06:45:13 PM PDT 24
Finished Jul 25 06:46:09 PM PDT 24
Peak memory 201080 kb
Host smart-8e9be8e5-5f15-4d4e-819f-e759142e9480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139801000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.4139801000
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3091544144
Short name T439
Test name
Test status
Simulation time 5308445701 ps
CPU time 12.37 seconds
Started Jul 25 06:45:23 PM PDT 24
Finished Jul 25 06:45:35 PM PDT 24
Peak memory 201064 kb
Host smart-0962e7eb-799e-4ee2-891e-af878333a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091544144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3091544144
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.263306427
Short name T506
Test name
Test status
Simulation time 5674343281 ps
CPU time 3.95 seconds
Started Jul 25 06:45:13 PM PDT 24
Finished Jul 25 06:45:18 PM PDT 24
Peak memory 201092 kb
Host smart-e60f9a76-ee67-42ac-8dca-1c0f91a431d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263306427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.263306427
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2614237714
Short name T302
Test name
Test status
Simulation time 232505203846 ps
CPU time 130.36 seconds
Started Jul 25 06:45:13 PM PDT 24
Finished Jul 25 06:47:23 PM PDT 24
Peak memory 201216 kb
Host smart-46669bcf-7e9c-42fb-a932-feebad85b0f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614237714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2614237714
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1543849166
Short name T540
Test name
Test status
Simulation time 92553244130 ps
CPU time 141.83 seconds
Started Jul 25 06:45:14 PM PDT 24
Finished Jul 25 06:47:36 PM PDT 24
Peak memory 210108 kb
Host smart-1d072015-a767-4d6b-b37f-c8614b0bf83c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543849166 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1543849166
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.4108101669
Short name T686
Test name
Test status
Simulation time 312186284 ps
CPU time 1 seconds
Started Jul 25 06:40:54 PM PDT 24
Finished Jul 25 06:40:55 PM PDT 24
Peak memory 201052 kb
Host smart-f9619b25-3da4-417c-afc2-943bded70493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108101669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.4108101669
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2331737270
Short name T226
Test name
Test status
Simulation time 321171226414 ps
CPU time 339.83 seconds
Started Jul 25 06:40:53 PM PDT 24
Finished Jul 25 06:46:33 PM PDT 24
Peak memory 201216 kb
Host smart-3f220046-a189-4e03-9fe4-0e3ff09e4ee5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331737270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2331737270
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1950352596
Short name T510
Test name
Test status
Simulation time 366687911223 ps
CPU time 869.19 seconds
Started Jul 25 06:40:52 PM PDT 24
Finished Jul 25 06:55:22 PM PDT 24
Peak memory 201244 kb
Host smart-06c88e93-1e40-4ef3-9bbf-fef4230ce5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950352596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1950352596
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3442002644
Short name T145
Test name
Test status
Simulation time 329312137399 ps
CPU time 127.53 seconds
Started Jul 25 06:40:55 PM PDT 24
Finished Jul 25 06:43:03 PM PDT 24
Peak memory 201240 kb
Host smart-6b96d88b-358f-4faf-9bcf-bde9e668bb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442002644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3442002644
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.797135875
Short name T533
Test name
Test status
Simulation time 490892292963 ps
CPU time 308.13 seconds
Started Jul 25 06:40:54 PM PDT 24
Finished Jul 25 06:46:02 PM PDT 24
Peak memory 201216 kb
Host smart-3f124995-91c5-4757-960b-e48284d509c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=797135875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.797135875
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.4182196823
Short name T693
Test name
Test status
Simulation time 327605608857 ps
CPU time 753.82 seconds
Started Jul 25 06:40:55 PM PDT 24
Finished Jul 25 06:53:29 PM PDT 24
Peak memory 201300 kb
Host smart-a1277769-5146-4558-977b-c444ef185b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182196823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.4182196823
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.527280011
Short name T791
Test name
Test status
Simulation time 156612073126 ps
CPU time 96.25 seconds
Started Jul 25 06:40:55 PM PDT 24
Finished Jul 25 06:42:32 PM PDT 24
Peak memory 201240 kb
Host smart-6e1f25af-5b15-4e01-b99a-e2f044795b75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=527280011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.527280011
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.890687105
Short name T749
Test name
Test status
Simulation time 171580077450 ps
CPU time 381.62 seconds
Started Jul 25 06:40:53 PM PDT 24
Finished Jul 25 06:47:15 PM PDT 24
Peak memory 201312 kb
Host smart-1615ae80-7040-40cf-bd9c-55fd60ba2d00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890687105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.890687105
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4124486493
Short name T644
Test name
Test status
Simulation time 617193610970 ps
CPU time 799.51 seconds
Started Jul 25 06:40:53 PM PDT 24
Finished Jul 25 06:54:13 PM PDT 24
Peak memory 201244 kb
Host smart-15487896-de84-45af-a6fa-938963d9ad79
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124486493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.4124486493
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2524052559
Short name T536
Test name
Test status
Simulation time 69829258319 ps
CPU time 289.7 seconds
Started Jul 25 06:40:57 PM PDT 24
Finished Jul 25 06:45:46 PM PDT 24
Peak memory 201688 kb
Host smart-a3734620-378d-4a6b-815d-094783b605e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524052559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2524052559
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1249182386
Short name T356
Test name
Test status
Simulation time 25608040281 ps
CPU time 58.02 seconds
Started Jul 25 06:40:53 PM PDT 24
Finished Jul 25 06:41:51 PM PDT 24
Peak memory 201076 kb
Host smart-e1f11494-1451-430b-8a37-cf2c732c5229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249182386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1249182386
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1981657269
Short name T710
Test name
Test status
Simulation time 3616295845 ps
CPU time 2.97 seconds
Started Jul 25 06:40:58 PM PDT 24
Finished Jul 25 06:41:01 PM PDT 24
Peak memory 201064 kb
Host smart-9ea2f3b5-8f9b-4609-bd27-86e4edaff552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981657269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1981657269
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3369982331
Short name T444
Test name
Test status
Simulation time 5839963635 ps
CPU time 4.21 seconds
Started Jul 25 06:40:54 PM PDT 24
Finished Jul 25 06:40:58 PM PDT 24
Peak memory 201116 kb
Host smart-ac3e11e4-fbe8-448d-99ef-c45aa9dcc101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369982331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3369982331
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2575482979
Short name T614
Test name
Test status
Simulation time 216151012742 ps
CPU time 114.13 seconds
Started Jul 25 06:40:53 PM PDT 24
Finished Jul 25 06:42:48 PM PDT 24
Peak memory 201160 kb
Host smart-e725b8d1-a1c9-4c30-9732-e5c573d11074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575482979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2575482979
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.77046497
Short name T189
Test name
Test status
Simulation time 72042577401 ps
CPU time 45.34 seconds
Started Jul 25 06:40:55 PM PDT 24
Finished Jul 25 06:41:40 PM PDT 24
Peak memory 201332 kb
Host smart-cc4df2b4-f8dd-4384-98ae-c79e6cb14f06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77046497 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.77046497
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.301840029
Short name T70
Test name
Test status
Simulation time 506904534 ps
CPU time 0.8 seconds
Started Jul 25 06:40:59 PM PDT 24
Finished Jul 25 06:41:00 PM PDT 24
Peak memory 201028 kb
Host smart-8bddfb26-9af0-47dc-9ba9-2a2f6b27063c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301840029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.301840029
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1624171359
Short name T744
Test name
Test status
Simulation time 185654942992 ps
CPU time 379.93 seconds
Started Jul 25 06:40:53 PM PDT 24
Finished Jul 25 06:47:14 PM PDT 24
Peak memory 201264 kb
Host smart-187448bc-64b4-4a64-8a9c-2e1338dee4fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624171359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1624171359
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1268145993
Short name T148
Test name
Test status
Simulation time 158691051657 ps
CPU time 178.26 seconds
Started Jul 25 06:40:53 PM PDT 24
Finished Jul 25 06:43:51 PM PDT 24
Peak memory 201256 kb
Host smart-7bab73d5-5e99-486e-84f9-9883e19fca5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268145993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1268145993
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3489517742
Short name T92
Test name
Test status
Simulation time 487165735673 ps
CPU time 530.2 seconds
Started Jul 25 06:40:56 PM PDT 24
Finished Jul 25 06:49:47 PM PDT 24
Peak memory 201236 kb
Host smart-6d1adc36-ce7d-4186-b81f-643f181edad2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489517742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3489517742
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3015099241
Short name T600
Test name
Test status
Simulation time 167738202845 ps
CPU time 67.66 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:42:08 PM PDT 24
Peak memory 201212 kb
Host smart-867d070e-d21c-4bcd-a2c6-ab6c796c015d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015099241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3015099241
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1721771826
Short name T503
Test name
Test status
Simulation time 484428861400 ps
CPU time 162.08 seconds
Started Jul 25 06:40:57 PM PDT 24
Finished Jul 25 06:43:39 PM PDT 24
Peak memory 201232 kb
Host smart-1a4ad6af-244e-488c-b477-dcbd4c0d9da6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721771826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1721771826
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3747839938
Short name T571
Test name
Test status
Simulation time 344151968324 ps
CPU time 118.64 seconds
Started Jul 25 06:40:56 PM PDT 24
Finished Jul 25 06:42:54 PM PDT 24
Peak memory 201264 kb
Host smart-aaaac2c4-15ce-4ec3-8efa-0edb893426fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747839938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3747839938
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.761864971
Short name T455
Test name
Test status
Simulation time 198237385868 ps
CPU time 106.84 seconds
Started Jul 25 06:40:57 PM PDT 24
Finished Jul 25 06:42:45 PM PDT 24
Peak memory 201212 kb
Host smart-c905acac-005c-4ee0-8f4c-3e60d7e1cf81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761864971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.761864971
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3859841832
Short name T203
Test name
Test status
Simulation time 119695933993 ps
CPU time 484.26 seconds
Started Jul 25 06:41:02 PM PDT 24
Finished Jul 25 06:49:07 PM PDT 24
Peak memory 201680 kb
Host smart-65426846-d4cb-405d-9255-14c1a456d096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859841832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3859841832
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3041276847
Short name T360
Test name
Test status
Simulation time 40242068168 ps
CPU time 42.4 seconds
Started Jul 25 06:41:06 PM PDT 24
Finished Jul 25 06:41:48 PM PDT 24
Peak memory 201072 kb
Host smart-44fa52ba-dec0-4f6d-b999-a8d9382a6900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041276847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3041276847
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.4188468953
Short name T397
Test name
Test status
Simulation time 3568364457 ps
CPU time 5.76 seconds
Started Jul 25 06:40:55 PM PDT 24
Finished Jul 25 06:41:01 PM PDT 24
Peak memory 201132 kb
Host smart-c9074c6d-029c-4a08-ab47-61d8bcee858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188468953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4188468953
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2279496386
Short name T790
Test name
Test status
Simulation time 5617433347 ps
CPU time 7.19 seconds
Started Jul 25 06:40:56 PM PDT 24
Finished Jul 25 06:41:03 PM PDT 24
Peak memory 201116 kb
Host smart-3c48fac3-2134-406e-9da1-8bf7a4d61016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279496386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2279496386
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.807490322
Short name T746
Test name
Test status
Simulation time 210156381216 ps
CPU time 447.33 seconds
Started Jul 25 06:41:55 PM PDT 24
Finished Jul 25 06:49:22 PM PDT 24
Peak memory 201316 kb
Host smart-0d9d3f89-712a-4a0e-acf6-4b235036030f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807490322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.807490322
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.8843175
Short name T671
Test name
Test status
Simulation time 378584237 ps
CPU time 0.83 seconds
Started Jul 25 06:41:05 PM PDT 24
Finished Jul 25 06:41:06 PM PDT 24
Peak memory 201004 kb
Host smart-4dff8697-0312-409b-bd0d-29fac436f439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8843175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.8843175
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1278158023
Short name T546
Test name
Test status
Simulation time 509632271663 ps
CPU time 720.82 seconds
Started Jul 25 06:41:01 PM PDT 24
Finished Jul 25 06:53:02 PM PDT 24
Peak memory 201240 kb
Host smart-702554ae-0446-4572-ad40-9580c53bbea8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278158023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1278158023
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2735790495
Short name T634
Test name
Test status
Simulation time 164288160898 ps
CPU time 356.06 seconds
Started Jul 25 06:41:05 PM PDT 24
Finished Jul 25 06:47:01 PM PDT 24
Peak memory 201284 kb
Host smart-d5583875-322e-48db-9ee8-256b027e2064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735790495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2735790495
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2804275874
Short name T391
Test name
Test status
Simulation time 493394822950 ps
CPU time 1130.15 seconds
Started Jul 25 06:41:01 PM PDT 24
Finished Jul 25 06:59:51 PM PDT 24
Peak memory 201288 kb
Host smart-4fa86796-07f5-40e5-baf6-f6b956d87d04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804275874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2804275874
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3877872749
Short name T621
Test name
Test status
Simulation time 332157407723 ps
CPU time 386.61 seconds
Started Jul 25 06:41:04 PM PDT 24
Finished Jul 25 06:47:31 PM PDT 24
Peak memory 201292 kb
Host smart-40f91f87-fb09-49e1-aae3-224da202668c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877872749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3877872749
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2361400268
Short name T167
Test name
Test status
Simulation time 339785203808 ps
CPU time 180.84 seconds
Started Jul 25 06:41:02 PM PDT 24
Finished Jul 25 06:44:02 PM PDT 24
Peak memory 201212 kb
Host smart-b5b5f2a9-c26b-4e99-98c3-031444d65c06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361400268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2361400268
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2427977063
Short name T319
Test name
Test status
Simulation time 201973883761 ps
CPU time 120.41 seconds
Started Jul 25 06:40:59 PM PDT 24
Finished Jul 25 06:43:00 PM PDT 24
Peak memory 201228 kb
Host smart-99d8e5db-4ccc-4381-a796-f79418bcc1f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427977063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2427977063
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2753963149
Short name T352
Test name
Test status
Simulation time 570918122689 ps
CPU time 1267.58 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 07:02:08 PM PDT 24
Peak memory 201264 kb
Host smart-5794db5e-c3e5-4cd4-81f2-9f28f00be4e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753963149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2753963149
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.633069172
Short name T501
Test name
Test status
Simulation time 107461632866 ps
CPU time 593.84 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:50:54 PM PDT 24
Peak memory 201664 kb
Host smart-c2d66b41-99c9-4a81-9325-46d1c45d6c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633069172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.633069172
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2931050898
Short name T547
Test name
Test status
Simulation time 31904865467 ps
CPU time 19 seconds
Started Jul 25 06:41:01 PM PDT 24
Finished Jul 25 06:41:20 PM PDT 24
Peak memory 201056 kb
Host smart-be339fc0-8a6a-4c1e-8631-e1ae1edb646b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931050898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2931050898
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3958995499
Short name T395
Test name
Test status
Simulation time 4771025892 ps
CPU time 11.76 seconds
Started Jul 25 06:41:03 PM PDT 24
Finished Jul 25 06:41:15 PM PDT 24
Peak memory 201072 kb
Host smart-94fef109-c185-4c30-bbaa-9c1c2e1302e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958995499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3958995499
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1738999085
Short name T674
Test name
Test status
Simulation time 5935669237 ps
CPU time 14.22 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:41:14 PM PDT 24
Peak memory 201140 kb
Host smart-ac1e1e37-fc23-4a67-b965-e921007e8b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738999085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1738999085
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1504311858
Short name T765
Test name
Test status
Simulation time 441719495 ps
CPU time 1.68 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:41:02 PM PDT 24
Peak memory 201052 kb
Host smart-335af787-9b8e-40d3-be86-a0261f2b3ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504311858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1504311858
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2081944029
Short name T667
Test name
Test status
Simulation time 367627989558 ps
CPU time 304.7 seconds
Started Jul 25 06:41:03 PM PDT 24
Finished Jul 25 06:46:08 PM PDT 24
Peak memory 201228 kb
Host smart-3d0fb198-f741-4784-a460-457bef1b8dc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081944029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2081944029
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1338493069
Short name T339
Test name
Test status
Simulation time 164927383889 ps
CPU time 403.88 seconds
Started Jul 25 06:40:58 PM PDT 24
Finished Jul 25 06:47:42 PM PDT 24
Peak memory 201216 kb
Host smart-80c4ded1-3844-4909-9426-79619fec3fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338493069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1338493069
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2299720712
Short name T604
Test name
Test status
Simulation time 333890194247 ps
CPU time 188.38 seconds
Started Jul 25 06:41:03 PM PDT 24
Finished Jul 25 06:44:11 PM PDT 24
Peak memory 201236 kb
Host smart-2a89e909-00cc-4e68-aa20-70adbbbecf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299720712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2299720712
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1950238763
Short name T453
Test name
Test status
Simulation time 488060725035 ps
CPU time 324.08 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:46:25 PM PDT 24
Peak memory 201252 kb
Host smart-0c269640-62fc-45e2-93f6-c13ff0e80dcf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950238763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1950238763
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2957540595
Short name T554
Test name
Test status
Simulation time 326728234226 ps
CPU time 358.24 seconds
Started Jul 25 06:41:02 PM PDT 24
Finished Jul 25 06:47:00 PM PDT 24
Peak memory 201228 kb
Host smart-a48d47b9-2367-4896-aeea-18c9b27b3040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957540595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2957540595
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.615379457
Short name T782
Test name
Test status
Simulation time 491216539991 ps
CPU time 1185.27 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 07:00:46 PM PDT 24
Peak memory 201244 kb
Host smart-36e9b003-fd24-441a-aba8-631450af993b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=615379457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.615379457
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2695399438
Short name T264
Test name
Test status
Simulation time 350811235377 ps
CPU time 817.16 seconds
Started Jul 25 06:41:05 PM PDT 24
Finished Jul 25 06:54:42 PM PDT 24
Peak memory 201236 kb
Host smart-5c4a033a-ae2d-4058-975b-dc3dad11a3c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695399438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2695399438
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.420486254
Short name T786
Test name
Test status
Simulation time 593152519631 ps
CPU time 356.76 seconds
Started Jul 25 06:41:01 PM PDT 24
Finished Jul 25 06:46:58 PM PDT 24
Peak memory 201220 kb
Host smart-dd519970-08d1-4a92-b4eb-4908fed50e5c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420486254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.420486254
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.4202185555
Short name T196
Test name
Test status
Simulation time 99111961509 ps
CPU time 355.57 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:46:56 PM PDT 24
Peak memory 201720 kb
Host smart-ad1524d6-bf96-4b30-8498-a997529ae80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202185555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.4202185555
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2811909360
Short name T398
Test name
Test status
Simulation time 43775408775 ps
CPU time 26.3 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:41:27 PM PDT 24
Peak memory 201088 kb
Host smart-705814a1-0179-48c2-b47c-27538cdf752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811909360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2811909360
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2335704530
Short name T784
Test name
Test status
Simulation time 5363601756 ps
CPU time 6.83 seconds
Started Jul 25 06:41:03 PM PDT 24
Finished Jul 25 06:41:10 PM PDT 24
Peak memory 201048 kb
Host smart-96d339c9-2455-47d5-b3a7-4f9dc2fa3d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335704530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2335704530
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1568589365
Short name T349
Test name
Test status
Simulation time 5888486783 ps
CPU time 6.17 seconds
Started Jul 25 06:41:02 PM PDT 24
Finished Jul 25 06:41:08 PM PDT 24
Peak memory 201104 kb
Host smart-9ba34d96-632e-4f3b-80c1-fa4c5745dbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568589365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1568589365
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3787829899
Short name T452
Test name
Test status
Simulation time 167744659705 ps
CPU time 99.58 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:42:40 PM PDT 24
Peak memory 201232 kb
Host smart-2fc16390-f50d-4281-b34c-0f04335c2b1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787829899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3787829899
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2594903448
Short name T17
Test name
Test status
Simulation time 293308034397 ps
CPU time 491.89 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:49:13 PM PDT 24
Peak memory 210088 kb
Host smart-7d51cd42-7dff-47d2-bd8f-609401e56c5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594903448 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2594903448
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.4015588183
Short name T463
Test name
Test status
Simulation time 353910862 ps
CPU time 1.43 seconds
Started Jul 25 06:41:05 PM PDT 24
Finished Jul 25 06:41:07 PM PDT 24
Peak memory 201052 kb
Host smart-4251a31c-c312-480a-af70-299210c18508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015588183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.4015588183
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1633556843
Short name T593
Test name
Test status
Simulation time 166543043929 ps
CPU time 380.24 seconds
Started Jul 25 06:41:11 PM PDT 24
Finished Jul 25 06:47:32 PM PDT 24
Peak memory 201260 kb
Host smart-629517c6-a8d7-4faa-ac6a-dce2fb71d60f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633556843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1633556843
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2866475958
Short name T132
Test name
Test status
Simulation time 167305152780 ps
CPU time 199.65 seconds
Started Jul 25 06:41:07 PM PDT 24
Finished Jul 25 06:44:27 PM PDT 24
Peak memory 201308 kb
Host smart-f6452f86-2834-44f9-82aa-10663a85ed56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866475958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2866475958
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2028464680
Short name T698
Test name
Test status
Simulation time 164772286203 ps
CPU time 109.19 seconds
Started Jul 25 06:41:08 PM PDT 24
Finished Jul 25 06:42:58 PM PDT 24
Peak memory 201200 kb
Host smart-9f7b5a66-59e8-459c-8bea-7173d9700133
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028464680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2028464680
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3644539845
Short name T91
Test name
Test status
Simulation time 331320751364 ps
CPU time 671.97 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:52:13 PM PDT 24
Peak memory 201300 kb
Host smart-2d206a60-07f7-47c8-ad5b-cbe53c1a821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644539845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3644539845
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2335429618
Short name T594
Test name
Test status
Simulation time 326499194349 ps
CPU time 340.75 seconds
Started Jul 25 06:41:00 PM PDT 24
Finished Jul 25 06:46:41 PM PDT 24
Peak memory 201252 kb
Host smart-548b8aa6-8ce8-40a4-afe5-5703964c8a4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335429618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2335429618
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1157875830
Short name T775
Test name
Test status
Simulation time 521235051506 ps
CPU time 256.64 seconds
Started Jul 25 06:41:08 PM PDT 24
Finished Jul 25 06:45:24 PM PDT 24
Peak memory 201172 kb
Host smart-eeb485d3-9d7c-4739-b072-8cef64cb2c9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157875830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1157875830
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2542851533
Short name T548
Test name
Test status
Simulation time 403959868715 ps
CPU time 243.89 seconds
Started Jul 25 06:41:13 PM PDT 24
Finished Jul 25 06:45:17 PM PDT 24
Peak memory 201252 kb
Host smart-7fdb04d2-b7ce-4a50-a15d-499348d6d1f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542851533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2542851533
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1175061902
Short name T769
Test name
Test status
Simulation time 103755653609 ps
CPU time 581.51 seconds
Started Jul 25 06:41:08 PM PDT 24
Finished Jul 25 06:50:50 PM PDT 24
Peak memory 201696 kb
Host smart-245d3b2e-ae66-4f71-aed6-7f4c1ee4071f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175061902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1175061902
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2003421890
Short name T576
Test name
Test status
Simulation time 23773224249 ps
CPU time 57.74 seconds
Started Jul 25 06:41:08 PM PDT 24
Finished Jul 25 06:42:06 PM PDT 24
Peak memory 201040 kb
Host smart-5d367981-a810-4d4a-92fa-14b4ea1ddc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003421890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2003421890
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3423317890
Short name T475
Test name
Test status
Simulation time 4955539984 ps
CPU time 12.64 seconds
Started Jul 25 06:41:09 PM PDT 24
Finished Jul 25 06:41:22 PM PDT 24
Peak memory 201080 kb
Host smart-0a696a1a-a0af-4e3f-a8cd-4db5f76aa6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423317890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3423317890
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.570508081
Short name T105
Test name
Test status
Simulation time 5642971648 ps
CPU time 13.93 seconds
Started Jul 25 06:41:02 PM PDT 24
Finished Jul 25 06:41:16 PM PDT 24
Peak memory 201088 kb
Host smart-c89dbeef-7e9c-426d-8726-edeb811a1552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570508081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.570508081
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1740341562
Short name T336
Test name
Test status
Simulation time 169985737750 ps
CPU time 207.15 seconds
Started Jul 25 06:41:07 PM PDT 24
Finished Jul 25 06:44:35 PM PDT 24
Peak memory 201236 kb
Host smart-b4ebc0e0-19e0-4b99-8b50-d891175813ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740341562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1740341562
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3478554319
Short name T243
Test name
Test status
Simulation time 70645182519 ps
CPU time 161.07 seconds
Started Jul 25 06:41:13 PM PDT 24
Finished Jul 25 06:43:54 PM PDT 24
Peak memory 209600 kb
Host smart-2549f9d3-bfc7-4b0c-84e6-92c5f8ef7217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478554319 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3478554319
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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