Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6604	1			T1	10		T6	83		T7	64
testmodes[AdcCtrlTestmodeNormal]	5206	1			T1	10		T2	3		T5	3
testmodes[AdcCtrlTestmodeLowpower]	5381	1			T3	1		T6	23		T7	76
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3619	1			T1	4		T6	64		T7	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1617	1			T1	6		T6	9		T7	23
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1259	1			T6	9		T7	22		T45	17
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1661	1			T1	5		T6	11		T7	28
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1918	1			T1	4		T2	2		T5	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1277	1			T6	4		T7	29		T41	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1219	1			T6	8		T7	17		T45	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1326	1			T6	6		T7	33		T51	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2596	1			T6	9		T7	25		T8	13