Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22038

1

T1

20

T2

31

T5

38

auto[ADC_CTRL_FILTER_COND_OUT]

3647

1

T3

9

T7

44

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19391

1

T1

20

T2

27

T3

9

auto[1]

6294

1

T2

4

T7

22

T9

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T215	1		-	-		-	-
values[0]	47	1			T145	28		T31	7		T216	9
values[1]	833	1			T51	29		T143	13		T154	11
values[2]	877	1			T5	17		T12	10		T44	16
values[3]	633	1			T10	12		T41	11		T45	30
values[4]	774	1			T12	23		T51	2		T152	14
values[5]	2944	1			T2	4		T3	9		T11	14
values[6]	748	1			T7	22		T10	11		T45	1
values[7]	805	1			T2	27		T9	3		T41	7
values[8]	657	1			T5	8		T7	22		T152	16
values[9]	1112	1			T5	13		T6	2		T10	14
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1073	1			T44	16		T51	29		T143	44
values[1]	793	1			T5	17		T12	10		T41	11
values[2]	586	1			T10	12		T45	15		T135	8
values[3]	2999	1			T2	4		T11	14		T12	23
values[4]	799	1			T3	9		T10	11		T45	1
values[5]	832	1			T2	22		T9	2		T25	5
values[6]	725	1			T2	5		T7	44		T9	1
values[7]	628	1			T5	21		T13	14		T152	16
values[8]	861	1			T6	2		T10	14		T12	1
values[9]	108	1			T147	17		T20	6		T217	29
minimum	16281	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T51	18		T143	17		T174	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T44	16		T143	10		T145	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	9		T12	10		T45	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T41	5		T138	1		T186	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T45	8		T135	8		T26	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	1		T155	22		T218	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T2	1		T11	14		T12	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T134	13		T143	16		T135	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T10	1		T45	1		T145	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	9		T26	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	12		T9	1		T25	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T9	1		T219	16		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	3		T9	1		T41	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	27		T155	14		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	14		T13	1		T152	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T163	1		T187	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	2		T12	1		T43	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	1		T132	15		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T147	1		T222	1		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T20	4		T217	16		T224	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16113	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T216	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T51	11		T143	14		T174	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T143	3		T145	30		T14	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	8		T45	7		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	6		T138	8		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T45	7		T26	7		T77	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	11		T149	13		T179	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	898	1			T2	3		T12	10		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T134	13		T143	11		T80	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	10		T145	9		T164	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T26	11		T178	9		T18	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	10		T15	1		T137	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T219	16		T147	8		T148	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	2		T41	2		T43	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	17		T187	10		T100	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T5	7		T13	3		T190	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	9		T163	2		T187	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T43	10		T132	14		T187	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T10	13		T132	11		T138	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T147	16		T222	4		T223	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T20	2		T217	13		T182	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	2		T14	1		T25	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T215	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T225	1		T226	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T145	11		T31	4		T216	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T51	18		T154	1		T174	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T143	10		T77	12		T80	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	9		T12	10		T143	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T44	16		T145	16		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T45	16		T135	7		T26	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	1		T41	5		T155	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	13		T51	1		T152	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T135	11		T80	1		T227	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T2	1		T11	14		T141	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	9		T134	13		T143	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	1		T45	1		T25	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	12		T219	16		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T2	15		T9	2		T41	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	1		T155	14		T187	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	8		T152	16		T155	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	15		T163	1		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T5	6		T6	2		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	1		T13	1		T132	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T145	17		T31	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T51	11		T154	10		T174	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T143	3		T77	2		T80	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	8		T143	14		T149	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T145	13		T138	8		T14	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T45	14		T26	7		T77	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	11		T41	6		T149	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	10		T51	1		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T80	2		T227	10		T39	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	883	1			T2	3		T134	6		T161	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T134	13		T143	11		T26	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	10		T15	1		T228	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	10		T219	16		T147	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	12		T41	2		T43	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T187	10		T100	1		T229	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T190	2		T36	5		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	7		T163	2		T230	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	7		T13	3		T43	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T10	13		T13	9		T132	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9] , minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T51	12		T143	15		T174	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T44	1		T143	4		T145	32
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T5	9		T12	1		T45	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T41	7		T138	9		T186	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T45	8		T135	1		T26	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	12		T155	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T2	4		T11	1		T12	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T134	14		T143	12		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T10	11		T45	1		T145	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	1		T26	12		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	11		T9	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	1		T219	17		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	3		T9	1		T41	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	19		T155	1		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	9		T13	4		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	10		T163	3		T187	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	2		T12	1		T43	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T10	14		T132	12		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T147	17		T222	5		T223	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T20	5		T217	14		T224	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16272	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T216	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T51	17		T143	16		T77	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T44	15		T143	9		T145	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	8		T12	9		T45	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T41	4		T150	15		T192	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T45	7		T135	7		T26	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T155	21		T218	11		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T11	13		T12	12		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T134	12		T143	15		T135	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T145	9		T82	13		T164	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	8		T178	5		T18	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	11		T25	4		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T219	15		T148	8		T229	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	2		T41	4		T43	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	25		T155	13		T187	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	12		T152	15		T139	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T187	2		T231	1		T232	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T43	9		T141	14		T132	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T132	14		T219	9		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T20	1		T217	15		T224	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T216	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T215	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T225	1		T226	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T145	18		T31	5		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T51	12		T154	11		T174	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T143	4		T77	3		T80	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T5	9		T12	1		T143	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T44	1		T145	14		T138	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T45	16		T135	1		T26	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	12		T41	7		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	11		T51	2		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T135	1		T80	3		T227	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T2	4		T11	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	1		T134	14		T143	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	11		T45	1		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	11		T219	17		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T2	14		T9	2		T41	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	1		T155	1		T187	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T5	1		T152	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	8		T163	3		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T5	8		T6	2		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	397	1			T10	14		T13	10		T132	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T145	10		T31	2		T216	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T51	17		T77	19		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T143	9		T77	11		T80	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	8		T12	9		T143	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T44	15		T145	15		T14	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T45	14		T135	6		T26	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T41	4		T155	21		T218	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	12		T152	13		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T135	10		T227	4		T39	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T11	13		T141	2		T134	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	8		T134	12		T143	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T25	4		T15	1		T80	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	11		T219	15		T148	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	13		T41	4		T43	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T155	13		T187	11		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	7		T152	15		T155	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	14		T230	10		T231	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T5	5		T43	9		T141	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T132	14		T219	9		T187	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21989

1

T1

20

T5

38

T6

130

auto[ADC_CTRL_FILTER_COND_OUT]

3696

1

T2

31

T3

9

T7

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19236

1

T1

20

T2

9

T5

8

auto[1]

6449

1

T2

22

T3

9

T5

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T147	9		T233	1		T234	1
values[0]	28	1			T187	2		T38	7		T235	19
values[1]	814	1			T141	3		T134	26		T143	13
values[2]	700	1			T12	1		T143	31		T221	1
values[3]	813	1			T2	22		T7	22		T13	10
values[4]	792	1			T5	13		T6	2		T51	29
values[5]	2916	1			T10	12		T11	14		T12	33
values[6]	754	1			T2	5		T3	9		T43	9
values[7]	669	1			T5	17		T9	3		T10	11
values[8]	778	1			T7	22		T10	14		T141	15
values[9]	1156	1			T2	4		T5	8		T41	7
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	985	1			T141	3		T134	26		T143	13
values[1]	716	1			T12	1		T143	31		T152	16
values[2]	914	1			T2	22		T7	22		T13	10
values[3]	2805	1			T5	13		T6	2		T11	14
values[4]	904	1			T2	5		T10	12		T12	23
values[5]	616	1			T3	9		T5	17		T134	11
values[6]	801	1			T7	22		T9	2		T10	11
values[7]	580	1			T2	4		T9	1		T10	14
values[8]	831	1			T5	8		T41	7		T141	15
values[9]	266	1			T45	1		T26	12		T236	14
minimum	16267	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T132	6		T152	14		T135	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T141	3		T134	13		T143	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T221	1		T138	1		T155	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	1		T143	17		T152	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T45	8		T14	9		T155	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T2	12		T7	12		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T5	6		T6	2		T11	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T41	5		T164	4		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T12	13		T144	1		T145	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	3		T10	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	9		T134	5		T227	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	9		T145	10		T77	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	15		T9	1		T43	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	1		T10	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	1		T10	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	1		T80	2		T139	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	8		T15	4		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T41	5		T141	15		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T237	14		T238	7		T91	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T45	1		T26	1		T236	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T180	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T132	14		T219	16		T39	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T134	13		T143	3		T145	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T138	4		T80	2		T137	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T143	14		T138	8		T187	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T45	7		T14	6		T239	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	10		T7	10		T13	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	850	1			T5	7		T51	11		T161	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T41	6		T164	11		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T12	10		T144	5		T145	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	2		T10	11		T174	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T5	8		T134	6		T227	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T145	9		T77	2		T228	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	7		T43	16		T26	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	10		T13	3		T137	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T10	13		T190	2		T240	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T2	3		T219	9		T187	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	1		T80	13		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T41	2		T51	1		T132	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T238	7		T91	10		T241	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T26	11		T236	6		T77	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T180	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T147	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T233	1		T234	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T187	1		T38	5		T235	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T132	6		T152	14		T135	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T141	3		T134	13		T143	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T221	1		T138	1		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T143	17		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T14	9		T155	23		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	12		T7	12		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	6		T6	2		T51	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T186	1		T38	2		T242	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1582	1			T11	14		T12	23		T44	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	1		T174	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T43	3		T134	5		T145	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	3		T3	9		T77	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	9		T9	2		T43	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	1		T10	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T7	15		T10	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T141	15		T80	2		T219	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T5	8		T15	4		T80	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T2	1		T41	5		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T147	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T187	1		T38	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T132	14		T219	16		T39	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T134	13		T143	3		T145	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	4		T80	2		T106	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T143	14		T138	8		T147	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	6		T137	6		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	10		T7	10		T13	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	7		T51	11		T45	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T38	1		T242	6		T229	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	900	1			T12	10		T144	5		T161	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	11		T174	4		T164	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T43	6		T134	6		T145	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	2		T77	2		T16	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T5	8		T43	10		T100	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	10		T13	3		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	7		T10	13		T190	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T219	9		T187	4		T244	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T15	1		T80	13		T227	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T2	3		T41	2		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2