Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21920

1

T1

20

T5

38

T6

130

auto[ADC_CTRL_FILTER_COND_OUT]

3765

1

T2

31

T3

9

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19196

1

T1

20

T2

9

T5

8

auto[1]

6489

1

T2

22

T3

9

T5

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	179	1			T45	16		T26	12		T236	14
values[0]	20	1			T187	2		T38	7		T308	11
values[1]	915	1			T141	3		T134	26		T143	13
values[2]	612	1			T12	1		T143	31		T221	1
values[3]	877	1			T2	22		T7	22		T13	10
values[4]	714	1			T5	13		T6	2		T51	29
values[5]	3000	1			T2	5		T10	12		T11	14
values[6]	683	1			T3	9		T43	9		T134	11
values[7]	646	1			T5	17		T9	3		T10	11
values[8]	762	1			T7	22		T10	14		T141	15
values[9]	1023	1			T2	4		T5	8		T41	7
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	865	1			T141	3		T134	26		T143	13
values[1]	663	1			T12	1		T143	31		T152	16
values[2]	922	1			T2	22		T7	22		T13	10
values[3]	2822	1			T5	13		T6	2		T11	14
values[4]	897	1			T2	5		T10	12		T12	23
values[5]	585	1			T3	9		T5	17		T43	9
values[6]	761	1			T7	22		T9	2		T10	11
values[7]	648	1			T2	4		T9	1		T10	14
values[8]	910	1			T5	8		T41	7		T132	26
values[9]	159	1			T51	2		T45	1		T26	12
minimum	16453	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T141	3		T132	6		T135	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T134	13		T143	10		T152	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T221	1		T138	1		T155	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	1		T143	17		T152	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	12		T14	9		T155	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	12		T13	1		T41	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T5	6		T6	2		T11	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T164	4		T38	2		T151	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T145	11		T135	11		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	3		T10	1		T12	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	9		T43	3		T134	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	9		T145	10		T77	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	15		T9	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T10	1		T297	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	1		T10	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	1		T141	15		T80	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	8		T15	4		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T41	5		T132	15		T45	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T257	5		T238	7		T91	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T51	1		T45	1		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16188	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T186	1		T187	1		T38	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T132	14		T228	4		T106	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T134	13		T143	3		T145	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T138	4		T80	2		T148	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T143	14		T138	8		T137	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	10		T14	6		T239	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	10		T13	9		T41	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	866	1			T5	7		T51	11		T45	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T164	11		T38	1		T309	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T145	17		T138	11		T77	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	2		T10	11		T12	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T5	8		T43	6		T134	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T145	9		T77	2		T16	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	7		T13	3		T43	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	10		T137	9		T106	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T10	13		T190	2		T149	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	3		T219	9		T187	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T15	1		T80	13		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T41	2		T132	11		T45	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T257	2		T238	7		T91	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T51	1		T26	11		T236	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	2		T14	1		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T187	1		T38	2		T280	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T80	1		T151	1		T20	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T45	9		T26	1		T236	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T308	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T187	1		T38	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T141	3		T132	6		T135	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T134	13		T143	10		T152	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T221	1		T138	1		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T143	17		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	12		T14	9		T155	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	12		T13	1		T41	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	6		T6	2		T51	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T38	2		T242	4		T229	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1639	1			T11	14		T12	10		T44	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	3		T10	1		T12	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T43	3		T134	5		T145	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	9		T77	12		T297	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	9		T9	2		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T10	1		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T7	15		T10	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T141	15		T80	2		T219	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T5	8		T15	4		T227	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T2	1		T41	5		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T80	13		T20	8		T263	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T45	7		T26	11		T236	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T308	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T187	1		T38	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T132	14		T219	16		T228	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T134	13		T143	3		T145	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	4		T80	2		T150	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T143	14		T138	8		T137	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	10		T14	6		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	10		T13	9		T41	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	7		T51	11		T45	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T38	1		T242	6		T229	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T161	26		T138	11		T77	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	2		T10	11		T12	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T43	6		T134	6		T145	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T77	2		T16	6		T228	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T5	8		T13	3		T43	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	10		T145	9		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	7		T10	13		T190	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T219	9		T187	4		T244	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T15	1		T227	2		T164	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	3		T41	2		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T141	1		T132	15		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T134	14		T143	4		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T221	1		T138	5		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T143	15		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T7	11		T14	11		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	11		T13	10		T41	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T5	8		T6	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T164	12		T38	2		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T145	18		T135	1		T138	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	3		T10	12		T12	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	9		T43	7		T134	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	1		T145	10		T77	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	8		T9	1		T13	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	1		T10	11		T297	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T9	1		T10	14		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	4		T141	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T5	1		T15	4		T80	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T41	3		T132	12		T45	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T257	5		T238	8		T91	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T51	2		T45	1		T26	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16331	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T186	1		T187	2		T38	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T141	2		T132	5		T135	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T134	12		T143	9		T152	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T155	13		T148	8		T150	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T143	16		T152	15		T75	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	11		T14	4		T155	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	11		T41	4		T143	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T5	5		T11	13		T12	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T164	3		T38	1		T151	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T145	10		T135	10		T25	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	2		T12	12		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	8		T43	2		T134	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	8		T145	9		T77	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	14		T43	9		T135	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T106	2		T235	16		T35	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T190	12		T149	8		T240	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T141	14		T80	1		T139	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	7		T15	1		T227	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T41	4		T132	14		T45	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T257	2		T238	6		T91	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T236	7		T90	11		T287	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T219	15		T39	5		T239	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T254	1		T310	7		T311	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T80	14		T151	1		T20	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T45	9		T26	12		T236	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T308	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T187	2		T38	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T141	1		T132	15		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T134	14		T143	4		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T221	1		T138	5		T80	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	1		T143	15		T138	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T7	11		T14	11		T155	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	11		T13	10		T41	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	8		T6	2		T51	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T38	2		T242	7		T229	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T11	1		T12	1		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	3		T10	12		T12	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T43	7		T134	7		T145	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	1		T77	3		T297	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	9		T9	2		T13	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	1		T10	11		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	8		T10	14		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T141	1		T80	1		T219	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T5	1		T15	4		T227	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T2	4		T41	3		T51	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T20	1		T263	1		T91	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T45	7		T236	7		T246	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T141	2		T132	5		T135	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T134	12		T143	9		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T82	2		T150	4		T247	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T143	16		T75	12		T187	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	11		T14	4		T155	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	11		T41	4		T143	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	5		T51	17		T45	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T38	1		T242	3		T229	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T11	13		T12	9		T44	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	2		T12	12		T164	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T43	2		T134	4		T145	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	8		T77	11		T16	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	8		T43	9		T135	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T145	9		T106	2		T235	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	14		T190	12		T164	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T141	14		T80	1		T219	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T5	7		T15	1		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T41	4		T132	14		T77	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20