Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22114

1

T1

20

T2

9

T5

8

auto[ADC_CTRL_FILTER_COND_OUT]

3571

1

T2

22

T3

9

T5

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19404

1

T1

20

T2

4

T5

25

auto[1]

6281

1

T2

27

T3

9

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	399	1			T5	8		T7	22		T51	29
values[0]	38	1			T218	12		T230	25		T253	1
values[1]	780	1			T9	1		T43	20		T144	6
values[2]	692	1			T2	5		T41	11		T135	8
values[3]	558	1			T12	1		T141	15		T152	30
values[4]	882	1			T5	17		T9	1		T10	12
values[5]	698	1			T2	22		T5	13		T134	11
values[6]	576	1			T6	2		T12	23		T77	13
values[7]	771	1			T10	25		T13	4		T41	7
values[8]	3138	1			T11	14		T12	10		T145	28
values[9]	899	1			T2	4		T3	9		T7	22
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	617	1			T9	1		T43	20		T144	6
values[1]	704	1			T2	5		T41	11		T152	30
values[2]	770	1			T5	17		T12	1		T141	18
values[3]	723	1			T9	1		T10	12		T13	10
values[4]	691	1			T2	22		T5	13		T12	23
values[5]	620	1			T6	2		T10	11		T13	4
values[6]	2948	1			T10	14		T11	14		T12	10
values[7]	885	1			T31	2		T174	5		T137	7
values[8]	982	1			T2	4		T3	9		T7	44
values[9]	182	1			T5	8		T134	26		T143	13
minimum	16563	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	1		T154	1		T15	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T43	10		T144	1		T187	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	3		T41	5		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T152	30		T135	8		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T141	18		T145	10		T155	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	9		T12	1		T143	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T9	1		T13	1		T132	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T10	1		T45	8		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T134	5		T45	8		T26	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	12		T5	6		T12	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T14	9		T77	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	2		T10	1		T41	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1			T11	14		T12	10		T161	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	1		T145	11		T80	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T31	2		T174	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T38	2		T274	1		T228	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T2	1		T7	27		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T3	9		T9	1		T44	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T5	8		T134	13		T143	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T297	1		T192	6		T279	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16188	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T230	14		T266	9		T281	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T154	10		T15	1		T164	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T43	10		T144	5		T187	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	2		T41	6		T219	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T138	11		T219	9		T177	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T145	9		T164	15		T229	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	8		T143	14		T163	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	9		T132	14		T138	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T10	11		T45	7		T138	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T134	6		T45	7		T26	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	10		T5	7		T12	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	3		T14	6		T77	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	10		T41	2		T43	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T161	26		T246	7		T188	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	13		T145	17		T80	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T174	4		T137	6		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T38	1		T274	16		T228	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	3		T7	17		T51	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T51	11		T143	11		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T134	13		T143	3		T171	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T192	4		T279	11		T298	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	2		T132	11		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T230	11		T266	16		T281	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	8		T7	15		T134	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T51	18		T145	16		T150	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T218	12		T253	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T230	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	1		T132	15		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T43	10		T144	1		T262	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	3		T41	5		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T135	8		T138	1		T219	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T141	15		T221	1		T155	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T152	30		T312	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T9	1		T13	1		T141	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	9		T10	1		T143	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T134	5		T45	8		T25	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	12		T5	6		T31	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T77	10		T150	5		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	2		T12	13		T82	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	1		T14	9		T246	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	2		T41	5		T43	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1601	1			T11	14		T12	10		T161	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T145	11		T80	1		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T7	12		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T3	9		T9	1		T44	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	7		T134	13		T143	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T51	11		T145	13		T150	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T230	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T132	11		T15	1		T164	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T43	10		T144	5		T262	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	2		T41	6		T154	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T138	11		T219	9		T187	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T137	9		T164	15		T278	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T163	2		T281	2		T198	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	9		T132	14		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T5	8		T10	11		T143	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T134	6		T45	7		T26	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T2	10		T5	7		T31	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T77	3		T150	3		T35	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	10		T190	2		T149	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	3		T14	6		T246	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	23		T41	2		T43	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	943	1			T161	26		T188	20		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T145	17		T80	13		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	3		T7	10		T51	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T143	11		T227	12		T187	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T9	1		T154	11		T15	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T43	11		T144	6		T187	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	3		T41	7		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T152	2		T135	1		T138	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T141	2		T145	10		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	9		T12	1		T143	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T9	1		T13	10		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T10	12		T45	8		T138	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T134	7		T45	8		T26	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	11		T5	8		T12	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	4		T14	11		T77	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	2		T10	11		T41	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T11	1		T12	1		T161	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T10	14		T145	18		T80	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T31	2		T174	5		T137	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T38	2		T274	17		T228	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T2	4		T7	19		T51	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	1		T9	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T5	1		T134	14		T143	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T297	1		T192	5		T279	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16310	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T230	15		T266	17		T281	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	1		T80	1		T139	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T43	9		T187	2		T293	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	2		T41	4		T155	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T152	28		T135	7		T219	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T141	16		T145	9		T155	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	8		T143	16		T296	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T132	5		T25	4		T77	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T45	7		T228	2		T39	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T134	4		T45	7		T26	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	11		T5	5		T12	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T14	4		T77	9		T216	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T41	4		T43	2		T82	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T11	13		T12	9		T27	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T145	10		T164	3		T16	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T231	1		T18	4		T257	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T38	1		T228	6		T149	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	25		T135	6		T236	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	8		T44	15		T51	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T5	7		T134	12		T143	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T192	5		T279	6		T298	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T132	14		T218	11		T228	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T230	10		T266	8		T281	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T7	8		T134	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T51	12		T145	14		T150	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T218	1		T253	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T230	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	1		T132	12		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T43	11		T144	6		T262	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	3		T41	7		T154	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T135	1		T138	12		T219	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T141	1		T221	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	1		T152	2		T312	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	1		T13	10		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	9		T10	12		T143	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T134	7		T45	8		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	11		T5	8		T31	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T77	4		T150	4		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	2		T12	11		T82	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	4		T14	11		T246	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	25		T41	3		T43	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T11	1		T12	1		T161	29
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T145	18		T80	14		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	4		T7	11		T51	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T3	1		T9	1		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	7		T7	14		T134	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T51	17		T145	15		T150	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T218	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T230	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T132	14		T15	1		T80	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T43	9		T293	7		T266	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	2		T41	4		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T135	7		T219	9		T187	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T141	14		T155	8		T164	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T152	28		T281	10		T198	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T141	2		T132	5		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	8		T143	16		T45	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T134	4		T45	7		T25	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	11		T5	5		T31	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T77	9		T150	4		T216	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	12		T82	13		T190	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	4		T246	7		T100	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T41	4		T43	2		T164	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T11	13		T12	9		T27	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T145	10		T38	1		T228	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	11		T135	6		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T3	8		T44	15		T143	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20