Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22195

1

T1

20

T3

9

T5

8

auto[ADC_CTRL_FILTER_COND_OUT]

3490

1

T2

31

T5

30

T7

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19610

1

T1

20

T2

4

T3

9

auto[1]

6075

1

T2

27

T5

13

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	60	1			T9	1		T51	29		T321	1
values[0]	41	1			T309	13		T225	1		T276	13
values[1]	918	1			T5	8		T143	13		T152	16
values[2]	750	1			T2	4		T12	23		T13	4
values[3]	1001	1			T7	22		T9	1		T10	14
values[4]	2889	1			T2	22		T6	2		T11	14
values[5]	570	1			T5	17		T7	22		T10	12
values[6]	513	1			T9	1		T43	20		T141	3
values[7]	779	1			T2	5		T3	9		T5	13
values[8]	583	1			T12	1		T45	15		T135	11
values[9]	1327	1			T10	11		T12	10		T41	7
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	930	1			T5	8		T143	13		T152	16
values[1]	1033	1			T2	4		T9	1		T10	14
values[2]	867	1			T7	22		T134	26		T152	14
values[3]	2879	1			T2	22		T5	17		T6	2
values[4]	480	1			T7	22		T31	7		T164	2
values[5]	695	1			T9	1		T13	10		T43	20
values[6]	578	1			T2	5		T3	9		T5	13
values[7]	651	1			T144	6		T45	15		T135	11
values[8]	1086	1			T9	1		T10	11		T12	10
values[9]	190	1			T41	7		T51	29		T186	1
minimum	16296	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T5	8		T143	10		T152	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T138	1		T14	9		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T9	1		T41	5		T143	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T2	1		T10	1		T12	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T7	15		T134	13		T152	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T26	8		T75	13		T80	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T6	2		T10	1		T11	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	12		T5	9		T45	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T164	1		T39	13		T239	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	12		T31	4		T228	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T13	1		T43	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T141	3		T134	5		T15	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	9		T132	6		T155	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	3		T5	6		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T144	1		T135	11		T25	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T45	8		T137	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T9	1		T12	10		T43	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T10	1		T221	1		T155	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T41	5		T51	18		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T177	7		T108	1		T171	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16118	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T322	8		T317	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T143	3		T77	2		T80	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T138	11		T14	6		T80	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T41	6		T143	11		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	3		T10	13		T12	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	7		T134	13		T145	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T26	7		T40	3		T106	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	901	1			T10	11		T161	26		T26	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	10		T5	8		T45	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T164	1		T39	5		T239	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T7	10		T31	3		T228	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	9		T43	10		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T134	6		T15	1		T236	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T132	14		T174	4		T100	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	2		T5	7		T138	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T144	5		T77	3		T219	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T45	7		T137	6		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T43	6		T77	19		T106	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T10	10		T246	7		T37	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T41	2		T51	11		T170	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T177	5		T171	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	2		T14	1		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T322	11		T317	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T9	1		T51	18		T321	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T260	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T309	1		T195	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T225	1		T276	13		T318	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T5	8		T143	10		T152	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T138	1		T14	9		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T41	5		T143	16		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T12	13		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T7	15		T9	1		T152	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T10	1		T143	17		T132	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T6	2		T11	14		T141	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	12		T45	8		T26	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T10	1		T164	1		T39	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	9		T7	12		T227	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T43	10		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T141	3		T134	5		T31	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	9		T13	1		T132	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	3		T5	6		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T135	11		T31	2		T77	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	1		T45	8		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T12	10		T41	5		T43	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T10	1		T221	1		T155	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T51	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T260	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T309	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T318	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T143	3		T80	17		T227	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T138	11		T14	6		T80	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T41	6		T143	11		T154	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	3		T12	10		T13	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	7		T145	17		T255	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T10	13		T143	14		T132	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T134	13		T161	26		T26	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T2	10		T45	7		T26	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T10	11		T164	1		T39	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	8		T7	10		T227	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T43	10		T51	1		T145	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T134	6		T31	3		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	9		T132	14		T174	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	2		T5	7		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T77	3		T219	9		T187	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T45	7		T137	6		T150	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T41	2		T43	6		T144	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T10	10		T246	7		T37	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T5	1		T143	4		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T138	12		T14	11		T80	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T9	1		T41	7		T143	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T2	4		T10	14		T12	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T7	8		T134	14		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T26	8		T75	1		T80	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T6	2		T10	12		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	11		T5	9		T45	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T164	2		T39	13		T239	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	11		T31	5		T228	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	1		T13	10		T43	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T141	1		T134	7		T15	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	1		T132	15		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	3		T5	8		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T144	6		T135	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T45	8		T137	7		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T9	1		T12	1		T43	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T10	11		T221	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T41	3		T51	12		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T177	6		T108	1		T171	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16261	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T322	16		T317	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	7		T143	9		T152	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	4		T187	11		T148	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T41	4		T143	15		T135	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	12		T143	16		T132	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	14		T134	12		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T26	7		T75	12		T80	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T11	13		T141	14		T27	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	11		T5	8		T45	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T39	5		T239	9		T191	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T7	11		T31	2		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T43	9		T145	24		T319	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T141	2		T134	4		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	8		T132	5		T155	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	2		T5	5		T155	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T135	10		T25	4		T77	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T45	7		T228	10		T235	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	9		T43	2		T44	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T155	21		T246	7		T37	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T41	4		T51	17		T170	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T177	6		T171	9		T172	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T171	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T322	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T9	1		T51	12		T321	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T260	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T309	13		T195	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T225	1		T276	1		T318	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T5	1		T143	4		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T138	12		T14	11		T80	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T41	7		T143	12		T154	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	4		T12	11		T13	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T7	8		T9	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T10	14		T143	15		T132	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T6	2		T11	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T2	11		T45	8		T26	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	12		T164	2		T39	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	9		T7	11		T227	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	1		T43	11		T51	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T141	1		T134	7		T31	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	1		T13	10		T132	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	3		T5	8		T138	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T135	1		T31	2		T77	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	1		T45	8		T137	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T12	1		T41	3		T43	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T10	11		T221	1		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T51	17		T287	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T260	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T276	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	7		T143	9		T152	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	4		T187	11		T148	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T41	4		T143	15		T77	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	12		T135	7		T187	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	14		T152	13		T145	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T143	16		T132	14		T75	32
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T11	13		T141	14		T134	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T2	11		T45	7		T26	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T39	5		T191	3		T232	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	8		T7	11		T227	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T43	9		T145	24		T242	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T141	2		T134	4		T31	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	8		T132	5		T155	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	2		T5	5		T155	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T135	10		T77	9		T139	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T45	7		T235	18		T150	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T12	9		T41	4		T43	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T155	21		T246	7		T37	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20