Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21820

1

T1

20

T2

31

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3865

1

T9

2

T10

12

T12

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19560

1

T1

20

T3

9

T5

8

auto[1]

6125

1

T2

31

T5

30

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	264	1			T143	44		T45	15		T25	5
values[0]	45	1			T249	9		T91	27		T251	8
values[1]	766	1			T5	8		T10	14		T43	9
values[2]	729	1			T9	1		T41	7		T141	3
values[3]	662	1			T5	17		T13	10		T43	20
values[4]	845	1			T2	4		T3	9		T5	13
values[5]	701	1			T2	5		T7	22		T45	1
values[6]	539	1			T7	22		T145	19		T136	1
values[7]	966	1			T10	12		T12	1		T138	12
values[8]	840	1			T2	22		T10	11		T134	11
values[9]	3074	1			T6	2		T9	1		T11	14
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	820	1			T5	8		T9	1		T10	14
values[1]	655	1			T43	20		T141	3		T132	26
values[2]	745	1			T3	9		T5	17		T13	10
values[3]	725	1			T2	4		T5	13		T9	1
values[4]	728	1			T2	5		T7	22		T145	29
values[5]	638	1			T7	22		T10	12		T12	1
values[6]	2969	1			T2	22		T11	14		T144	6
values[7]	846	1			T9	1		T10	11		T134	11
values[8]	928	1			T6	2		T12	23		T13	4
values[9]	151	1			T45	15		T190	15		T244	10
minimum	16480	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	8		T10	1		T41	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	1		T14	9		T82	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T152	14		T145	11		T80	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T43	10		T141	3		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	9		T5	9		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T134	13		T132	6		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	1		T5	6		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T141	15		T45	1		T312	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	3		T7	12		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T145	16		T135	8		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	15		T12	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	1		T145	10		T37	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T2	12		T11	14		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T152	16		T138	1		T155	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T10	1		T134	5		T135	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T9	1		T135	7		T155	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	2		T13	1		T41	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T12	13		T44	16		T143	33
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T45	8		T244	1		T235	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T190	13		T34	1		T293	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16149	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T273	1		T19	5		T323	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	13		T41	2		T43	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	6		T16	6		T239	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T145	17		T228	2		T192	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T43	10		T132	11		T80	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	8		T13	9		T26	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T134	13		T132	14		T138	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	3		T5	7		T45	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T187	1		T149	13		T255	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	2		T7	10		T138	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T145	13		T154	10		T187	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	7		T106	7		T256	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	11		T145	9		T37	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T2	10		T144	5		T161	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T138	11		T219	16		T164	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	10		T134	6		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T174	4		T80	2		T240	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	3		T41	6		T51	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	10		T143	25		T77	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T45	7		T244	9		T258	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T190	2		T34	8		T293	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	2		T14	1		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T19	2		T323	11		T180	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T143	10		T45	8		T25	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T143	17		T155	9		T77	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T249	9		T251	1		T261	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T91	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	8		T10	1		T43	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	9		T82	14		T100	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T41	5		T152	14		T145	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	1		T141	3		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	9		T13	1		T227	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	10		T134	13		T132	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T2	1		T3	9		T5	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T141	15		T138	1		T77	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	3		T7	12		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T45	1		T145	16		T135	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	15		T136	1		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T145	10		T228	3		T235	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	1		T219	10		T164	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T10	1		T138	1		T219	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	12		T10	1		T134	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T152	16		T135	7		T155	36
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1641	1			T6	2		T11	14		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T9	1		T12	13		T44	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T143	3		T45	7		T244	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T143	14		T77	2		T149	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T251	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T91	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	13		T43	6		T51	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	6		T239	7		T230	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T41	2		T145	17		T228	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T132	11		T80	13		T16	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	8		T13	9		T227	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	10		T134	13		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	3		T5	7		T45	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T138	8		T77	3		T187	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T7	10		T138	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T145	13		T154	10		T187	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	7		T36	5		T106	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T145	9		T228	3		T150	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T219	9		T164	11		T40	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T10	11		T138	11		T219	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	10		T10	10		T134	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T174	4		T80	2		T147	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T13	3		T41	6		T51	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	10		T143	11		T190	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	1		T10	14		T41	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	1		T14	11		T82	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T152	1		T145	18		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T43	11		T141	1		T132	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	1		T5	9		T13	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T134	14		T132	15		T138	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	4		T5	8		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T141	1		T45	1		T312	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	3		T7	11		T138	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T145	14		T135	1		T154	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	8		T12	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	12		T145	10		T37	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T2	11		T11	1		T144	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T152	1		T138	12		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T10	11		T134	7		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	1		T135	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T6	2		T13	4		T41	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T12	11		T44	1		T143	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T45	8		T244	10		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T190	3		T34	9		T293	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16314	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T273	1		T19	5		T323	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	7		T41	4		T43	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	4		T82	13		T16	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T152	13		T145	10		T80	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T43	9		T141	2		T132	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	8		T5	8		T227	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T134	12		T132	5		T77	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	5		T12	9		T45	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T141	14		T149	13		T191	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	2		T7	11		T80	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T145	15		T135	7		T187	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	14		T106	2		T263	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T145	9		T37	7		T235	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T2	11		T11	13		T27	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T152	15		T155	13		T219	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T134	4		T135	10		T227	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T135	6		T155	21		T240	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T41	4		T51	17		T143	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	12		T44	15		T143	31
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T45	7		T235	18		T258	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T190	12		T293	5		T324	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T218	11		T164	11		T325	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T19	2		T323	14		T315	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T143	4		T45	8		T25	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T143	15		T155	1		T77	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T249	1		T251	8		T261	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T91	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	1		T10	14		T43	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	11		T82	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T41	3		T152	1		T145	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	1		T141	1		T132	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	9		T13	10		T227	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T43	11		T134	14		T132	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	4		T3	1		T5	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T141	1		T138	9		T77	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	3		T7	11		T138	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T45	1		T145	14		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	8		T136	1		T36	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T145	10		T228	4		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T219	10		T164	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T10	12		T138	12		T219	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T2	11		T10	11		T134	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T152	1		T135	1		T155	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T6	2		T11	1		T13	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	1		T12	11		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T143	9		T45	7		T25	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T143	16		T155	8		T77	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T249	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T91	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T5	7		T43	2		T218	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	4		T82	13		T100	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T41	4		T152	13		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T141	2		T132	14		T82	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	8		T227	4		T150	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T43	9		T134	12		T132	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	8		T5	5		T12	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T141	14		T77	9		T39	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	2		T7	11		T80	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T145	15		T135	7		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	14		T106	2		T263	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T145	9		T228	2		T235	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T219	9		T164	3		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T219	15		T37	7		T265	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	11		T134	4		T135	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T152	15		T135	6		T155	34
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T11	13		T41	4		T51	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	12		T44	15		T143	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20