Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22024

1

T1

20

T2

31

T5

38

auto[ADC_CTRL_FILTER_COND_OUT]

3661

1

T3

9

T7

44

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19391

1

T1

20

T2

27

T3

9

auto[1]

6294

1

T2

4

T7

22

T9

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	192	1			T141	15		T132	26		T38	3
values[0]	71	1			T145	28		T239	16		T298	26
values[1]	763	1			T51	29		T143	13		T14	15
values[2]	934	1			T5	17		T12	10		T44	16
values[3]	609	1			T10	12		T41	11		T45	30
values[4]	801	1			T2	4		T12	23		T51	2
values[5]	2926	1			T3	9		T11	14		T141	3
values[6]	750	1			T2	22		T10	11		T25	5
values[7]	848	1			T2	5		T7	22		T9	3
values[8]	656	1			T5	8		T7	22		T152	16
values[9]	881	1			T5	13		T6	2		T10	14
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	761	1			T44	16		T143	44		T145	28
values[1]	806	1			T5	17		T12	10		T41	11
values[2]	625	1			T10	12		T45	15		T135	8
values[3]	2942	1			T2	4		T11	14		T12	23
values[4]	828	1			T3	9		T10	11		T45	1
values[5]	846	1			T2	22		T25	5		T15	5
values[6]	741	1			T2	5		T7	44		T9	3
values[7]	608	1			T5	21		T13	14		T152	16
values[8]	870	1			T6	2		T10	14		T12	1
values[9]	104	1			T132	26		T279	13		T324	2
minimum	16554	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T143	17		T77	20		T80	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T44	16		T143	10		T145	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T5	9		T12	10		T45	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T41	5		T145	16		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T45	8		T135	8		T26	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	1		T155	22		T218	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T2	1		T11	14		T12	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T134	13		T143	16		T135	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	1		T45	1		T145	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	9		T26	1		T75	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	12		T25	5		T15	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T219	16		T220	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	3		T9	2		T41	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	27		T9	1		T155	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	14		T13	1		T152	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	1		T163	1		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T6	2		T12	1		T43	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	1		T221	1		T138	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T223	1		T326	5		T327	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T132	15		T279	11		T324	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16228	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T31	4		T77	12		T240	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T143	14		T77	19		T80	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T143	3		T145	17		T14	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T5	8		T45	7		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T41	6		T145	13		T138	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T45	7		T26	7		T77	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	11		T149	13		T179	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	887	1			T2	3		T12	10		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T134	13		T143	11		T80	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	10		T145	9		T137	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T26	11		T177	5		T178	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	10		T15	1		T35	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T219	16		T147	8		T148	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	2		T41	2		T43	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	17		T187	10		T100	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T5	7		T13	3		T190	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	9		T163	2		T187	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T43	10		T132	14		T187	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T10	13		T138	15		T219	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T223	2		T327	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T132	11		T279	2		T324	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	2		T51	11		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T31	3		T77	2		T240	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T141	15		T196	18		T328	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T132	15		T38	2		T148	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T239	12		T298	12		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T145	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T51	18		T174	1		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T143	10		T14	9		T31	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T5	9		T12	10		T143	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T44	16		T145	16		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T45	16		T26	8		T77	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	1		T41	5		T155	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	1		T12	13		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T135	11		T80	1		T227	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T11	14		T141	3		T134	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	9		T134	13		T143	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	12		T10	1		T25	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T26	1		T219	16		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T2	3		T9	2		T41	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	12		T9	1		T155	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	8		T152	16		T155	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	15		T163	1		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	6		T6	2		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	1		T13	1		T221	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T329	14		T222	11		T223	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T132	11		T38	1		T148	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T239	4		T298	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T145	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T51	11		T174	4		T80	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T143	3		T14	6		T31	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T5	8		T143	14		T154	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T145	13		T138	8		T236	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T45	14		T26	7		T77	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	11		T41	6		T149	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	3		T12	10		T51	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T80	2		T227	10		T39	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	888	1			T134	6		T145	9		T161	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T134	13		T143	11		T178	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	10		T10	10		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T26	11		T219	16		T147	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	2		T41	2		T43	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	10		T187	10		T100	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T190	2		T228	2		T293	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	7		T163	2		T230	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	7		T13	3		T43	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T10	13		T13	9		T138	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T143	15		T77	20		T80	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T44	1		T143	4		T145	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T5	9		T12	1		T45	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T41	7		T145	14		T138	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T45	8		T135	1		T26	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	12		T155	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T2	4		T11	1		T12	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T134	14		T143	12		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T10	11		T45	1		T145	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	1		T26	12		T75	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	11		T25	1		T15	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T219	17		T220	1		T147	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	3		T9	2		T41	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	19		T9	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	9		T13	4		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	10		T163	3		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	2		T12	1		T43	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T10	14		T221	1		T138	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T223	3		T326	1		T327	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T132	12		T279	3		T324	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16364	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T31	5		T77	3		T240	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T143	16		T77	19		T40	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T44	15		T143	9		T145	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	8		T12	9		T45	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T41	4		T145	15		T150	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T45	7		T135	7		T26	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T155	21		T218	11		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T11	13		T12	12		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T134	12		T143	15		T135	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T145	9		T82	13		T164	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	8		T75	12		T177	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	11		T25	4		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T219	15		T148	8		T255	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	2		T41	4		T43	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	25		T155	13		T187	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	12		T152	15		T139	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T187	2		T231	1		T232	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T43	9		T141	14		T132	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T219	9		T38	1		T148	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T326	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T132	14		T279	10		T217	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T51	17		T239	20		T168	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T31	2		T77	11		T240	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T141	1		T196	1		T328	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T132	12		T38	2		T148	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T239	5		T298	15		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T145	18		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T51	12		T174	5		T80	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T143	4		T14	11		T31	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T5	9		T12	1		T143	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T44	1		T145	14		T138	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T45	16		T26	8		T77	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	12		T41	7		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	4		T12	11		T51	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T135	1		T80	3		T227	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T11	1		T141	1		T134	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T3	1		T134	14		T143	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T2	11		T10	11		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T26	12		T219	17		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T2	3		T9	2		T41	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	11		T9	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T5	1		T152	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	8		T163	3		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	8		T6	2		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T10	14		T13	10		T221	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T141	14		T196	17		T328	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T132	14		T38	1		T148	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T239	11		T298	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T145	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T51	17		T40	1		T239	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T143	9		T14	4		T31	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	8		T12	9		T143	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T44	15		T145	15		T236	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T45	14		T26	7		T77	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T41	4		T155	21		T218	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	12		T152	13		T135	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T135	10		T227	4		T39	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T11	13		T141	2		T134	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	8		T134	12		T143	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	11		T25	4		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T219	15		T148	8		T255	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	2		T41	4		T43	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	11		T155	13		T187	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	7		T152	15		T155	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	14		T230	10		T231	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	5		T43	9		T132	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T219	9		T187	2		T20	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20