Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19857

1

T1

20

T2

4

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

5828

1

T2

27

T5

25

T7

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19455

1

T1

20

T3

9

T5

17

auto[1]

6230

1

T2

31

T5

21

T7

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	200	1			T141	3		T132	20		T100	2
values[0]	29	1			T263	9		T193	16		T302	1
values[1]	902	1			T2	4		T41	11		T145	28
values[2]	898	1			T12	1		T13	4		T51	29
values[3]	655	1			T3	9		T5	8		T7	22
values[4]	956	1			T7	22		T9	1		T10	14
values[5]	798	1			T5	13		T12	23		T13	10
values[6]	688	1			T51	2		T143	13		T45	16
values[7]	559	1			T2	27		T9	2		T12	10
values[8]	770	1			T5	17		T43	9		T134	26
values[9]	2976	1			T6	2		T10	11		T11	14
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	817	1			T2	4		T41	11		T152	14
values[1]	3042	1			T7	22		T10	12		T11	14
values[2]	678	1			T3	9		T5	8		T10	14
values[3]	870	1			T7	22		T9	1		T12	23
values[4]	824	1			T5	13		T13	10		T44	16
values[5]	657	1			T9	1		T12	10		T43	20
values[6]	630	1			T2	27		T9	1		T134	26
values[7]	723	1			T5	17		T43	9		T141	15
values[8]	755	1			T10	11		T141	3		T134	11
values[9]	163	1			T6	2		T132	20		T239	16
minimum	16526	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T2	1		T14	9		T77	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T41	5		T152	14		T155	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	1		T13	1		T227	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1679	1			T7	15		T10	1		T11	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	9		T10	1		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	8		T143	16		T75	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T45	8		T154	1		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T7	12		T9	1		T12	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	6		T44	16		T132	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	1		T143	17		T155	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T43	10		T45	9		T31	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	1		T12	10		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T144	1		T138	2		T39	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	15		T9	1		T134	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T43	3		T141	15		T145	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	9		T221	1		T80	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T10	1		T134	5		T135	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T141	3		T26	1		T297	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T6	2		T132	6		T239	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T108	1		T305	15		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16188	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T145	11		T330	1		T193	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	3		T14	6		T77	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T41	6		T236	6		T37	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	3		T227	2		T228	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	977	1			T7	7		T10	11		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	13		T145	9		T77	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T143	11		T16	6		T293	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T45	7		T154	10		T36	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	10		T12	10		T41	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	7		T132	11		T80	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	9		T143	14		T164	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T43	10		T45	7		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T51	1		T143	3		T150	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T144	5		T138	12		T39	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T2	12		T134	13		T38	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T43	6		T145	13		T138	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	8		T80	15		T149	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	10		T134	6		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T26	11		T137	6		T164	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T132	14		T239	4		T247	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T251	2		T331	2		T306	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	2		T14	1		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T145	17		T193	10		T167	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T132	6		T247	1		T332	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T141	3		T100	1		T165	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T263	3		T90	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T193	6		T302	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	1		T77	20		T82	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T41	5		T145	11		T155	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	1		T13	1		T14	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T51	18		T152	14		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	9		T145	10		T135	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	8		T7	15		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	1		T45	8		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T7	12		T9	1		T41	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	6		T44	16		T132	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	13		T13	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T45	9		T31	6		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T51	1		T143	10		T135	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	10		T144	1		T138	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	15		T9	2		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T43	3		T145	16		T75	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	9		T134	13		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T6	2		T10	1		T141	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1571	1			T11	14		T161	3		T24	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T132	14		T247	1		T332	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T100	1		T231	4		T251	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T263	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T193	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	3		T77	19		T137	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T41	6		T145	17		T236	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	3		T14	6		T227	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T51	11		T147	8		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T145	9		T304	1		T178	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	7		T10	11		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T10	13		T45	7		T154	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	10		T41	2		T190	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	7		T132	11		T80	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	10		T13	9		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T45	7		T31	3		T80	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T51	1		T143	3		T150	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T43	10		T144	5		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	12		T38	1		T274	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T43	6		T145	13		T246	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	8		T134	13		T80	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	10		T134	6		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	890	1			T161	26		T26	11		T137	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T2	4		T14	11		T77	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T41	7		T152	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	1		T13	4		T227	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1299	1			T7	8		T10	12		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T10	14		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	1		T143	12		T75	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T45	8		T154	11		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T7	11		T9	1		T12	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	8		T44	1		T132	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	10		T143	15		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T43	11		T45	9		T31	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	1		T12	1		T51	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T144	6		T138	14		T39	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	14		T9	1		T134	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T43	7		T141	1		T145	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	9		T221	1		T80	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T10	11		T134	7		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T141	1		T26	12		T297	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T6	2		T132	15		T239	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T108	1		T305	1		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16356	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T145	18		T330	1		T193	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	4		T77	19		T82	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T41	4		T152	13		T155	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T227	8		T228	6		T242	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1357	1			T7	14		T11	13		T51	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T3	8		T145	9		T135	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	7		T143	15		T75	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T45	7		T196	13		T166	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T7	11		T12	12		T41	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	5		T44	15		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T143	16		T155	21		T164	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T43	9		T45	7		T31	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T12	9		T143	9		T135	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T39	5		T150	11		T296	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	13		T134	12		T152	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T43	2		T141	14		T145	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	8		T80	15		T139	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T134	4		T135	7		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T141	2		T187	11		T235	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T132	5		T239	11		T216	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T305	14		T306	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T100	3		T106	2		T263	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T145	10		T193	5		T294	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T132	15		T247	2		T332	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T141	1		T100	2		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T263	8		T90	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T193	11		T302	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T2	4		T77	20		T82	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T41	7		T145	18		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T12	1		T13	4		T14	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T51	12		T152	1		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	1		T145	10		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	1		T7	8		T10	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T10	14		T45	8		T154	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	11		T9	1		T41	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	8		T44	1		T132	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	11		T13	10		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T45	9		T31	7		T80	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	2		T143	4		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T43	11		T144	6		T138	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	14		T9	2		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T43	7		T145	14		T75	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	9		T134	14		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T6	2		T10	11		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1208	1			T11	1		T161	29		T24	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T132	5		T91	14		T333	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T141	2		T165	8		T231	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T263	1		T90	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T193	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T77	19		T82	2		T100	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T41	4		T145	10		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	4		T227	8		T228	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T51	17		T152	13		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T3	8		T145	9		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	7		T7	14		T143	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T45	7		T77	9		T219	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T7	11		T41	4		T75	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	5		T44	15		T132	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	12		T143	16		T155	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T45	7		T31	2		T148	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T143	9		T135	6		T150	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T43	9		T227	4		T39	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T2	13		T12	9		T152	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T43	2		T145	15		T75	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	8		T134	12		T80	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T141	14		T134	4		T135	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1253	1			T11	13		T27	9		T76	31

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20