Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T132	15		T152	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T141	1		T134	14		T143	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T221	1		T138	5		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	1		T143	15		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T45	8		T14	11		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T2	11		T7	11		T13	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T5	8		T6	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T41	7		T164	12		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T12	11		T144	6		T145	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	3		T10	12		T174	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	9		T134	7		T227	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	1		T145	10		T77	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	8		T9	1		T43	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T9	1		T10	11		T13	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T9	1		T10	14		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	4		T80	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	1		T15	4		T80	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T41	3		T141	1		T51	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T237	1		T238	8		T91	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T45	1		T26	12		T236	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T180	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T132	5		T152	13		T135	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T141	2		T134	12		T143	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T155	13		T148	8		T150	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T143	16		T152	15		T75	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T45	7		T14	4		T155	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	11		T7	11		T143	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T5	5		T11	13		T12	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T41	4		T164	3		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T12	12		T145	10		T135	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	2		T16	5		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	8		T134	4		T227	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	8		T145	9		T77	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	14		T43	11		T135	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T106	2		T235	16		T35	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T190	12		T240	1		T245	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T80	1		T139	15		T218	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	7		T15	1		T227	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T41	4		T141	14		T132	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T237	13		T238	6		T91	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T236	7		T77	19		T246	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T147	9		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T233	1		T234	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T187	2		T38	7		T235	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T132	15		T152	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T141	1		T134	14		T143	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T221	1		T138	5		T80	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	1		T143	15		T138	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	11		T155	2		T137	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	11		T7	11		T13	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	8		T6	2		T51	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T186	1		T38	2		T242	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T11	1		T12	12		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T10	12		T174	5		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T43	7		T134	7		T145	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	3		T3	1		T77	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	9		T9	2		T43	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	1		T10	11		T13	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	8		T10	14		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T141	1		T80	1		T219	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T5	1		T15	4		T80	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T2	4		T41	3		T51	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T235	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T132	5		T152	13		T135	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T141	2		T134	12		T143	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T82	2		T150	4		T247	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T143	16		T75	12		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	4		T155	21		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	11		T7	11		T41	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	5		T51	17		T45	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T38	1		T242	3		T229	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T11	13		T12	21		T44	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T164	3		T149	11		T248	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T43	2		T134	4		T145	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	2		T3	8		T77	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	8		T43	9		T135	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T145	9		T106	2		T235	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T7	14		T190	12		T164	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T141	14		T80	1		T219	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	7		T15	1		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T41	4		T132	14		T45	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20