Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21707

1

T1

20

T2

31

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3978

1

T9

2

T10

12

T12

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19583

1

T1

20

T3

9

T5

21

auto[1]

6102

1

T2

31

T5

17

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T178	15		T56	15		-	-
values[0]	19	1			T249	9		T250	1		T251	8
values[1]	802	1			T5	8		T10	14		T43	9
values[2]	624	1			T9	1		T41	7		T141	3
values[3]	783	1			T2	4		T5	17		T9	1
values[4]	825	1			T2	5		T3	9		T5	13
values[5]	694	1			T7	22		T12	10		T45	1
values[6]	548	1			T7	22		T12	1		T145	19
values[7]	928	1			T10	12		T219	51		T156	1
values[8]	871	1			T2	22		T10	11		T134	11
values[9]	3307	1			T6	2		T9	1		T11	14
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	990	1			T5	8		T9	1		T10	14
values[1]	710	1			T41	7		T43	20		T134	26
values[2]	623	1			T3	9		T5	17		T13	10
values[3]	775	1			T2	4		T5	13		T9	1
values[4]	756	1			T2	5		T7	22		T145	29
values[5]	657	1			T7	22		T10	12		T12	1
values[6]	2934	1			T2	22		T11	14		T144	6
values[7]	832	1			T9	1		T10	11		T134	11
values[8]	889	1			T6	2		T13	4		T41	11
values[9]	208	1			T12	23		T155	9		T190	15
minimum	16311	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	8		T10	1		T43	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T9	1		T141	3		T14	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T41	5		T134	13		T152	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	10		T132	15		T75	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	9		T5	9		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T132	6		T138	1		T77	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T2	1		T5	6		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T141	15		T45	1		T187	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	3		T7	12		T80	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T145	16		T135	8		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	15		T136	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	1		T12	1		T145	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T2	12		T11	14		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T152	16		T138	1		T155	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	1		T134	5		T135	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T9	1		T135	7		T155	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T6	2		T13	1		T41	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T44	16		T143	33		T75	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T235	19		T252	1		T253	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T12	13		T155	9		T190	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16112	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T218	12		T91	15		T254	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T10	13		T43	6		T51	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	6		T16	6		T239	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T41	2		T134	13		T145	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T43	10		T132	11		T80	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	8		T13	9		T26	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T132	14		T138	8		T77	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	3		T5	7		T45	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T187	1		T149	13		T255	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	2		T7	10		T80	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T145	13		T138	4		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	7		T106	7		T256	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	11		T145	9		T164	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	915	1			T2	10		T144	5		T161	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	11		T80	2		T219	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	10		T134	6		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T174	4		T240	4		T257	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	3		T41	6		T51	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T143	25		T77	2		T187	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T258	3		T259	9		T260	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T12	10		T190	2		T242	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	2		T14	1		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T91	12		T254	1		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T178	6		T56	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T249	9		T251	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T250	1		T261	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	8		T10	1		T43	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T14	9		T82	14		T218	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T41	5		T152	14		T145	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	1		T141	3		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	1		T5	9		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T43	10		T132	6		T75	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T2	3		T3	9		T5	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T141	15		T138	1		T77	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	12		T12	10		T80	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T45	1		T145	16		T135	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	15		T36	3		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T145	10		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T219	10		T164	4		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T10	1		T219	16		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	12		T10	1		T134	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T152	16		T135	7		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1706	1			T6	2		T11	14		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T9	1		T12	13		T44	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T178	9		T56	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T251	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	13		T43	6		T51	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	6		T239	7		T230	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T41	2		T145	17		T262	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T132	11		T80	13		T16	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	3		T5	8		T13	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T43	10		T132	14		T257	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	2		T5	7		T45	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T138	8		T77	3		T187	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	10		T80	15		T163	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T145	13		T138	4		T154	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	7		T36	5		T106	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T145	9		T228	3		T150	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T219	9		T164	11		T100	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T10	11		T219	16		T164	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	10		T10	10		T134	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T138	11		T174	4		T80	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T13	3		T41	6		T51	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	10		T143	25		T77	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T5	1		T10	14		T43	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T9	1		T141	1		T14	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T41	3		T134	14		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T43	11		T132	12		T75	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	1		T5	9		T13	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T132	15		T138	9		T77	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	4		T5	8		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T141	1		T45	1		T187	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	3		T7	11		T80	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T145	14		T135	1		T138	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	8		T136	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T10	12		T12	1		T145	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T2	11		T11	1		T144	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T152	1		T138	12		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	11		T134	7		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	1		T135	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	2		T13	4		T41	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T44	1		T143	27		T75	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T235	1		T252	1		T253	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T12	11		T155	1		T190	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16269	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T218	1		T91	13		T254	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	7		T43	2		T164	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T141	2		T14	4		T82	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T41	4		T134	12		T152	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	9		T132	14		T75	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	8		T5	8		T227	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T132	5		T77	9		T165	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	5		T12	9		T45	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T141	14		T149	13		T191	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	2		T7	11		T80	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T145	15		T135	7		T187	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T7	14		T106	2		T263	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T145	9		T37	7		T235	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T2	11		T11	13		T27	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T152	15		T155	13		T219	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T134	4		T135	10		T227	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T135	6		T155	21		T240	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T41	4		T51	17		T143	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T44	15		T143	31		T75	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T235	18		T258	9		T264	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T12	12		T155	8		T190	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T218	11		T91	14		T254	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T178	10		T56	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T249	1		T251	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T250	1		T261	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	1		T10	14		T43	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T14	11		T82	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T41	3		T152	1		T145	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	1		T141	1		T132	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	4		T5	9		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T43	11		T132	15		T75	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T2	3		T3	1		T5	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T141	1		T138	9		T77	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	11		T12	1		T80	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T45	1		T145	14		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	8		T36	8		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T145	10		T228	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T219	10		T164	12		T100	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T10	12		T219	17		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	11		T10	11		T134	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T152	1		T135	1		T138	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T6	2		T11	1		T13	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T9	1		T12	11		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T178	5		T56	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T249	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T5	7		T43	2		T164	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T14	4		T82	13		T218	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T41	4		T152	13		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T141	2		T132	14		T82	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	8		T134	12		T227	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T43	9		T132	5		T75	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	2		T3	8		T5	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T141	14		T77	9		T149	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	11		T12	9		T80	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T145	15		T135	7		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	14		T106	2		T263	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T145	9		T228	2		T235	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T219	9		T164	3		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T219	15		T37	7		T265	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	11		T134	4		T135	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T152	15		T135	6		T155	34
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T11	13		T41	4		T51	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T12	12		T44	15		T143	31

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20