Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22050

1

T1

20

T5

13

T6

130

auto[ADC_CTRL_FILTER_COND_OUT]

3635

1

T2

31

T3

9

T5

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19501

1

T1

20

T2

22

T5

13

auto[1]

6184

1

T2

9

T3

9

T5

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T9	1		T177	12		T254	10
values[0]	41	1			T12	1		T136	1		T266	25
values[1]	514	1			T2	5		T141	15		T134	26
values[2]	2991	1			T10	12		T11	14		T12	23
values[3]	503	1			T138	9		T174	5		T77	39
values[4]	773	1			T5	17		T10	14		T43	29
values[5]	724	1			T5	13		T10	11		T44	16
values[6]	933	1			T3	9		T5	8		T7	22
values[7]	846	1			T2	26		T9	1		T41	7
values[8]	788	1			T9	1		T134	11		T144	6
values[9]	1290	1			T6	2		T7	22		T12	10
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	815	1			T2	5		T12	1		T141	15
values[1]	2857	1			T10	12		T11	14		T12	23
values[2]	646	1			T143	27		T135	7		T138	9
values[3]	593	1			T5	30		T10	14		T43	29
values[4]	957	1			T10	11		T45	1		T31	2
values[5]	801	1			T2	22		T3	9		T5	8
values[6]	830	1			T2	4		T9	1		T41	7
values[7]	738	1			T9	1		T134	11		T144	6
values[8]	1044	1			T6	2		T7	22		T9	1
values[9]	150	1			T41	11		T145	29		T178	29
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T141	15		T152	16		T135	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	3		T12	1		T134	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1520	1			T11	14		T132	6		T161	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	1		T12	13		T141	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T143	16		T135	7		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T138	1		T16	10		T149	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	6		T43	3		T26	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	9		T10	1		T43	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T82	3		T265	13		T149	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	1		T45	1		T31	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T45	8		T80	1		T227	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	12		T3	9		T5	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T41	5		T51	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	1		T9	1		T51	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	1		T134	5		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T138	1		T80	16		T190	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T6	2		T7	12		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T12	10		T13	2		T155	31
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T41	5		T145	16		T267	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T178	16		T256	1		T268	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T138	4		T31	3		T77	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	2		T134	13		T80	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T132	14		T161	26		T164	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	11		T12	10		T26	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T143	11		T174	4		T36	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T138	8		T16	6		T149	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	7		T43	6		T26	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	8		T10	13		T43	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T265	14		T149	13		T239	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	10		T77	2		T219	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T45	7		T80	13		T227	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	10		T7	7		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T41	2		T51	1		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	3		T51	11		T143	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T134	6		T144	5		T137	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T138	11		T80	15		T190	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	10		T132	11		T45	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T13	12		T187	10		T228	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T41	6		T145	13		T267	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T178	13		T256	5		T268	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T9	1		T177	7		T215	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T254	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T266	9		T269	1		T270	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T12	1		T136	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T141	15		T152	16		T135	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T2	3		T134	13		T236	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T11	14		T132	6		T161	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	1		T12	13		T141	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T174	1		T187	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T138	1		T77	20		T16	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T43	3		T143	16		T135	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	9		T10	1		T43	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T5	6		T26	8		T139	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	1		T44	16		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T45	8		T227	9		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	9		T5	8		T7	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T41	5		T51	1		T143	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T2	13		T9	1		T51	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T9	1		T134	5		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T190	13		T164	4		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T6	2		T7	12		T41	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T12	10		T13	2		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T177	5		T215	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T254	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T266	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T169	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T138	4		T31	3		T77	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T2	2		T134	13		T236	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T132	14		T161	26		T164	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T10	11		T12	10		T26	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T174	4		T187	1		T147	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T138	8		T77	19		T16	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T43	6		T143	11		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	8		T10	13		T43	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	7		T26	7		T239	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	10		T77	2		T219	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T45	7		T227	2		T265	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	7		T37	12		T148	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T41	2		T51	1		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	13		T51	11		T143	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T134	6		T144	5		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T190	2		T164	11		T106	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T7	10		T41	6		T132	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T13	12		T138	11		T187	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T141	1		T152	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	3		T12	1		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T11	1		T132	15		T161	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	12		T12	11		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T143	12		T135	1		T174	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T138	9		T16	11		T149	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	8		T43	7		T26	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	9		T10	14		T43	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T82	1		T265	15		T149	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	11		T45	1		T31	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T45	8		T80	14		T227	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	11		T3	1		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T41	3		T51	2		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	4		T9	1		T51	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T134	7		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T138	12		T80	16		T190	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T6	2		T7	11		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T12	1		T13	14		T155	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T41	7		T145	14		T267	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T178	14		T256	6		T268	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T141	14		T152	15		T135	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	2		T134	12		T218	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T11	13		T132	5		T27	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	12		T141	2		T236	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T143	15		T135	6		T191	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T16	5		T149	11		T235	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T5	5		T43	2		T26	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	8		T43	9		T44	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T82	2		T265	12		T149	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T77	11		T219	15		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T45	7		T227	8		T231	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	11		T3	8		T5	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T41	4		T143	16		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T51	17		T143	9		T75	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T134	4		T155	13		T80	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T80	15		T190	12		T164	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	11		T132	14		T45	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	9		T155	29		T187	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T41	4		T145	15		T267	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T178	15		T268	9		T271	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T9	1		T177	6		T215	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T254	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T266	17		T269	1		T270	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T12	1		T136	1		T169	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T141	1		T152	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	3		T134	14		T236	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T11	1		T132	15		T161	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T10	12		T12	11		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T174	5		T187	2		T147	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T138	9		T77	20		T16	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T43	7		T143	12		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	9		T10	14		T43	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	8		T26	8		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	11		T44	1		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T45	8		T227	3		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	1		T5	1		T7	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T41	3		T51	2		T143	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	15		T9	1		T51	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	1		T134	7		T144	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T190	3		T164	12		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T6	2		T7	11		T41	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	433	1			T12	1		T13	14		T138	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T177	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T254	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T266	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T141	14		T152	15		T135	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T2	2		T134	12		T236	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T11	13		T132	5		T27	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	12		T141	2		T227	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T191	3		T272	12		T237	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T77	19		T16	5		T235	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T43	2		T143	15		T135	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	8		T43	9		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	5		T26	7		T139	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T44	15		T77	11		T219	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T45	7		T227	8		T265	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	8		T5	7		T7	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T41	4		T143	16		T75	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	11		T51	17		T143	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T134	4		T15	1		T155	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T190	12		T164	3		T106	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T7	11		T41	4		T132	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T12	9		T155	29		T187	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20