Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22067

1

T1

20

T5

13

T6

130

auto[ADC_CTRL_FILTER_COND_OUT]

3618

1

T2

31

T3

9

T5

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19464

1

T1

20

T2

22

T5

13

auto[1]

6221

1

T2

9

T3

9

T5

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	340	1			T6	2		T9	1		T13	10
values[0]	12	1			T136	1		T169	11		-	-
values[1]	514	1			T2	5		T12	1		T134	26
values[2]	3045	1			T10	12		T11	14		T12	23
values[3]	580	1			T143	27		T138	9		T174	5
values[4]	666	1			T5	17		T10	25		T43	29
values[5]	700	1			T5	13		T44	16		T45	1
values[6]	935	1			T3	9		T5	8		T7	22
values[7]	818	1			T2	26		T9	1		T41	7
values[8]	864	1			T9	1		T134	11		T144	6
values[9]	957	1			T7	22		T12	10		T13	4
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	675	1			T2	5		T12	1		T134	26
values[1]	2900	1			T10	12		T11	14		T12	23
values[2]	645	1			T143	27		T135	11		T138	9
values[3]	594	1			T5	30		T10	14		T43	29
values[4]	944	1			T10	11		T45	16		T77	14
values[5]	796	1			T2	22		T3	9		T5	8
values[6]	809	1			T2	4		T9	1		T41	7
values[7]	773	1			T9	1		T134	11		T144	6
values[8]	989	1			T6	2		T7	22		T9	1
values[9]	179	1			T13	10		T145	28		T273	1
minimum	16381	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T135	8		T138	1		T25	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	3		T12	1		T134	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T11	14		T141	15		T132	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	1		T12	13		T141	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T143	16		T174	1		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T135	11		T138	1		T16	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	6		T43	3		T135	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	9		T10	1		T43	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T45	8		T82	3		T149	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	1		T45	1		T77	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T80	1		T227	9		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	12		T3	9		T5	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T41	5		T51	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	1		T9	1		T51	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T9	1		T134	5		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T138	1		T155	9		T80	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T6	2		T7	12		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T12	10		T13	1		T155	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T145	11		T267	10		T170	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	1		T273	1		T178	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16154	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T136	1		T164	1		T220	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T138	4		T77	3		T274	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	2		T134	13		T236	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T132	14		T161	26		T164	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	11		T12	10		T26	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T143	11		T174	4		T36	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T138	8		T16	6		T149	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	7		T43	6		T26	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	8		T10	13		T43	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T45	7		T149	13		T239	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	10		T77	2		T219	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T80	13		T227	2		T265	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	10		T7	7		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T41	2		T51	1		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	3		T51	11		T143	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T134	6		T144	5		T34	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T138	11		T80	15		T190	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	10		T41	6		T132	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	3		T187	10		T228	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T145	17		T267	7		T170	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T13	9		T178	13		T268	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	2		T14	1		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T164	1		T38	1		T19	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	2		T9	1		T132	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T13	1		T274	1		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T136	1		T169	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T152	16		T135	8		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	3		T12	1		T134	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T11	14		T141	15		T132	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T10	1		T12	13		T141	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T143	16		T174	1		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T138	1		T77	20		T16	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T43	3		T135	7		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	9		T10	2		T43	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	6		T26	8		T82	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T44	16		T45	1		T77	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T45	8		T227	9		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	9		T5	8		T7	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T41	5		T51	1		T143	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	13		T9	1		T51	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T9	1		T134	5		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T80	16		T190	13		T164	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	12		T41	5		T45	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T12	10		T13	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T132	11		T145	17		T100	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T13	9		T33	12		T178	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T169	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T138	4		T31	3		T77	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T2	2		T134	13		T236	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T132	14		T161	26		T164	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T10	11		T12	10		T26	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T143	11		T174	4		T187	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T138	8		T77	19		T16	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T43	6		T36	5		T255	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	8		T10	23		T43	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	7		T26	7		T239	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T77	2		T228	3		T39	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T45	7		T227	2		T265	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	7		T219	16		T37	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T41	2		T51	1		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	13		T51	11		T143	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T134	6		T144	5		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T80	15		T190	2		T164	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	10		T41	6		T45	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T13	3		T138	11		T187	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T135	1		T138	5		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	3		T12	1		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T11	1		T141	1		T132	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T10	12		T12	11		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T143	12		T174	5		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T135	1		T138	9		T16	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	8		T43	7		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	9		T10	14		T43	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T45	8		T82	1		T149	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	11		T45	1		T77	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T80	14		T227	3		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	11		T3	1		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T41	3		T51	2		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	4		T9	1		T51	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	1		T134	7		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T138	12		T155	1		T80	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T6	2		T7	11		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T12	1		T13	4		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T145	18		T267	8		T170	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T13	10		T273	1		T178	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16287	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T136	1		T164	2		T220	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T135	7		T25	4		T77	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T2	2		T134	12		T236	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T11	13		T141	14		T132	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	12		T141	2		T77	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T143	15		T158	5		T272	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T135	10		T16	5		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	5		T43	2		T135	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T5	8		T43	9		T44	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T45	7		T82	2		T149	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T77	11		T219	15		T37	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T227	8		T265	12		T231	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	11		T3	8		T5	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T41	4		T143	16		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T51	17		T143	9		T75	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T134	4		T155	13		T80	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T155	8		T80	15		T190	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	11		T41	4		T132	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	9		T155	21		T187	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T145	10		T267	9		T170	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T178	15		T268	9		T271	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T152	15		T31	2		T246	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T38	1		T19	2		T275	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T6	2		T9	1		T132	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	10		T274	1		T33	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T136	1		T169	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T152	1		T135	1		T138	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	3		T12	1		T134	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T11	1		T141	1		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T10	12		T12	11		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T143	12		T174	5		T187	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T138	9		T77	20		T16	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T43	7		T135	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	9		T10	25		T43	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T5	8		T26	8		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T44	1		T45	1		T77	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T45	8		T227	3		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	1		T5	1		T7	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T41	3		T51	2		T143	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	15		T9	1		T51	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	1		T134	7		T144	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T80	16		T190	3		T164	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	11		T41	7		T45	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T12	1		T13	4		T138	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T132	14		T145	10		T263	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T178	15		T268	9		T276	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T152	15		T135	7		T25	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T2	2		T134	12		T236	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T11	13		T141	14		T132	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	12		T141	2		T227	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T143	15		T177	9		T272	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T77	19		T16	5		T235	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T43	2		T135	6		T255	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	8		T43	9		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	5		T26	7		T82	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T44	15		T77	11		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T45	7		T227	8		T265	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	8		T5	7		T7	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T41	4		T143	16		T75	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	11		T51	17		T143	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T134	4		T15	1		T155	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T80	15		T190	12		T164	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	11		T41	4		T45	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	9		T155	29		T187	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20