Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22047

1

T1

20

T2

26

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3638

1

T2

5

T5

25

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19122

1

T1

20

T2

26

T3

9

auto[1]

6563

1

T2

5

T6

8

T7

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	583	1			T6	6		T7	3		T45	5
values[0]	79	1			T77	13		T220	1		T267	19
values[1]	620	1			T3	9		T12	1		T43	9
values[2]	2760	1			T7	22		T9	1		T10	14
values[3]	821	1			T5	13		T10	12		T41	7
values[4]	663	1			T10	11		T141	3		T134	26
values[5]	681	1			T5	17		T6	2		T143	31
values[6]	977	1			T2	26		T5	8		T51	2
values[7]	954	1			T2	5		T9	1		T41	11
values[8]	655	1			T12	23		T145	57		T25	5
values[9]	1147	1			T7	22		T9	1		T12	10
minimum	15745	1			T1	20		T6	122		T7	214

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	889	1			T3	9		T7	22		T12	1
values[1]	2663	1			T5	13		T9	1		T10	26
values[2]	717	1			T41	7		T141	15		T45	1
values[3]	759	1			T10	11		T141	3		T134	26
values[4]	788	1			T5	17		T6	2		T51	2
values[5]	886	1			T2	26		T5	8		T143	44
values[6]	974	1			T2	5		T9	1		T12	23
values[7]	670	1			T41	11		T145	57		T25	5
values[8]	895	1			T7	22		T12	10		T13	10
values[9]	174	1			T9	1		T13	4		T45	15
minimum	16270	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T3	9		T7	12		T43	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T45	8		T145	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1508	1			T5	6		T9	1		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	1		T43	10		T135	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T41	5		T141	15		T45	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T31	2		T155	22		T139	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T155	14		T37	1		T100	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T10	1		T141	3		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	2		T164	12		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	9		T51	1		T277	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T2	13		T143	27		T132	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	8		T132	15		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	1		T12	13		T143	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T2	3		T75	21		T36	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T41	5		T145	27		T25	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T37	1		T38	2		T278	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T7	15		T51	18		T152	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	10		T13	1		T44	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T13	1		T45	8		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T9	1		T77	12		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16112	1			T1	20		T6	126		T7	217
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	10		T43	6		T134	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T45	7		T145	9		T26	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	847	1			T5	7		T10	11		T144	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	13		T43	10		T236	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T41	2		T138	19		T227	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T246	7		T190	2		T164	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T248	12		T279	11		T169	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	10		T134	13		T219	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T164	15		T106	9		T149	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	8		T51	1		T40	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	13		T143	17		T132	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T132	11		T138	4		T154	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	10		T143	11		T80	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	2		T36	5		T274	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T41	6		T145	30		T219	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T38	1		T278	2		T192	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	7		T51	11		T77	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	9		T174	4		T16	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T13	3		T45	7		T163	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T77	2		T256	4		T280	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	2		T14	1		T25	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	512	1			T6	6		T7	3		T45	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T77	12		T250	1		T281	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T220	1		T267	10		T282	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T77	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	9		T43	3		T134	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	1		T45	8		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T7	12		T9	1		T11	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	1		T43	10		T135	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	6		T10	1		T41	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T31	2		T155	22		T139	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T45	1		T135	8		T227	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	1		T141	3		T134	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	2		T143	17		T100	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	9		T221	1		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T2	13		T143	10		T132	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T5	8		T51	1		T132	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	1		T41	5		T143	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T2	3		T138	1		T75	34
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	13		T145	27		T25	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T37	1		T146	1		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T7	15		T13	1		T51	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T9	1		T12	10		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15601	1			T1	20		T6	120		T7	214
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T283	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T77	2		T281	13		T284	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T267	9		T282	2		T285	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T77	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T43	6		T134	6		T14	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T45	7		T145	9		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	840	1			T7	10		T144	5		T161	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	13		T43	10		T26	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	7		T10	11		T41	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T246	7		T190	2		T164	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T227	2		T239	12		T248	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	10		T134	13		T219	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T143	14		T106	2		T149	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	8		T164	1		T55	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	13		T143	3		T132	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T51	1		T132	11		T154	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T41	6		T143	11		T80	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	2		T138	4		T187	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	10		T145	30		T219	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T38	1		T278	2		T262	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T7	7		T13	3		T51	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	9		T174	4		T16	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T3	1		T7	11		T43	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T12	1		T45	8		T145	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T5	8		T9	1		T10	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	14		T43	11		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T41	3		T141	1		T45	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T31	2		T155	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T155	1		T37	1		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T10	11		T141	1		T134	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T6	2		T164	16		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	9		T51	2		T277	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T2	15		T143	19		T132	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	1		T132	12		T138	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T9	1		T12	11		T143	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	3		T75	1		T36	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T41	7		T145	32		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T37	1		T38	2		T278	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T7	8		T51	12		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	1		T13	10		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T13	4		T45	8		T163	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T9	1		T77	3		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16270	1			T1	20		T6	128		T7	217
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	8		T7	11		T43	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T45	7		T145	9		T135	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T5	5		T11	13		T27	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T43	9		T135	10		T236	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T41	4		T141	14		T135	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T155	21		T139	15		T246	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T155	13		T100	2		T196	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T141	2		T134	12		T219	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T164	11		T106	2		T149	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	8		T40	1		T286	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T2	11		T143	25		T132	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	7		T132	14		T31	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	12		T143	15		T152	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	2		T75	20		T235	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T41	4		T145	25		T25	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T38	1		T192	5		T232	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	14		T51	17		T152	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	9		T44	15		T16	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T45	7		T217	15		T56	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T77	11		T287	12		T288	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	512	1			T6	6		T7	3		T45	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T77	3		T250	1		T281	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T220	1		T267	10		T282	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T77	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	1		T43	7		T134	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	1		T45	8		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1149	1			T7	11		T9	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T10	14		T43	11		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	8		T10	12		T41	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T31	2		T155	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T45	1		T135	1		T227	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	11		T141	1		T134	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	2		T143	15		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	9		T221	1		T164	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T2	15		T143	4		T132	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	1		T51	2		T132	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T9	1		T41	7		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	3		T138	5		T75	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	11		T145	32		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T37	1		T146	1		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T7	8		T13	4		T51	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T9	1		T12	1		T13	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15745	1			T1	20		T6	122		T7	214
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T283	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T77	11		T281	11		T284	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T267	9		T282	2		T285	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T77	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	8		T43	2		T134	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T45	7		T145	9		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T7	11		T11	13		T27	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T43	9		T135	10		T26	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	5		T41	4		T141	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T155	21		T139	15		T246	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T135	7		T227	8		T239	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T141	2		T134	12		T219	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T143	16		T100	2		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T5	8		T55	1		T279	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T2	11		T143	9		T132	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	7		T132	14		T31	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T41	4		T143	15		T152	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	2		T75	32		T235	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	12		T145	25		T25	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T38	1		T192	5		T232	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T7	14		T51	17		T152	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	9		T44	15		T16	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20