Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21797

1

T1

20

T2

9

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3888

1

T2

22

T5

25

T6

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19281

1

T1

20

T2

31

T3

9

auto[1]

6404

1

T6

8

T7

25

T9

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	703	1			T6	6		T7	3		T45	5
values[0]	3	1			T220	1		T289	1		T290	1
values[1]	698	1			T3	9		T12	1		T43	9
values[2]	2718	1			T7	22		T9	1		T10	14
values[3]	814	1			T5	13		T10	12		T41	7
values[4]	703	1			T10	11		T141	3		T134	26
values[5]	650	1			T5	17		T6	2		T221	1
values[6]	1036	1			T2	26		T5	8		T51	2
values[7]	876	1			T2	5		T9	1		T143	27
values[8]	734	1			T12	23		T41	11		T145	28
values[9]	1005	1			T7	22		T9	1		T12	10
minimum	15745	1			T1	20		T6	122		T7	214

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	640	1			T3	9		T7	22		T12	1
values[1]	2680	1			T5	13		T9	1		T10	26
values[2]	763	1			T138	21		T31	2		T155	22
values[3]	745	1			T10	11		T141	3		T134	26
values[4]	761	1			T5	17		T6	2		T51	2
values[5]	959	1			T2	26		T5	8		T143	44
values[6]	917	1			T2	5		T9	1		T12	23
values[7]	669	1			T41	11		T145	57		T25	5
values[8]	926	1			T7	22		T12	10		T13	14
values[9]	106	1			T9	1		T45	15		T77	14
minimum	16519	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	9		T7	12		T43	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T45	8		T26	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T5	6		T10	1		T11	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	1		T10	1		T41	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T138	2		T227	9		T219	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T31	2		T155	22		T139	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	1		T45	1		T155	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T141	3		T134	13		T135	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T149	12		T150	5		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	9		T6	2		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T2	1		T143	27		T152	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	12		T5	8		T132	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	3		T9	1		T12	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T75	21		T82	14		T36	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T145	27		T25	5		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T41	5		T219	10		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T13	1		T51	18		T152	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T7	15		T12	10		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T9	1		T45	8		T77	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T250	1		T291	1		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16174	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T145	10		T106	1		T166	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	10		T43	6		T134	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T45	7		T26	7		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	850	1			T5	7		T10	11		T144	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	13		T41	2		T43	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T138	19		T227	2		T219	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T164	11		T239	12		T257	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T10	10		T239	4		T255	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T134	13		T55	19		T293	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T149	13		T150	3		T245	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	8		T51	1		T164	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	3		T143	17		T227	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	10		T132	25		T138	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T2	2		T12	10		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T36	5		T38	2		T274	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T145	30		T187	4		T229	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T41	6		T219	9		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	3		T51	11		T16	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	7		T13	9		T174	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T45	7		T77	2		T163	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T288	7		T215	4		T294	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	2		T14	7		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T145	9		T106	16		T160	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	564	1			T6	6		T7	3		T45	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T231	3		T250	1		T166	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T220	1		T289	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	9		T43	3		T134	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T45	8		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T7	12		T11	14		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	1		T10	1		T43	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	6		T10	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T41	5		T141	15		T31	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	1		T45	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T141	3		T134	13		T135	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T149	12		T17	2		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	9		T6	2		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T2	1		T143	27		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	12		T5	8		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	3		T9	1		T143	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T138	1		T75	21		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	13		T145	11		T25	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T41	5		T82	14		T219	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T9	1		T13	1		T51	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	15		T12	10		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15601	1			T1	20		T6	120		T7	214
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T77	2		T163	2		T239	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T231	4		T280	8		T21	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T43	6		T134	6		T14	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T45	7		T145	9		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	846	1			T7	10		T144	5		T161	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	13		T43	10		T26	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T5	7		T10	11		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T41	2		T80	2		T164	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	10		T138	8		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T134	13		T239	12		T293	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T149	13		T245	3		T180	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	8		T164	1		T40	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	3		T143	17		T150	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	10		T51	1		T132	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T2	2		T143	11		T80	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T138	4		T187	1		T36	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	10		T145	17		T187	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T41	6		T219	9		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	3		T51	11		T45	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	7		T13	9		T174	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	1		T7	11		T43	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	1		T45	8		T26	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T5	8		T10	12		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	1		T10	14		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T138	21		T227	3		T219	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T31	2		T155	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	11		T45	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T141	1		T134	14		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T149	14		T150	4		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	9		T6	2		T51	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T2	4		T143	19		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	11		T5	1		T132	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	3		T9	1		T12	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T75	1		T82	1		T36	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T145	32		T25	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T41	7		T219	10		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T13	4		T51	12		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	8		T12	1		T13	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T9	1		T45	8		T77	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T250	1		T291	1		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16340	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T145	10		T106	17		T166	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	8		T7	11		T43	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	7		T26	7		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T5	5		T11	13		T27	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T41	4		T43	9		T141	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T227	8		T219	15		T246	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T155	21		T139	15		T164	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T155	13		T239	11		T255	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T141	2		T134	12		T135	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T149	11		T150	4		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	8		T164	11		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T143	25		T152	15		T75	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	11		T5	7		T132	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T2	2		T12	12		T143	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T75	20		T82	13		T149	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T145	25		T25	4		T187	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T41	4		T219	9		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T51	17		T152	13		T80	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	14		T12	9		T44	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T45	7		T77	11		T260	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T287	12		T288	7		T294	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T14	4		T216	8		T19	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T145	9		T160	10		T272	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	537	1			T6	6		T7	3		T45	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T231	6		T250	1		T166	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T220	1		T289	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	1		T43	7		T134	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	1		T45	8		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1153	1			T7	11		T11	1		T144	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	1		T10	14		T43	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T5	8		T10	12		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T41	3		T141	1		T31	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	11		T45	1		T138	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T141	1		T134	14		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T149	14		T17	2		T245	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	9		T6	2		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T2	4		T143	19		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T2	11		T5	1		T51	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	3		T9	1		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T138	5		T75	1		T187	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	11		T145	18		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T41	7		T82	1		T219	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T9	1		T13	4		T51	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	8		T12	1		T13	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15745	1			T1	20		T6	122		T7	214
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T77	11		T239	10		T196	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T231	1		T166	15		T281	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	8		T43	2		T134	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T45	7		T145	9		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T7	11		T11	13		T27	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T43	9		T135	10		T26	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	5		T246	7		T190	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T41	4		T141	14		T155	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T155	13		T227	8		T219	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T141	2		T134	12		T135	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T149	11		T295	8		T217	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	8		T100	2		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T143	25		T150	4		T232	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	11		T5	7		T132	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	2		T143	15		T152	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T75	20		T235	18		T296	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	12		T145	10		T25	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T41	4		T82	13		T219	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T51	17		T152	13		T45	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	14		T12	9		T44	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20