Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22150

1

T1

20

T2

9

T5

8

auto[ADC_CTRL_FILTER_COND_OUT]

3535

1

T2

22

T3

9

T5

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19399

1

T1

20

T2

4

T5

25

auto[1]

6286

1

T2

27

T3

9

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	36	1			T3	9		T279	18		T295	9
values[0]	61	1			T9	1		T164	2		T230	25
values[1]	733	1			T43	20		T144	6		T132	26
values[2]	733	1			T2	5		T12	1		T41	11
values[3]	583	1			T152	30		T45	15		T221	1
values[4]	855	1			T5	17		T9	1		T10	12
values[5]	696	1			T2	22		T5	13		T134	11
values[6]	596	1			T6	2		T12	23		T13	4
values[7]	760	1			T10	25		T41	7		T43	9
values[8]	3121	1			T11	14		T12	10		T161	29
values[9]	1257	1			T2	4		T5	8		T7	44
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	829	1			T9	1		T43	20		T144	6
values[1]	741	1			T2	5		T41	11		T152	30
values[2]	773	1			T5	17		T12	1		T141	18
values[3]	734	1			T2	22		T9	1		T10	12
values[4]	652	1			T5	13		T12	23		T13	10
values[5]	630	1			T6	2		T10	11		T13	4
values[6]	2920	1			T10	14		T11	14		T12	10
values[7]	961	1			T143	27		T31	2		T174	5
values[8]	863	1			T2	4		T3	9		T7	44
values[9]	257	1			T5	8		T134	26		T143	13
minimum	16325	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T9	1		T43	10		T132	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T144	1		T80	2		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	3		T41	5		T219	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T152	30		T135	8		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T141	18		T143	17		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	9		T12	1		T297	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T9	1		T132	6		T45	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	12		T10	1		T45	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	1		T134	5		T26	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	6		T12	13		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	1		T14	9		T77	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	2		T10	1		T41	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T11	14		T12	10		T161	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	1		T145	11		T164	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T31	2		T174	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T143	16		T80	1		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T2	1		T7	27		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	9		T44	16		T51	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T5	8		T134	13		T143	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T297	1		T192	6		T279	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16123	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T266	9		T22	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T43	10		T132	11		T154	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T144	5		T164	1		T230	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	2		T41	6		T219	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	11		T219	9		T187	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T143	14		T145	9		T164	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T5	8		T163	2		T240	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T132	14		T45	7		T138	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T2	10		T10	11		T45	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	9		T134	6		T26	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	7		T12	10		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	3		T14	6		T77	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	10		T41	2		T43	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T161	26		T246	7		T188	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	13		T145	17		T164	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T174	4		T137	6		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T143	11		T80	13		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	3		T7	17		T51	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T51	11		T145	13		T227	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T134	13		T143	3		T171	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T192	4		T279	11		T298	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	2		T14	1		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T266	16		T22	1		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T3	9		T279	7		T295	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T9	1		T253	1		T258	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T164	1		T230	14		T289	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T43	10		T132	15		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T144	1		T80	2		T262	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	3		T41	5		T141	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	1		T135	8		T219	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T221	1		T155	9		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T152	30		T45	8		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T9	1		T13	1		T141	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	9		T10	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T134	5		T45	8		T25	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	12		T5	6		T31	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	1		T77	10		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	2		T12	13		T75	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	9		T246	8		T100	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	2		T41	5		T43	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T11	14		T12	10		T161	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T80	1		T38	2		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T2	1		T5	8		T7	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T44	16		T51	18		T143	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T279	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T258	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T164	1		T230	11		T299	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T43	10		T132	11		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T144	5		T262	10		T293	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	2		T41	6		T154	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T219	9		T187	4		T177	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T137	9		T164	15		T55	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T45	7		T138	11		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	9		T143	14		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T5	8		T10	11		T138	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T134	6		T45	7		T26	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	10		T5	7		T31	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	3		T77	3		T149	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	10		T190	2		T34	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	6		T246	7		T100	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	23		T41	2		T43	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T161	26		T137	6		T188	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T80	13		T38	1		T274	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T2	3		T7	17		T51	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T51	11		T143	11		T145	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	1		T43	11		T132	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T144	6		T80	1		T164	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	3		T41	7		T219	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T152	2		T135	1		T138	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T141	2		T143	15		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	9		T12	1		T297	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T9	1		T132	15		T45	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T2	11		T10	12		T45	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	10		T134	7		T26	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	8		T12	11		T31	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	4		T14	11		T77	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	2		T10	11		T41	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T11	1		T12	1		T161	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	14		T145	18		T164	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T31	2		T174	5		T137	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T143	12		T80	14		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	4		T7	19		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	1		T44	1		T51	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T5	1		T134	14		T143	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T297	1		T192	5		T279	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16283	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T266	17		T22	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T43	9		T132	14		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T80	1		T230	10		T293	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	2		T41	4		T219	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T152	28		T135	7		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T141	16		T143	16		T145	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	8		T296	18		T191	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T132	5		T45	7		T25	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T2	11		T45	7		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T134	4		T26	7		T77	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T5	5		T12	12		T31	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	4		T77	9		T216	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T41	4		T43	2		T82	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T11	13		T12	9		T27	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T145	10		T164	3		T16	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T231	1		T18	4		T257	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T143	15		T38	1		T228	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	25		T135	6		T236	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	8		T44	15		T51	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T5	7		T134	12		T143	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T192	5		T279	6		T298	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T300	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T266	8		T22	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T3	1		T279	12		T295	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T9	1		T253	1		T258	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T164	2		T230	15		T289	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T43	11		T132	12		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T144	6		T80	1		T262	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	3		T41	7		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T135	1		T219	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T221	1		T155	1		T137	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T152	2		T45	8		T138	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T9	1		T13	10		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	9		T10	12		T138	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T134	7		T45	8		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	11		T5	8		T31	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	4		T77	4		T149	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	2		T12	11		T75	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	11		T246	8		T100	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	25		T41	3		T43	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T11	1		T12	1		T161	29
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T80	14		T38	2		T274	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T2	4		T5	1		T7	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T44	1		T51	12		T143	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T3	8		T279	6		T295	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T258	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T230	10		T299	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T43	9		T132	14		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T80	1		T293	7		T266	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	2		T41	4		T141	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T135	7		T219	9		T187	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T155	8		T164	11		T235	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T152	28		T45	7		T155	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T141	2		T143	16		T132	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	8		T228	2		T39	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T134	4		T45	7		T25	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T2	11		T5	5		T31	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T77	9		T149	11		T150	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	12		T75	12		T82	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	4		T246	7		T100	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T41	4		T43	2		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T11	13		T12	9		T27	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T38	1		T228	6		T235	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T5	7		T7	25		T134	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T44	15		T51	17		T143	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20