Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25685

1

T1

20

T2

31

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19837

1

T1

20

T2

4

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

5848

1

T2

27

T5

25

T7

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19482

1

T1

20

T3

9

T5

17

auto[1]

6203

1

T2

31

T5

21

T7

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21535

1

T1

20

T2

16

T3

9

auto[1]

4150

1

T2

15

T5

15

T6

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	17	1			T232	17		-	-		-	-
values[0]	111	1			T155	14		T236	14		T250	1
values[1]	813	1			T2	4		T41	11		T152	14
values[2]	917	1			T5	8		T12	1		T13	4
values[3]	595	1			T3	9		T7	22		T10	12
values[4]	943	1			T7	22		T9	1		T10	14
values[5]	907	1			T5	13		T12	23		T13	10
values[6]	615	1			T51	2		T143	13		T45	16
values[7]	540	1			T2	27		T9	2		T12	10
values[8]	847	1			T5	17		T43	9		T134	26
values[9]	3126	1			T6	2		T10	11		T11	14
minimum	16254	1			T1	20		T6	128		T7	217

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1046	1			T2	4		T41	11		T145	28
values[1]	3047	1			T7	22		T10	12		T11	14
values[2]	669	1			T3	9		T5	8		T10	14
values[3]	854	1			T7	22		T9	1		T12	23
values[4]	786	1			T5	13		T13	10		T44	16
values[5]	746	1			T9	1		T12	10		T43	20
values[6]	597	1			T2	22		T9	1		T134	26
values[7]	712	1			T2	5		T5	17		T43	9
values[8]	698	1			T10	11		T141	3		T134	11
values[9]	235	1			T6	2		T132	20		T15	5
minimum	16295	1			T1	20		T6	128		T7	217

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

4344

1

T2

13

T3

8

T5

20

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T2	1		T14	9		T77	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T41	5		T145	11		T155	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	1		T13	1		T227	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1683	1			T7	15		T10	1		T11	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	9		T10	1		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	8		T143	16		T75	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T45	8		T154	1		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T7	12		T9	1		T12	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	6		T44	16		T132	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	1		T143	17		T155	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T43	10		T144	1		T45	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	1		T12	10		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T138	2		T163	1		T39	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	12		T9	1		T134	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T43	3		T141	15		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	3		T5	9		T145	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	1		T134	5		T135	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T141	3		T297	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T6	2		T132	6		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T108	1		T210	1		T301	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16120	1			T1	20		T6	126		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T302	1		T303	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T2	3		T14	6		T77	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T41	6		T145	17		T236	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	3		T227	2		T228	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	979	1			T7	7		T10	11		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	13		T145	9		T77	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T143	11		T16	6		T293	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T45	7		T154	10		T36	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	10		T12	10		T41	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	7		T132	11		T80	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	9		T143	14		T164	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T43	10		T144	5		T45	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T51	1		T143	3		T278	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T138	12		T163	2		T39	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T2	10		T134	13		T38	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T43	6		T138	11		T246	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	2		T5	8		T145	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	10		T134	6		T174	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T137	6		T164	1		T187	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T132	14		T15	1		T239	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T210	12		T301	13		T251	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	2		T14	1		T25	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T303	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T232	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T250	1		T263	3		T170	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T155	14		T236	8		T302	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	1		T77	20		T82	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T41	5		T152	14		T145	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	1		T13	1		T14	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T5	8		T51	18		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T3	9		T145	10		T135	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	15		T10	1		T26	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T10	1		T45	8		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T7	12		T9	1		T143	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	6		T44	16		T132	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T12	13		T13	1		T41	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T45	9		T31	4		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T51	1		T143	10		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	10		T144	1		T138	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	15		T9	2		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T43	3		T75	13		T246	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	9		T134	13		T145	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T6	2		T10	1		T141	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1622	1			T11	14		T141	3		T161	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16110	1			T1	20		T6	126		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T232	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T263	6		T170	18		T215	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T236	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	3		T77	19		T137	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T41	6		T145	17		T37	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	3		T14	6		T227	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T51	11		T147	8		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T145	9		T304	1		T178	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	7		T10	11		T26	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	13		T45	7		T154	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	10		T143	11		T190	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	7		T132	11		T80	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	10		T13	9		T41	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T45	7		T31	3		T80	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T51	1		T143	3		T187	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T43	10		T144	5		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T2	12		T38	1		T34	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T43	6		T246	7		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	8		T134	13		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T10	10		T134	6		T132	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	878	1			T161	26		T26	11		T137	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T14	1		T25	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T2	4		T14	11		T77	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T41	7		T145	18		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	1		T13	4		T227	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1303	1			T7	8		T10	12		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	1		T10	14		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T143	12		T75	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T45	8		T154	11		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T7	11		T9	1		T12	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	8		T44	1		T132	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	10		T143	15		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T43	11		T144	6		T45	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	1		T12	1		T51	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T138	14		T163	3		T39	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	11		T9	1		T134	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T43	7		T141	1		T138	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	3		T5	9		T145	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	11		T134	7		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T141	1		T297	1		T137	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T6	2		T132	15		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T108	1		T210	13		T301	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16272	1			T1	20		T6	128		T7	217
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T302	1		T303	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	4		T77	19		T82	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T41	4		T145	10		T155	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T227	8		T228	6		T242	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1359	1			T7	14		T11	13		T51	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	8		T145	9		T135	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	7		T143	15		T75	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T45	7		T279	16		T266	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T7	11		T12	12		T41	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	5		T44	15		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T143	16		T155	21		T164	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	9		T45	7		T31	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	9		T143	9		T135	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T39	5		T150	11		T296	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T2	11		T134	12		T152	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T43	2		T141	14		T75	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	2		T5	8		T145	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T134	4		T135	7		T219	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T141	2		T187	11		T235	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T132	5		T15	1		T239	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T301	13		T305	14		T306	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T307	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T303	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T232	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T250	1		T263	8		T170	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T155	1		T236	7		T302	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	4		T77	20		T82	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T41	7		T152	1		T145	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T12	1		T13	4		T14	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T51	12		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	1		T145	10		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	8		T10	12		T26	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	14		T45	8		T154	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T7	11		T9	1		T143	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	8		T44	1		T132	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	11		T13	10		T41	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T45	9		T31	5		T80	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T51	2		T143	4		T187	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T43	11		T144	6		T138	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	14		T9	2		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T43	7		T75	1		T246	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	9		T134	14		T145	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T6	2		T10	11		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1202	1			T11	1		T141	1		T161	29
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T1	20		T6	128		T7	217
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T232	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T263	1		T170	11		T90	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T155	13		T236	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T77	19		T82	2		T100	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T41	4		T152	13		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	4		T227	8		T228	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T5	7		T51	17		T100	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T3	8		T145	9		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	14		T26	7		T232	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T45	7		T77	9		T219	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T7	11		T143	15		T75	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	5		T44	15		T132	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	12		T41	4		T143	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T45	7		T31	2		T39	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T143	9		T150	4		T35	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T43	9		T227	4		T150	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	13		T12	9		T152	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T43	2		T75	12		T246	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	8		T134	12		T145	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T141	14		T134	4		T132	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1298	1			T11	13		T141	2		T27	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21341

1

T1

20

T2

18

T3

1

auto[1]

auto[0]

4344

1

T2

13

T3

8

T5

20