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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.07 96.67 100.00 100.00 98.83 98.33 91.46


Total test records in report: 920
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T799 /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3000853251 Jul 26 06:51:04 PM PDT 24 Jul 26 07:06:46 PM PDT 24 399802843211 ps
T800 /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1317504294 Jul 26 06:55:48 PM PDT 24 Jul 26 06:55:57 PM PDT 24 9155637952 ps
T801 /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1957769350 Jul 26 06:55:54 PM PDT 24 Jul 26 07:01:02 PM PDT 24 338365677465 ps
T802 /workspace/coverage/default/30.adc_ctrl_fsm_reset.2622406738 Jul 26 06:53:19 PM PDT 24 Jul 26 07:00:02 PM PDT 24 112637694745 ps
T803 /workspace/coverage/default/29.adc_ctrl_fsm_reset.2273434821 Jul 26 06:53:06 PM PDT 24 Jul 26 06:57:14 PM PDT 24 82305746332 ps
T804 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2386301174 Jul 26 05:45:09 PM PDT 24 Jul 26 05:45:10 PM PDT 24 364237228 ps
T126 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3411043205 Jul 26 05:45:04 PM PDT 24 Jul 26 05:45:06 PM PDT 24 434248113 ps
T109 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1517462955 Jul 26 05:44:52 PM PDT 24 Jul 26 05:44:54 PM PDT 24 387299049 ps
T86 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.776443317 Jul 26 05:45:01 PM PDT 24 Jul 26 05:45:03 PM PDT 24 398763462 ps
T805 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2052920367 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:08 PM PDT 24 310058694 ps
T63 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3050596656 Jul 26 05:45:03 PM PDT 24 Jul 26 05:45:06 PM PDT 24 675726441 ps
T110 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3548535929 Jul 26 05:45:09 PM PDT 24 Jul 26 05:45:10 PM PDT 24 519015703 ps
T806 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.156143948 Jul 26 05:45:13 PM PDT 24 Jul 26 05:45:14 PM PDT 24 471428880 ps
T52 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3434609278 Jul 26 05:44:56 PM PDT 24 Jul 26 05:45:13 PM PDT 24 9103891819 ps
T111 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3173175618 Jul 26 05:45:01 PM PDT 24 Jul 26 05:45:04 PM PDT 24 792819767 ps
T60 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1859331596 Jul 26 05:45:02 PM PDT 24 Jul 26 05:45:04 PM PDT 24 472121866 ps
T807 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2181461870 Jul 26 05:45:02 PM PDT 24 Jul 26 05:45:04 PM PDT 24 472766470 ps
T808 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.766084359 Jul 26 05:45:03 PM PDT 24 Jul 26 05:45:04 PM PDT 24 525417092 ps
T50 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3309544584 Jul 26 05:45:08 PM PDT 24 Jul 26 05:45:22 PM PDT 24 3706671397 ps
T53 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3806980104 Jul 26 05:45:10 PM PDT 24 Jul 26 05:45:22 PM PDT 24 4633295991 ps
T47 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2186643268 Jul 26 05:45:02 PM PDT 24 Jul 26 05:45:08 PM PDT 24 2485699121 ps
T131 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.495611213 Jul 26 05:44:56 PM PDT 24 Jul 26 05:44:59 PM PDT 24 1080609176 ps
T54 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2485040428 Jul 26 05:44:54 PM PDT 24 Jul 26 05:44:58 PM PDT 24 4393308376 ps
T69 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1449848071 Jul 26 05:44:57 PM PDT 24 Jul 26 05:44:59 PM PDT 24 355656389 ps
T67 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1881155501 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:20 PM PDT 24 4462124873 ps
T87 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1572457914 Jul 26 05:44:54 PM PDT 24 Jul 26 05:44:56 PM PDT 24 329287131 ps
T809 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2403916351 Jul 26 05:45:09 PM PDT 24 Jul 26 05:45:11 PM PDT 24 375445136 ps
T48 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1972483966 Jul 26 05:44:49 PM PDT 24 Jul 26 05:45:06 PM PDT 24 4788687452 ps
T49 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2197542969 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:08 PM PDT 24 411557685 ps
T64 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1545864584 Jul 26 05:44:50 PM PDT 24 Jul 26 05:44:53 PM PDT 24 441526098 ps
T97 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2378052650 Jul 26 05:45:10 PM PDT 24 Jul 26 05:45:12 PM PDT 24 546695356 ps
T810 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2334774019 Jul 26 05:44:53 PM PDT 24 Jul 26 05:44:54 PM PDT 24 380970477 ps
T66 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2013857822 Jul 26 05:44:56 PM PDT 24 Jul 26 05:45:00 PM PDT 24 5862285429 ps
T811 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.171687577 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:07 PM PDT 24 376382078 ps
T127 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.134289015 Jul 26 05:44:54 PM PDT 24 Jul 26 05:45:00 PM PDT 24 2471121103 ps
T112 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3866199358 Jul 26 05:45:13 PM PDT 24 Jul 26 05:45:17 PM PDT 24 1080611950 ps
T128 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2740192113 Jul 26 05:45:01 PM PDT 24 Jul 26 05:45:02 PM PDT 24 608934713 ps
T113 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1197636324 Jul 26 05:44:52 PM PDT 24 Jul 26 05:44:53 PM PDT 24 378016659 ps
T812 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1688222150 Jul 26 05:45:20 PM PDT 24 Jul 26 05:45:22 PM PDT 24 306222230 ps
T129 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4251123801 Jul 26 05:44:52 PM PDT 24 Jul 26 05:44:54 PM PDT 24 535834742 ps
T114 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.936530071 Jul 26 05:44:50 PM PDT 24 Jul 26 05:44:52 PM PDT 24 1271001236 ps
T130 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2965031785 Jul 26 05:44:57 PM PDT 24 Jul 26 05:45:03 PM PDT 24 2660429273 ps
T813 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1188098269 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:09 PM PDT 24 2328101666 ps
T814 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3089482176 Jul 26 05:45:02 PM PDT 24 Jul 26 05:45:03 PM PDT 24 535789871 ps
T61 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.783393251 Jul 26 05:44:57 PM PDT 24 Jul 26 05:45:00 PM PDT 24 408054042 ps
T815 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3071100769 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:10 PM PDT 24 700393111 ps
T816 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1972893569 Jul 26 05:44:55 PM PDT 24 Jul 26 05:44:56 PM PDT 24 411400255 ps
T817 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.271352549 Jul 26 05:45:04 PM PDT 24 Jul 26 05:45:06 PM PDT 24 482548620 ps
T818 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2800999104 Jul 26 05:44:44 PM PDT 24 Jul 26 05:44:45 PM PDT 24 433846732 ps
T68 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3765967103 Jul 26 05:44:51 PM PDT 24 Jul 26 05:44:53 PM PDT 24 502732838 ps
T819 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3678160334 Jul 26 05:45:05 PM PDT 24 Jul 26 05:45:06 PM PDT 24 322605852 ps
T820 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4029561849 Jul 26 05:44:51 PM PDT 24 Jul 26 05:44:52 PM PDT 24 519050204 ps
T821 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.526833235 Jul 26 05:45:01 PM PDT 24 Jul 26 05:45:03 PM PDT 24 439816958 ps
T115 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.943091971 Jul 26 05:44:52 PM PDT 24 Jul 26 05:44:54 PM PDT 24 534230213 ps
T822 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.641008424 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:10 PM PDT 24 2562550960 ps
T116 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4273120850 Jul 26 05:45:02 PM PDT 24 Jul 26 05:45:04 PM PDT 24 566668790 ps
T823 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3361365024 Jul 26 05:45:00 PM PDT 24 Jul 26 05:45:02 PM PDT 24 915635251 ps
T824 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4151741064 Jul 26 05:44:47 PM PDT 24 Jul 26 05:44:49 PM PDT 24 327290929 ps
T117 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3089540141 Jul 26 05:44:54 PM PDT 24 Jul 26 05:44:57 PM PDT 24 502909081 ps
T825 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.633212894 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:15 PM PDT 24 2055655139 ps
T826 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2312263075 Jul 26 05:45:03 PM PDT 24 Jul 26 05:45:06 PM PDT 24 4507021157 ps
T118 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1711507917 Jul 26 05:44:53 PM PDT 24 Jul 26 05:44:55 PM PDT 24 485460438 ps
T827 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2095623256 Jul 26 05:44:57 PM PDT 24 Jul 26 05:44:58 PM PDT 24 374287606 ps
T828 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4085608508 Jul 26 05:45:10 PM PDT 24 Jul 26 05:45:12 PM PDT 24 369417037 ps
T829 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.403665685 Jul 26 05:45:15 PM PDT 24 Jul 26 05:45:17 PM PDT 24 310629758 ps
T830 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1926597110 Jul 26 05:45:38 PM PDT 24 Jul 26 05:45:39 PM PDT 24 424065482 ps
T831 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2208963989 Jul 26 05:45:10 PM PDT 24 Jul 26 05:45:11 PM PDT 24 367819201 ps
T832 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2050367716 Jul 26 05:44:54 PM PDT 24 Jul 26 05:45:02 PM PDT 24 4793879728 ps
T833 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1760836409 Jul 26 05:45:10 PM PDT 24 Jul 26 05:45:12 PM PDT 24 384046402 ps
T834 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2259641149 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:08 PM PDT 24 320499713 ps
T835 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3563300101 Jul 26 05:45:09 PM PDT 24 Jul 26 05:45:10 PM PDT 24 333933956 ps
T62 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3732662117 Jul 26 05:44:54 PM PDT 24 Jul 26 05:44:56 PM PDT 24 720642153 ps
T836 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4108146684 Jul 26 05:44:52 PM PDT 24 Jul 26 05:44:58 PM PDT 24 422259772 ps
T837 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1317180627 Jul 26 05:44:50 PM PDT 24 Jul 26 05:44:54 PM PDT 24 1238272993 ps
T71 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2635919346 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:19 PM PDT 24 8819770469 ps
T334 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2645846291 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:13 PM PDT 24 4560568140 ps
T838 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1165790072 Jul 26 05:45:03 PM PDT 24 Jul 26 05:45:05 PM PDT 24 653096268 ps
T70 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3827691193 Jul 26 05:45:00 PM PDT 24 Jul 26 05:45:02 PM PDT 24 709267228 ps
T839 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1552116429 Jul 26 05:44:53 PM PDT 24 Jul 26 05:45:17 PM PDT 24 9046862140 ps
T72 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.588495899 Jul 26 05:44:56 PM PDT 24 Jul 26 05:45:04 PM PDT 24 8688538305 ps
T840 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.716277042 Jul 26 05:45:00 PM PDT 24 Jul 26 05:45:02 PM PDT 24 427637862 ps
T841 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1795257392 Jul 26 05:44:51 PM PDT 24 Jul 26 05:45:04 PM PDT 24 4711933217 ps
T119 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3558973600 Jul 26 05:44:47 PM PDT 24 Jul 26 05:44:48 PM PDT 24 427423004 ps
T842 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3952003263 Jul 26 05:44:57 PM PDT 24 Jul 26 05:44:59 PM PDT 24 505085149 ps
T843 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3691035950 Jul 26 05:45:04 PM PDT 24 Jul 26 05:45:06 PM PDT 24 474730472 ps
T844 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.591562364 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:16 PM PDT 24 4462947542 ps
T845 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3296879114 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:07 PM PDT 24 300355995 ps
T846 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.578637529 Jul 26 05:44:55 PM PDT 24 Jul 26 05:44:57 PM PDT 24 596347625 ps
T847 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2924260068 Jul 26 05:44:51 PM PDT 24 Jul 26 05:44:55 PM PDT 24 3304460381 ps
T848 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.874758052 Jul 26 05:45:08 PM PDT 24 Jul 26 05:45:09 PM PDT 24 413186204 ps
T849 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.746847086 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:07 PM PDT 24 446226136 ps
T850 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1917356267 Jul 26 05:45:08 PM PDT 24 Jul 26 05:45:08 PM PDT 24 357661476 ps
T851 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2957947293 Jul 26 05:44:47 PM PDT 24 Jul 26 05:46:36 PM PDT 24 27107662714 ps
T852 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2445820007 Jul 26 05:44:55 PM PDT 24 Jul 26 05:45:16 PM PDT 24 8396049911 ps
T853 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1783612780 Jul 26 05:45:02 PM PDT 24 Jul 26 05:45:05 PM PDT 24 484088916 ps
T854 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1604561840 Jul 26 05:45:00 PM PDT 24 Jul 26 05:45:04 PM PDT 24 557346069 ps
T855 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4020906836 Jul 26 05:45:16 PM PDT 24 Jul 26 05:45:17 PM PDT 24 295691559 ps
T856 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.79966086 Jul 26 05:45:08 PM PDT 24 Jul 26 05:45:10 PM PDT 24 2043404265 ps
T857 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4256474161 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:09 PM PDT 24 381508197 ps
T858 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.156695691 Jul 26 05:44:49 PM PDT 24 Jul 26 05:44:51 PM PDT 24 506328486 ps
T859 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2976579134 Jul 26 05:45:08 PM PDT 24 Jul 26 05:45:13 PM PDT 24 2679081005 ps
T860 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1326224155 Jul 26 05:44:53 PM PDT 24 Jul 26 05:44:57 PM PDT 24 4569813092 ps
T861 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1672877835 Jul 26 05:44:56 PM PDT 24 Jul 26 05:44:57 PM PDT 24 434138170 ps
T862 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2239214339 Jul 26 05:45:02 PM PDT 24 Jul 26 05:45:04 PM PDT 24 334633703 ps
T120 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2647767013 Jul 26 05:44:54 PM PDT 24 Jul 26 05:44:57 PM PDT 24 796369008 ps
T863 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3582258032 Jul 26 05:45:09 PM PDT 24 Jul 26 05:45:10 PM PDT 24 474103044 ps
T864 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2713507522 Jul 26 05:44:46 PM PDT 24 Jul 26 05:44:48 PM PDT 24 434523940 ps
T865 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2180999703 Jul 26 05:45:03 PM PDT 24 Jul 26 05:45:06 PM PDT 24 564037063 ps
T866 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3167166444 Jul 26 05:45:08 PM PDT 24 Jul 26 05:45:11 PM PDT 24 545307970 ps
T867 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.29561313 Jul 26 05:45:05 PM PDT 24 Jul 26 05:45:07 PM PDT 24 520300072 ps
T868 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.67463025 Jul 26 05:44:53 PM PDT 24 Jul 26 05:46:33 PM PDT 24 26258694317 ps
T869 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2048296300 Jul 26 05:44:51 PM PDT 24 Jul 26 05:44:57 PM PDT 24 4147810418 ps
T121 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1364352352 Jul 26 05:44:53 PM PDT 24 Jul 26 05:44:57 PM PDT 24 866905397 ps
T870 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.643456770 Jul 26 05:45:26 PM PDT 24 Jul 26 05:45:27 PM PDT 24 345673585 ps
T871 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.517153302 Jul 26 05:44:48 PM PDT 24 Jul 26 05:44:50 PM PDT 24 533831000 ps
T872 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1819563339 Jul 26 05:44:42 PM PDT 24 Jul 26 05:44:43 PM PDT 24 383841533 ps
T122 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1781671226 Jul 26 05:45:03 PM PDT 24 Jul 26 05:45:05 PM PDT 24 361741784 ps
T873 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2238296146 Jul 26 05:45:08 PM PDT 24 Jul 26 05:45:09 PM PDT 24 342114000 ps
T874 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.205910989 Jul 26 05:45:02 PM PDT 24 Jul 26 05:45:03 PM PDT 24 502346475 ps
T875 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.44464903 Jul 26 05:44:58 PM PDT 24 Jul 26 05:45:01 PM PDT 24 389388176 ps
T876 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1173157570 Jul 26 05:45:01 PM PDT 24 Jul 26 05:45:02 PM PDT 24 358937406 ps
T877 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.875072309 Jul 26 05:44:54 PM PDT 24 Jul 26 05:45:01 PM PDT 24 2920871551 ps
T878 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3095200704 Jul 26 05:45:09 PM PDT 24 Jul 26 05:45:11 PM PDT 24 442061487 ps
T123 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4017552103 Jul 26 05:44:53 PM PDT 24 Jul 26 05:44:57 PM PDT 24 1043492500 ps
T879 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1786532087 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:09 PM PDT 24 2699900074 ps
T880 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1436163845 Jul 26 05:45:09 PM PDT 24 Jul 26 05:45:10 PM PDT 24 373037276 ps
T881 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.457366314 Jul 26 05:44:43 PM PDT 24 Jul 26 05:44:46 PM PDT 24 877070748 ps
T882 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3269396472 Jul 26 05:45:00 PM PDT 24 Jul 26 05:45:03 PM PDT 24 417977257 ps
T883 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.347976983 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:07 PM PDT 24 542151706 ps
T884 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.973472374 Jul 26 05:44:48 PM PDT 24 Jul 26 05:44:57 PM PDT 24 9171831406 ps
T885 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3183389662 Jul 26 05:45:02 PM PDT 24 Jul 26 05:45:08 PM PDT 24 8476283690 ps
T124 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2325955372 Jul 26 05:44:53 PM PDT 24 Jul 26 05:45:10 PM PDT 24 6804207911 ps
T125 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.812280442 Jul 26 05:44:58 PM PDT 24 Jul 26 05:44:59 PM PDT 24 320485262 ps
T336 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3609404972 Jul 26 05:45:11 PM PDT 24 Jul 26 05:45:32 PM PDT 24 7643832279 ps
T886 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.885045558 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:09 PM PDT 24 499321295 ps
T887 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3671736780 Jul 26 05:45:01 PM PDT 24 Jul 26 05:45:03 PM PDT 24 532779876 ps
T888 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2314402352 Jul 26 05:44:54 PM PDT 24 Jul 26 05:44:58 PM PDT 24 358476816 ps
T889 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.196689698 Jul 26 05:45:09 PM PDT 24 Jul 26 05:45:11 PM PDT 24 484770023 ps
T890 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.490404258 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:08 PM PDT 24 405997818 ps
T891 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3921849258 Jul 26 05:44:53 PM PDT 24 Jul 26 05:44:56 PM PDT 24 437968807 ps
T892 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2542655449 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:07 PM PDT 24 579809037 ps
T893 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2713573762 Jul 26 05:45:03 PM PDT 24 Jul 26 05:45:06 PM PDT 24 502370335 ps
T894 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1482195807 Jul 26 05:45:01 PM PDT 24 Jul 26 05:45:13 PM PDT 24 4375323988 ps
T895 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1765254697 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:08 PM PDT 24 327927065 ps
T896 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.662774699 Jul 26 05:45:04 PM PDT 24 Jul 26 05:45:06 PM PDT 24 438454969 ps
T897 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3726298070 Jul 26 05:45:08 PM PDT 24 Jul 26 05:45:15 PM PDT 24 2974844540 ps
T898 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2586264520 Jul 26 05:45:05 PM PDT 24 Jul 26 05:45:06 PM PDT 24 540369236 ps
T899 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4217464536 Jul 26 05:45:09 PM PDT 24 Jul 26 05:45:10 PM PDT 24 366099856 ps
T900 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.377263601 Jul 26 05:45:09 PM PDT 24 Jul 26 05:45:11 PM PDT 24 477200798 ps
T901 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1249528183 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:08 PM PDT 24 2912174985 ps
T902 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.466265274 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:08 PM PDT 24 498569121 ps
T903 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1667274624 Jul 26 05:44:50 PM PDT 24 Jul 26 05:44:53 PM PDT 24 611873644 ps
T904 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.245030040 Jul 26 05:45:06 PM PDT 24 Jul 26 05:45:10 PM PDT 24 2712493564 ps
T905 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.538002317 Jul 26 05:44:48 PM PDT 24 Jul 26 05:44:50 PM PDT 24 571833652 ps
T906 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3492546356 Jul 26 05:45:05 PM PDT 24 Jul 26 05:45:07 PM PDT 24 481811311 ps
T907 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3420802949 Jul 26 05:44:57 PM PDT 24 Jul 26 05:45:10 PM PDT 24 15332316196 ps
T908 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1131204067 Jul 26 05:44:59 PM PDT 24 Jul 26 05:45:03 PM PDT 24 3925012169 ps
T909 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3645635149 Jul 26 05:45:09 PM PDT 24 Jul 26 05:45:11 PM PDT 24 513375936 ps
T910 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3358922801 Jul 26 05:44:57 PM PDT 24 Jul 26 05:45:01 PM PDT 24 590595892 ps
T911 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2613557640 Jul 26 05:45:08 PM PDT 24 Jul 26 05:45:09 PM PDT 24 318952620 ps
T912 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2957591441 Jul 26 05:45:03 PM PDT 24 Jul 26 05:45:04 PM PDT 24 453769859 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1503594611 Jul 26 05:44:45 PM PDT 24 Jul 26 05:44:47 PM PDT 24 530501439 ps
T914 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3187221448 Jul 26 05:45:03 PM PDT 24 Jul 26 05:45:05 PM PDT 24 587820502 ps
T335 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1889945950 Jul 26 05:45:07 PM PDT 24 Jul 26 05:45:10 PM PDT 24 8727000520 ps
T915 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3926296808 Jul 26 05:44:57 PM PDT 24 Jul 26 05:45:00 PM PDT 24 450280348 ps
T916 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3034312946 Jul 26 05:44:59 PM PDT 24 Jul 26 05:45:00 PM PDT 24 330304149 ps
T917 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.69023093 Jul 26 05:44:47 PM PDT 24 Jul 26 05:45:05 PM PDT 24 26414534527 ps
T918 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1230657117 Jul 26 05:44:52 PM PDT 24 Jul 26 05:44:53 PM PDT 24 432043216 ps
T919 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3766100415 Jul 26 05:44:47 PM PDT 24 Jul 26 05:44:59 PM PDT 24 7922904563 ps
T920 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2127993893 Jul 26 05:45:04 PM PDT 24 Jul 26 05:45:18 PM PDT 24 8551685179 ps

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3001891445
Short name T6
Test name
Test status
Simulation time 104320619057 ps
CPU time 402.07 seconds
Started Jul 26 06:53:06 PM PDT 24
Finished Jul 26 06:59:48 PM PDT 24
Peak memory 217252 kb
Host smart-542a3ad4-3b1c-491e-92e3-afe1ac1ad3b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001891445 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3001891445
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.803350611
Short name T41
Test name
Test status
Simulation time 353834367290 ps
CPU time 184.1 seconds
Started Jul 26 06:49:28 PM PDT 24
Finished Jul 26 06:52:33 PM PDT 24
Peak memory 201152 kb
Host smart-530b28ce-e831-4059-b56d-d18ec34648d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803350611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.803350611
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2100718650
Short name T14
Test name
Test status
Simulation time 137389402581 ps
CPU time 171.5 seconds
Started Jul 26 06:52:15 PM PDT 24
Finished Jul 26 06:55:06 PM PDT 24
Peak memory 210052 kb
Host smart-64415ff2-0cc8-48fb-a3c5-c98429d3e9f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100718650 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2100718650
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1715265223
Short name T5
Test name
Test status
Simulation time 487034587055 ps
CPU time 929.89 seconds
Started Jul 26 06:52:22 PM PDT 24
Finished Jul 26 07:07:52 PM PDT 24
Peak memory 201128 kb
Host smart-0985786e-9ce4-4654-822a-27785eb4eae2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715265223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1715265223
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1097999354
Short name T80
Test name
Test status
Simulation time 681659403562 ps
CPU time 298.88 seconds
Started Jul 26 06:54:32 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 201148 kb
Host smart-13b11809-7561-40e0-a85a-8977560b3c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097999354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1097999354
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.427697425
Short name T77
Test name
Test status
Simulation time 574599522719 ps
CPU time 1240.48 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 07:10:38 PM PDT 24
Peak memory 201056 kb
Host smart-816e0140-bd27-4371-b33f-aaaa4263837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427697425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.427697425
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2068905588
Short name T10
Test name
Test status
Simulation time 487818569137 ps
CPU time 1159.5 seconds
Started Jul 26 06:55:17 PM PDT 24
Finished Jul 26 07:14:37 PM PDT 24
Peak memory 201220 kb
Host smart-7e9eee99-33e8-4cda-a175-803fa2073efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068905588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2068905588
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3995312262
Short name T257
Test name
Test status
Simulation time 262017008479 ps
CPU time 257.9 seconds
Started Jul 26 06:50:09 PM PDT 24
Finished Jul 26 06:54:27 PM PDT 24
Peak memory 209836 kb
Host smart-328ac19a-8cd3-4aa9-8c75-f80c4c6b6d69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995312262 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3995312262
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1927458279
Short name T187
Test name
Test status
Simulation time 496968767033 ps
CPU time 223.86 seconds
Started Jul 26 06:56:02 PM PDT 24
Finished Jul 26 06:59:46 PM PDT 24
Peak memory 201124 kb
Host smart-11cc8ba7-44ca-4a94-b762-c2f59937c62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927458279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1927458279
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2543107355
Short name T145
Test name
Test status
Simulation time 515136392038 ps
CPU time 227.89 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 06:53:44 PM PDT 24
Peak memory 201180 kb
Host smart-ca9a60a6-868b-43c7-94e8-8f09b559b66d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543107355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2543107355
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2619276590
Short name T164
Test name
Test status
Simulation time 506232269188 ps
CPU time 227.34 seconds
Started Jul 26 06:55:34 PM PDT 24
Finished Jul 26 06:59:21 PM PDT 24
Peak memory 201148 kb
Host smart-13d1e952-6f12-4fb1-8026-3973944c25f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619276590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2619276590
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2882137248
Short name T57
Test name
Test status
Simulation time 7594166177 ps
CPU time 6.58 seconds
Started Jul 26 06:49:47 PM PDT 24
Finished Jul 26 06:49:54 PM PDT 24
Peak memory 217944 kb
Host smart-710b8dab-c03b-4967-85f0-c0d2d58ab3cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882137248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2882137248
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1027174807
Short name T143
Test name
Test status
Simulation time 506839753117 ps
CPU time 274.24 seconds
Started Jul 26 06:51:37 PM PDT 24
Finished Jul 26 06:56:12 PM PDT 24
Peak memory 201156 kb
Host smart-47c7657e-1516-4f32-9f19-495c5403c911
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027174807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1027174807
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1859331596
Short name T60
Test name
Test status
Simulation time 472121866 ps
CPU time 1.8 seconds
Started Jul 26 05:45:02 PM PDT 24
Finished Jul 26 05:45:04 PM PDT 24
Peak memory 210424 kb
Host smart-788c9eb1-7266-4df4-b8d7-9f0264be35f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859331596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1859331596
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2166264081
Short name T141
Test name
Test status
Simulation time 481112898567 ps
CPU time 60.19 seconds
Started Jul 26 06:55:17 PM PDT 24
Finished Jul 26 06:56:17 PM PDT 24
Peak memory 201248 kb
Host smart-050a97fc-cb15-4a0e-9b2e-e324165de603
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166264081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2166264081
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.104741476
Short name T45
Test name
Test status
Simulation time 602373980382 ps
CPU time 1670.73 seconds
Started Jul 26 06:49:46 PM PDT 24
Finished Jul 26 07:17:37 PM PDT 24
Peak memory 201608 kb
Host smart-f8cb9750-21ec-4ac8-9c11-002f70da6de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104741476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.104741476
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2197542969
Short name T49
Test name
Test status
Simulation time 411557685 ps
CPU time 1.72 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:08 PM PDT 24
Peak memory 201456 kb
Host smart-8dc371ef-921a-4aff-b8be-7aa932c15e22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197542969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2197542969
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.527141932
Short name T12
Test name
Test status
Simulation time 499948288178 ps
CPU time 547.37 seconds
Started Jul 26 06:50:31 PM PDT 24
Finished Jul 26 06:59:38 PM PDT 24
Peak memory 201168 kb
Host smart-a6091828-6135-4329-9edf-fb8fc16fc0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527141932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.527141932
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3288456484
Short name T38
Test name
Test status
Simulation time 46002423523 ps
CPU time 75.38 seconds
Started Jul 26 06:51:03 PM PDT 24
Finished Jul 26 06:52:18 PM PDT 24
Peak memory 209560 kb
Host smart-8cc2edf3-836f-49ef-8c50-f0055801cb4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288456484 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3288456484
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.787414358
Short name T7
Test name
Test status
Simulation time 1490432886272 ps
CPU time 1229.73 seconds
Started Jul 26 06:49:36 PM PDT 24
Finished Jul 26 07:10:06 PM PDT 24
Peak memory 201580 kb
Host smart-f9551a24-5af5-4e22-aa65-789eefc25846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787414358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.787414358
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3359232100
Short name T239
Test name
Test status
Simulation time 588841970492 ps
CPU time 1367.09 seconds
Started Jul 26 06:53:08 PM PDT 24
Finished Jul 26 07:15:55 PM PDT 24
Peak memory 201124 kb
Host smart-d242228e-86cf-4fff-ae4d-42bb8d1ad160
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359232100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3359232100
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2210153613
Short name T155
Test name
Test status
Simulation time 531569870450 ps
CPU time 296.22 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:54:55 PM PDT 24
Peak memory 201172 kb
Host smart-176bbf1c-eab3-4d07-99b0-a046154c1834
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210153613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2210153613
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1029788149
Short name T178
Test name
Test status
Simulation time 508650424119 ps
CPU time 300.94 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:54:59 PM PDT 24
Peak memory 201176 kb
Host smart-17903858-366f-4bb1-8cb3-6fc24e448b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029788149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1029788149
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3886466891
Short name T91
Test name
Test status
Simulation time 540133901807 ps
CPU time 1022.27 seconds
Started Jul 26 06:56:09 PM PDT 24
Finished Jul 26 07:13:12 PM PDT 24
Peak memory 201168 kb
Host smart-97f0c488-d741-4e96-b821-8106cf658368
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886466891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3886466891
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2163930717
Short name T266
Test name
Test status
Simulation time 517071588562 ps
CPU time 646.69 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 07:06:03 PM PDT 24
Peak memory 201168 kb
Host smart-4d0f2614-3396-4a85-b41b-89e438d44791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163930717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2163930717
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2143590874
Short name T149
Test name
Test status
Simulation time 516468359306 ps
CPU time 591.57 seconds
Started Jul 26 06:55:03 PM PDT 24
Finished Jul 26 07:04:54 PM PDT 24
Peak memory 201416 kb
Host smart-2c2e5d43-45cd-4ef7-8bbd-3136d5fbd4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143590874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2143590874
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3107521723
Short name T279
Test name
Test status
Simulation time 370974561349 ps
CPU time 180.95 seconds
Started Jul 26 06:50:15 PM PDT 24
Finished Jul 26 06:53:16 PM PDT 24
Peak memory 201176 kb
Host smart-5bdab501-9f64-4723-8864-468262c353fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107521723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3107521723
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.588495899
Short name T72
Test name
Test status
Simulation time 8688538305 ps
CPU time 7.18 seconds
Started Jul 26 05:44:56 PM PDT 24
Finished Jul 26 05:45:04 PM PDT 24
Peak memory 201800 kb
Host smart-280c4a94-8cb7-47eb-bf03-bd58cbc523df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588495899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.588495899
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.153305751
Short name T357
Test name
Test status
Simulation time 495000304 ps
CPU time 1.81 seconds
Started Jul 26 06:49:27 PM PDT 24
Finished Jul 26 06:49:29 PM PDT 24
Peak memory 200952 kb
Host smart-1d0d43f2-ad67-4dbd-88b5-c78f436d6a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153305751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.153305751
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3867067600
Short name T35
Test name
Test status
Simulation time 500577335721 ps
CPU time 292.81 seconds
Started Jul 26 06:50:16 PM PDT 24
Finished Jul 26 06:55:09 PM PDT 24
Peak memory 201136 kb
Host smart-dd93ca4a-7523-4729-a6a8-2567d05ea292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867067600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3867067600
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1761917495
Short name T232
Test name
Test status
Simulation time 374908580589 ps
CPU time 289.74 seconds
Started Jul 26 06:51:37 PM PDT 24
Finished Jul 26 06:56:27 PM PDT 24
Peak memory 201152 kb
Host smart-5e410fff-ecd4-496b-8278-25dade001446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761917495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1761917495
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2002056645
Short name T260
Test name
Test status
Simulation time 345192990586 ps
CPU time 660.93 seconds
Started Jul 26 06:50:09 PM PDT 24
Finished Jul 26 07:01:10 PM PDT 24
Peak memory 201140 kb
Host smart-52baefa4-036f-4b4c-b4c8-d64c18c66731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002056645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2002056645
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.401895366
Short name T251
Test name
Test status
Simulation time 491814041765 ps
CPU time 1230.36 seconds
Started Jul 26 06:50:19 PM PDT 24
Finished Jul 26 07:10:50 PM PDT 24
Peak memory 201164 kb
Host smart-1e88ddfa-cff3-4e72-b442-a66e780eeded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401895366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.401895366
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2518374030
Short name T215
Test name
Test status
Simulation time 664372415335 ps
CPU time 131.55 seconds
Started Jul 26 06:50:34 PM PDT 24
Finished Jul 26 06:52:46 PM PDT 24
Peak memory 200876 kb
Host smart-0922ccf4-3012-43e9-9a61-00b80282a89a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518374030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2518374030
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3866199358
Short name T112
Test name
Test status
Simulation time 1080611950 ps
CPU time 4.36 seconds
Started Jul 26 05:45:13 PM PDT 24
Finished Jul 26 05:45:17 PM PDT 24
Peak memory 201700 kb
Host smart-4e646e0b-24de-497d-ab9a-5deab60c5e47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866199358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3866199358
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.473571489
Short name T147
Test name
Test status
Simulation time 328888954952 ps
CPU time 208.39 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 06:58:44 PM PDT 24
Peak memory 201252 kb
Host smart-08395361-7121-4e2c-b80c-34dff73e63f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473571489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.473571489
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2066281227
Short name T161
Test name
Test status
Simulation time 490403565860 ps
CPU time 1149.59 seconds
Started Jul 26 06:56:02 PM PDT 24
Finished Jul 26 07:15:12 PM PDT 24
Peak memory 201168 kb
Host smart-8ce380c6-2307-443f-a8b6-ff1f92a0e666
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066281227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2066281227
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3645887416
Short name T317
Test name
Test status
Simulation time 492131882597 ps
CPU time 1040.92 seconds
Started Jul 26 06:54:05 PM PDT 24
Finished Jul 26 07:11:26 PM PDT 24
Peak memory 201184 kb
Host smart-86edf36b-b87b-46e9-95cb-8ac0df6a03b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645887416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3645887416
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3827691193
Short name T70
Test name
Test status
Simulation time 709267228 ps
CPU time 2.25 seconds
Started Jul 26 05:45:00 PM PDT 24
Finished Jul 26 05:45:02 PM PDT 24
Peak memory 218148 kb
Host smart-81e0eb8b-4281-4463-bd60-7c3d07dd1c45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827691193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3827691193
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2402981949
Short name T281
Test name
Test status
Simulation time 655041008679 ps
CPU time 392.21 seconds
Started Jul 26 06:49:22 PM PDT 24
Finished Jul 26 06:55:55 PM PDT 24
Peak memory 201200 kb
Host smart-002bc5f8-ba5b-4005-bfb9-9123d318cacd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402981949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2402981949
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3325530307
Short name T263
Test name
Test status
Simulation time 169000650198 ps
CPU time 347.1 seconds
Started Jul 26 06:51:12 PM PDT 24
Finished Jul 26 06:56:59 PM PDT 24
Peak memory 210020 kb
Host smart-0faadef2-7ecc-4ca7-855c-a6597ca3d386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325530307 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3325530307
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1006733996
Short name T258
Test name
Test status
Simulation time 461916247038 ps
CPU time 1158.95 seconds
Started Jul 26 06:50:50 PM PDT 24
Finished Jul 26 07:10:09 PM PDT 24
Peak memory 201232 kb
Host smart-10866c08-324b-44e1-8534-60b65b349d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006733996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1006733996
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1964991986
Short name T230
Test name
Test status
Simulation time 194564434211 ps
CPU time 168.69 seconds
Started Jul 26 06:55:45 PM PDT 24
Finished Jul 26 06:58:33 PM PDT 24
Peak memory 209892 kb
Host smart-64fa6c64-b11e-48f0-a7d6-7c77857b4182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964991986 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1964991986
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3473129964
Short name T180
Test name
Test status
Simulation time 499094040383 ps
CPU time 312.63 seconds
Started Jul 26 06:56:10 PM PDT 24
Finished Jul 26 07:01:23 PM PDT 24
Peak memory 201136 kb
Host smart-8cc73dc7-fada-4ed5-a78a-2a7776b76f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473129964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3473129964
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2581861664
Short name T217
Test name
Test status
Simulation time 505067597229 ps
CPU time 216.66 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:53:36 PM PDT 24
Peak memory 201160 kb
Host smart-ffc49d51-2d83-48f7-af44-84b6d5ee83c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581861664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2581861664
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.622674836
Short name T276
Test name
Test status
Simulation time 358116421010 ps
CPU time 594.23 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:59:53 PM PDT 24
Peak memory 201216 kb
Host smart-fee085d2-29d1-4d94-bc9e-e5273bf978f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622674836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.622674836
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3906061388
Short name T177
Test name
Test status
Simulation time 374035469888 ps
CPU time 78.69 seconds
Started Jul 26 06:51:03 PM PDT 24
Finished Jul 26 06:52:22 PM PDT 24
Peak memory 201244 kb
Host smart-58224b3f-49fa-4c22-bc45-992300815005
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906061388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3906061388
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2790224432
Short name T37
Test name
Test status
Simulation time 592824528866 ps
CPU time 612.52 seconds
Started Jul 26 06:51:36 PM PDT 24
Finished Jul 26 07:01:49 PM PDT 24
Peak memory 209876 kb
Host smart-2a6e9ddc-fc5e-413b-b2a1-6159acd5d585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790224432 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2790224432
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1229949043
Short name T51
Test name
Test status
Simulation time 345331663447 ps
CPU time 202.01 seconds
Started Jul 26 06:54:05 PM PDT 24
Finished Jul 26 06:57:28 PM PDT 24
Peak memory 201164 kb
Host smart-831033d2-0e44-45b6-8259-ca3fb53749a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229949043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1229949043
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2050200572
Short name T169
Test name
Test status
Simulation time 485928190141 ps
CPU time 134.69 seconds
Started Jul 26 06:55:44 PM PDT 24
Finished Jul 26 06:57:59 PM PDT 24
Peak memory 201148 kb
Host smart-998e2af8-8601-45e4-b3a7-c197a6560c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050200572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2050200572
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1509083489
Short name T327
Test name
Test status
Simulation time 490096187198 ps
CPU time 658.82 seconds
Started Jul 26 06:49:19 PM PDT 24
Finished Jul 26 07:00:18 PM PDT 24
Peak memory 201144 kb
Host smart-ef970dad-dfa8-4e13-9877-7975babf055d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509083489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1509083489
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3984502039
Short name T254
Test name
Test status
Simulation time 156382457837 ps
CPU time 145.31 seconds
Started Jul 26 06:50:30 PM PDT 24
Finished Jul 26 06:52:55 PM PDT 24
Peak memory 209568 kb
Host smart-115929ab-9e24-4799-af29-5ab5411493c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984502039 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3984502039
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2408883074
Short name T218
Test name
Test status
Simulation time 183772947762 ps
CPU time 404.73 seconds
Started Jul 26 06:50:35 PM PDT 24
Finished Jul 26 06:57:20 PM PDT 24
Peak memory 201208 kb
Host smart-180c38cb-1e7d-4e4f-9ed8-17a840d80562
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408883074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2408883074
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2705816969
Short name T302
Test name
Test status
Simulation time 329710881052 ps
CPU time 190.95 seconds
Started Jul 26 06:49:26 PM PDT 24
Finished Jul 26 06:52:37 PM PDT 24
Peak memory 201224 kb
Host smart-c4318c49-70bf-4740-8c25-de2cf1753fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705816969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2705816969
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.4115022063
Short name T200
Test name
Test status
Simulation time 101082714045 ps
CPU time 532.81 seconds
Started Jul 26 06:54:11 PM PDT 24
Finished Jul 26 07:03:04 PM PDT 24
Peak memory 201600 kb
Host smart-1e45ac45-a5f8-45b8-b761-065cc7e2ab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115022063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.4115022063
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3096465056
Short name T170
Test name
Test status
Simulation time 559201532179 ps
CPU time 160.2 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:52:40 PM PDT 24
Peak memory 201168 kb
Host smart-ffc3a243-65b5-4b7e-957f-63c07edc6b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096465056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3096465056
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2383206145
Short name T249
Test name
Test status
Simulation time 419630043620 ps
CPU time 996.65 seconds
Started Jul 26 06:50:54 PM PDT 24
Finished Jul 26 07:07:31 PM PDT 24
Peak memory 201188 kb
Host smart-fa4e6421-b77d-46a4-baa6-c65ee1278591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383206145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2383206145
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2441099845
Short name T235
Test name
Test status
Simulation time 547063178778 ps
CPU time 1277.12 seconds
Started Jul 26 06:51:27 PM PDT 24
Finished Jul 26 07:12:44 PM PDT 24
Peak memory 201112 kb
Host smart-720a6f22-369a-4018-986b-9f4ae8ada0b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441099845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2441099845
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.99959583
Short name T308
Test name
Test status
Simulation time 235063975435 ps
CPU time 344.79 seconds
Started Jul 26 06:52:12 PM PDT 24
Finished Jul 26 06:57:57 PM PDT 24
Peak memory 209832 kb
Host smart-72a0e16d-f14c-4392-943c-632b8c1d8cba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99959583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.99959583
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2536974629
Short name T314
Test name
Test status
Simulation time 485649280832 ps
CPU time 485.67 seconds
Started Jul 26 06:52:31 PM PDT 24
Finished Jul 26 07:00:37 PM PDT 24
Peak memory 201248 kb
Host smart-cc636607-acd5-4af5-b4f7-ab1ecee9212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536974629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2536974629
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2577993435
Short name T306
Test name
Test status
Simulation time 168931210633 ps
CPU time 104.91 seconds
Started Jul 26 06:54:21 PM PDT 24
Finished Jul 26 06:56:06 PM PDT 24
Peak memory 201216 kb
Host smart-89613d08-68c3-429d-8bc9-9dad2dcd9fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577993435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2577993435
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1925517649
Short name T220
Test name
Test status
Simulation time 159924819259 ps
CPU time 91.44 seconds
Started Jul 26 06:54:37 PM PDT 24
Finished Jul 26 06:56:08 PM PDT 24
Peak memory 201132 kb
Host smart-5c43647e-9a66-4ef4-b90d-0433af78968a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925517649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1925517649
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.896436778
Short name T309
Test name
Test status
Simulation time 326264180040 ps
CPU time 744.04 seconds
Started Jul 26 06:55:34 PM PDT 24
Finished Jul 26 07:07:58 PM PDT 24
Peak memory 201228 kb
Host smart-c60e9b68-defa-47d0-8529-2457d9413dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896436778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.896436778
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1946268892
Short name T216
Test name
Test status
Simulation time 373464396649 ps
CPU time 869.3 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 07:04:27 PM PDT 24
Peak memory 201060 kb
Host smart-5d85c566-86a0-4ba3-9cb8-b7595e0dee42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946268892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1946268892
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1889945950
Short name T335
Test name
Test status
Simulation time 8727000520 ps
CPU time 3.72 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201744 kb
Host smart-c5e720dd-d75e-4790-a558-c88926e6cdca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889945950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1889945950
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.394501348
Short name T233
Test name
Test status
Simulation time 166575003764 ps
CPU time 410.61 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:56:51 PM PDT 24
Peak memory 201232 kb
Host smart-b407394d-ffd0-4687-b818-bb3fb1a1b445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394501348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.394501348
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.626100993
Short name T300
Test name
Test status
Simulation time 530894020008 ps
CPU time 1197.21 seconds
Started Jul 26 06:50:06 PM PDT 24
Finished Jul 26 07:10:04 PM PDT 24
Peak memory 201156 kb
Host smart-1493e4df-8513-4992-a213-7b7e16e3ad7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626100993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.626100993
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.330944929
Short name T283
Test name
Test status
Simulation time 267049720805 ps
CPU time 416.4 seconds
Started Jul 26 06:50:34 PM PDT 24
Finished Jul 26 06:57:31 PM PDT 24
Peak memory 200900 kb
Host smart-e8c24a91-4572-4a8c-983a-4ed1a717e90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330944929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.330944929
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3777919550
Short name T337
Test name
Test status
Simulation time 595736803085 ps
CPU time 2011.29 seconds
Started Jul 26 06:51:13 PM PDT 24
Finished Jul 26 07:24:45 PM PDT 24
Peak memory 209872 kb
Host smart-d90e1b78-0f1e-4572-9c3e-0bf35cf3e779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777919550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3777919550
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2878561552
Short name T267
Test name
Test status
Simulation time 335704660801 ps
CPU time 200.27 seconds
Started Jul 26 06:53:19 PM PDT 24
Finished Jul 26 06:56:39 PM PDT 24
Peak memory 201152 kb
Host smart-82b7e227-fb5b-439d-adbf-d7fe0480a35b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878561552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2878561552
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1165815866
Short name T193
Test name
Test status
Simulation time 523063020147 ps
CPU time 208.33 seconds
Started Jul 26 06:53:29 PM PDT 24
Finished Jul 26 06:56:57 PM PDT 24
Peak memory 201140 kb
Host smart-8e285903-9ca3-4afc-922e-535cf2341069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165815866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1165815866
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2087957972
Short name T207
Test name
Test status
Simulation time 602230051537 ps
CPU time 666.1 seconds
Started Jul 26 06:53:45 PM PDT 24
Finished Jul 26 07:04:51 PM PDT 24
Peak memory 201596 kb
Host smart-fff3c828-ffac-4d81-af97-3ad472d90b3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087957972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2087957972
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1924479980
Short name T303
Test name
Test status
Simulation time 334568615714 ps
CPU time 259.27 seconds
Started Jul 26 06:54:04 PM PDT 24
Finished Jul 26 06:58:24 PM PDT 24
Peak memory 201208 kb
Host smart-2d5a0870-a8fc-4abf-b471-aba03614222d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924479980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1924479980
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.713867725
Short name T225
Test name
Test status
Simulation time 489639802155 ps
CPU time 153.66 seconds
Started Jul 26 06:54:05 PM PDT 24
Finished Jul 26 06:56:39 PM PDT 24
Peak memory 201176 kb
Host smart-d894b994-98e8-4382-b6fd-c23ccb5d440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713867725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.713867725
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1252490778
Short name T250
Test name
Test status
Simulation time 488708645822 ps
CPU time 1163.28 seconds
Started Jul 26 06:54:28 PM PDT 24
Finished Jul 26 07:13:52 PM PDT 24
Peak memory 201180 kb
Host smart-0ebd8870-6a60-45ab-9cf8-f61a3c753486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252490778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1252490778
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.323050635
Short name T290
Test name
Test status
Simulation time 498335730422 ps
CPU time 1059.71 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 07:07:38 PM PDT 24
Peak memory 201196 kb
Host smart-8b2de9f9-d2d0-4232-b1b4-bb907ca9ab38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323050635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.323050635
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3702543805
Short name T214
Test name
Test status
Simulation time 148529227627 ps
CPU time 708.52 seconds
Started Jul 26 06:50:01 PM PDT 24
Finished Jul 26 07:01:50 PM PDT 24
Peak memory 201616 kb
Host smart-7d413b7c-c6cc-4a0d-a5a4-424dfbb3a798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702543805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3702543805
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1476209550
Short name T222
Test name
Test status
Simulation time 498395693096 ps
CPU time 1209.77 seconds
Started Jul 26 06:50:07 PM PDT 24
Finished Jul 26 07:10:17 PM PDT 24
Peak memory 201184 kb
Host smart-b4e5a2ef-9dc4-4d20-844d-0f76548d1e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476209550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1476209550
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2277678548
Short name T324
Test name
Test status
Simulation time 333479211778 ps
CPU time 153.41 seconds
Started Jul 26 06:50:24 PM PDT 24
Finished Jul 26 06:52:57 PM PDT 24
Peak memory 201200 kb
Host smart-971cb38f-580e-4ac4-9c59-552a9e83177c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277678548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2277678548
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1364242754
Short name T171
Test name
Test status
Simulation time 538390477898 ps
CPU time 106.82 seconds
Started Jul 26 06:49:29 PM PDT 24
Finished Jul 26 06:51:16 PM PDT 24
Peak memory 201196 kb
Host smart-e54bc84c-07b7-4e78-8311-6c029fa9379e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364242754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1364242754
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2923854413
Short name T246
Test name
Test status
Simulation time 189553592575 ps
CPU time 231.78 seconds
Started Jul 26 06:51:26 PM PDT 24
Finished Jul 26 06:55:18 PM PDT 24
Peak memory 201176 kb
Host smart-c561bd47-5b31-4ae0-a143-276ead346fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923854413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2923854413
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.648377394
Short name T318
Test name
Test status
Simulation time 490008324607 ps
CPU time 1069.05 seconds
Started Jul 26 06:51:37 PM PDT 24
Finished Jul 26 07:09:26 PM PDT 24
Peak memory 201268 kb
Host smart-2c173010-84ba-46d2-b977-cbb4d1c867fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648377394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.648377394
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.4070281852
Short name T307
Test name
Test status
Simulation time 514369419914 ps
CPU time 1151.72 seconds
Started Jul 26 06:52:41 PM PDT 24
Finished Jul 26 07:11:53 PM PDT 24
Peak memory 201188 kb
Host smart-1a5604e7-b473-4841-8d38-37f0e1020293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070281852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.4070281852
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.105090400
Short name T202
Test name
Test status
Simulation time 138540315767 ps
CPU time 678.47 seconds
Started Jul 26 06:55:10 PM PDT 24
Finished Jul 26 07:06:28 PM PDT 24
Peak memory 201680 kb
Host smart-54255bd6-6b06-4e92-b3e6-1958bb11798c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105090400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.105090400
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1250848452
Short name T236
Test name
Test status
Simulation time 173647251071 ps
CPU time 214.35 seconds
Started Jul 26 06:55:44 PM PDT 24
Finished Jul 26 06:59:18 PM PDT 24
Peak memory 201136 kb
Host smart-4287563d-c3d5-460a-9883-11333a3deba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250848452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1250848452
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1437546338
Short name T342
Test name
Test status
Simulation time 72769956964 ps
CPU time 262.63 seconds
Started Jul 26 06:55:47 PM PDT 24
Finished Jul 26 07:00:10 PM PDT 24
Peak memory 201560 kb
Host smart-c8f000dd-dea8-470d-810d-10694ee91194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437546338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1437546338
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.890954933
Short name T210
Test name
Test status
Simulation time 543998280688 ps
CPU time 1797.94 seconds
Started Jul 26 06:55:47 PM PDT 24
Finished Jul 26 07:25:45 PM PDT 24
Peak memory 218048 kb
Host smart-952882fe-0db6-4505-a007-3a1e24422285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890954933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
890954933
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.157719945
Short name T326
Test name
Test status
Simulation time 552612841053 ps
CPU time 1289.28 seconds
Started Jul 26 06:49:59 PM PDT 24
Finished Jul 26 07:11:28 PM PDT 24
Peak memory 201160 kb
Host smart-ff983878-0a02-4884-a91d-b8ab104353b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157719945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.157719945
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3582949627
Short name T322
Test name
Test status
Simulation time 259468296427 ps
CPU time 172.78 seconds
Started Jul 26 06:49:59 PM PDT 24
Finished Jul 26 06:52:52 PM PDT 24
Peak memory 209948 kb
Host smart-40899e59-3bcb-4da6-b395-1ea99b5e2dc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582949627 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3582949627
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.69023093
Short name T917
Test name
Test status
Simulation time 26414534527 ps
CPU time 18.13 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:45:05 PM PDT 24
Peak memory 201636 kb
Host smart-ff0101a3-8712-4009-881d-23e7ac4cdc6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69023093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_ba
sh.69023093
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.495611213
Short name T131
Test name
Test status
Simulation time 1080609176 ps
CPU time 2.23 seconds
Started Jul 26 05:44:56 PM PDT 24
Finished Jul 26 05:44:59 PM PDT 24
Peak memory 201456 kb
Host smart-bf565bf6-a722-4808-8d2e-d55bdf4b482b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495611213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.495611213
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.156695691
Short name T858
Test name
Test status
Simulation time 506328486 ps
CPU time 1.65 seconds
Started Jul 26 05:44:49 PM PDT 24
Finished Jul 26 05:44:51 PM PDT 24
Peak memory 201508 kb
Host smart-2cbe0370-0652-4e12-853c-7683d38d1697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156695691 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.156695691
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1819563339
Short name T872
Test name
Test status
Simulation time 383841533 ps
CPU time 0.91 seconds
Started Jul 26 05:44:42 PM PDT 24
Finished Jul 26 05:44:43 PM PDT 24
Peak memory 201424 kb
Host smart-5f85a8a6-8864-4824-9051-8eddd9d163de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819563339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1819563339
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2259641149
Short name T834
Test name
Test status
Simulation time 320499713 ps
CPU time 1.36 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:08 PM PDT 24
Peak memory 201404 kb
Host smart-0c7c7b50-c84e-4ef8-8da2-86bdbb44c35b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259641149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2259641149
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2048296300
Short name T869
Test name
Test status
Simulation time 4147810418 ps
CPU time 6.12 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:57 PM PDT 24
Peak memory 201776 kb
Host smart-31bce9da-acac-4a5d-99f2-954b874ab5c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048296300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2048296300
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.457366314
Short name T881
Test name
Test status
Simulation time 877070748 ps
CPU time 2.66 seconds
Started Jul 26 05:44:43 PM PDT 24
Finished Jul 26 05:44:46 PM PDT 24
Peak memory 217684 kb
Host smart-166448d5-dc4a-4095-b6ca-d4dce1580491
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457366314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.457366314
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3766100415
Short name T919
Test name
Test status
Simulation time 7922904563 ps
CPU time 11.77 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:59 PM PDT 24
Peak memory 201768 kb
Host smart-62c96955-1252-4fc2-ad6d-0f558aa05030
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766100415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3766100415
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3173175618
Short name T111
Test name
Test status
Simulation time 792819767 ps
CPU time 2.42 seconds
Started Jul 26 05:45:01 PM PDT 24
Finished Jul 26 05:45:04 PM PDT 24
Peak memory 201748 kb
Host smart-d50d83b5-593a-45e9-b381-2cb11995f91e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173175618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3173175618
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2957947293
Short name T851
Test name
Test status
Simulation time 27107662714 ps
CPU time 108.47 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:46:36 PM PDT 24
Peak memory 201680 kb
Host smart-4616e97e-209e-488f-bf5d-934dcf16832d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957947293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2957947293
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3361365024
Short name T823
Test name
Test status
Simulation time 915635251 ps
CPU time 1.88 seconds
Started Jul 26 05:45:00 PM PDT 24
Finished Jul 26 05:45:02 PM PDT 24
Peak memory 201384 kb
Host smart-0a8578af-2d98-41f8-9287-98551075cddf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361365024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3361365024
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3952003263
Short name T842
Test name
Test status
Simulation time 505085149 ps
CPU time 1.95 seconds
Started Jul 26 05:44:57 PM PDT 24
Finished Jul 26 05:44:59 PM PDT 24
Peak memory 201604 kb
Host smart-4927701e-bb9f-4be3-bd99-faded0fde25a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952003263 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3952003263
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.943091971
Short name T115
Test name
Test status
Simulation time 534230213 ps
CPU time 1.98 seconds
Started Jul 26 05:44:52 PM PDT 24
Finished Jul 26 05:44:54 PM PDT 24
Peak memory 201456 kb
Host smart-8404cd53-a20b-4b2a-a690-ae8862f4be2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943091971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.943091971
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1503594611
Short name T913
Test name
Test status
Simulation time 530501439 ps
CPU time 1.25 seconds
Started Jul 26 05:44:45 PM PDT 24
Finished Jul 26 05:44:47 PM PDT 24
Peak memory 201484 kb
Host smart-fb47b689-4b24-46d8-ba1f-35ad9338240b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503594611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1503594611
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.134289015
Short name T127
Test name
Test status
Simulation time 2471121103 ps
CPU time 5.83 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:45:00 PM PDT 24
Peak memory 201508 kb
Host smart-78425a53-0816-4fca-9d0b-3e76d09df78f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134289015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.134289015
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2314402352
Short name T888
Test name
Test status
Simulation time 358476816 ps
CPU time 3.08 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:44:58 PM PDT 24
Peak memory 201776 kb
Host smart-3c3e8d93-72b1-4726-9bfc-4a4e9d77d6d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314402352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2314402352
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1326224155
Short name T860
Test name
Test status
Simulation time 4569813092 ps
CPU time 3.93 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:57 PM PDT 24
Peak memory 201700 kb
Host smart-8f707640-c751-45f2-ac68-bc8bc85656e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326224155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1326224155
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1672877835
Short name T861
Test name
Test status
Simulation time 434138170 ps
CPU time 1.05 seconds
Started Jul 26 05:44:56 PM PDT 24
Finished Jul 26 05:44:57 PM PDT 24
Peak memory 201544 kb
Host smart-3e896c01-9440-40c0-90b5-7d8affcd1fa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672877835 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1672877835
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1517462955
Short name T109
Test name
Test status
Simulation time 387299049 ps
CPU time 0.97 seconds
Started Jul 26 05:44:52 PM PDT 24
Finished Jul 26 05:44:54 PM PDT 24
Peak memory 201332 kb
Host smart-edce027c-1fe1-430e-b7fb-1c1cf85b9a69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517462955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1517462955
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.171687577
Short name T811
Test name
Test status
Simulation time 376382078 ps
CPU time 0.74 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:07 PM PDT 24
Peak memory 201416 kb
Host smart-faf55fef-95c2-4b13-9b8a-6076b75058a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171687577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.171687577
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1188098269
Short name T813
Test name
Test status
Simulation time 2328101666 ps
CPU time 1.98 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:09 PM PDT 24
Peak memory 201620 kb
Host smart-068ca992-35e2-4088-a766-f084e2522576
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188098269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1188098269
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2238296146
Short name T873
Test name
Test status
Simulation time 342114000 ps
CPU time 1.2 seconds
Started Jul 26 05:45:08 PM PDT 24
Finished Jul 26 05:45:09 PM PDT 24
Peak memory 201548 kb
Host smart-69f37e63-3867-4e93-9b2f-6b70dd5a2242
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238296146 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2238296146
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1197636324
Short name T113
Test name
Test status
Simulation time 378016659 ps
CPU time 1.12 seconds
Started Jul 26 05:44:52 PM PDT 24
Finished Jul 26 05:44:53 PM PDT 24
Peak memory 201364 kb
Host smart-273668f0-5726-4c28-a28c-31ccea16947d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197636324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1197636324
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2095623256
Short name T827
Test name
Test status
Simulation time 374287606 ps
CPU time 0.86 seconds
Started Jul 26 05:44:57 PM PDT 24
Finished Jul 26 05:44:58 PM PDT 24
Peak memory 201464 kb
Host smart-5208df8e-8b81-4b72-b02e-ed9518e20fbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095623256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2095623256
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.245030040
Short name T904
Test name
Test status
Simulation time 2712493564 ps
CPU time 3.88 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201552 kb
Host smart-cb05e804-27bd-4ed6-8da2-f407ce16f41c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245030040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.245030040
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3765967103
Short name T68
Test name
Test status
Simulation time 502732838 ps
CPU time 2.15 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:53 PM PDT 24
Peak memory 201484 kb
Host smart-61b837b0-cc4e-4ccc-8729-84417fd43f34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765967103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3765967103
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2127993893
Short name T920
Test name
Test status
Simulation time 8551685179 ps
CPU time 13.49 seconds
Started Jul 26 05:45:04 PM PDT 24
Finished Jul 26 05:45:18 PM PDT 24
Peak memory 201776 kb
Host smart-75ee4f33-69e0-4184-adbf-af70512c56da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127993893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2127993893
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.776443317
Short name T86
Test name
Test status
Simulation time 398763462 ps
CPU time 1.36 seconds
Started Jul 26 05:45:01 PM PDT 24
Finished Jul 26 05:45:03 PM PDT 24
Peak memory 201544 kb
Host smart-6a592457-1a7e-424c-accb-d91e1b5755f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776443317 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.776443317
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.538002317
Short name T905
Test name
Test status
Simulation time 571833652 ps
CPU time 1.12 seconds
Started Jul 26 05:44:48 PM PDT 24
Finished Jul 26 05:44:50 PM PDT 24
Peak memory 201412 kb
Host smart-42e24558-4e49-479a-9a5b-cf3f7f24e531
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538002317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.538002317
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.766084359
Short name T808
Test name
Test status
Simulation time 525417092 ps
CPU time 0.86 seconds
Started Jul 26 05:45:03 PM PDT 24
Finished Jul 26 05:45:04 PM PDT 24
Peak memory 201420 kb
Host smart-46194444-fd8e-4a7c-8f32-ad6557f7a194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766084359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.766084359
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2976579134
Short name T859
Test name
Test status
Simulation time 2679081005 ps
CPU time 3.97 seconds
Started Jul 26 05:45:08 PM PDT 24
Finished Jul 26 05:45:13 PM PDT 24
Peak memory 201512 kb
Host smart-d7f070c8-519e-4072-b554-4874941f0832
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976579134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2976579134
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4256474161
Short name T857
Test name
Test status
Simulation time 381508197 ps
CPU time 2.19 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:09 PM PDT 24
Peak memory 201776 kb
Host smart-5dad1f7e-2df4-4528-8a91-c209239402a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256474161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4256474161
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2645846291
Short name T334
Test name
Test status
Simulation time 4560568140 ps
CPU time 6.72 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:13 PM PDT 24
Peak memory 201772 kb
Host smart-38595b49-7720-4acc-aa6d-912d929a0cd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645846291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2645846291
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2542655449
Short name T892
Test name
Test status
Simulation time 579809037 ps
CPU time 1.35 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:07 PM PDT 24
Peak memory 210708 kb
Host smart-181b1260-e189-43b7-ae8b-8be0ca5ead3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542655449 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2542655449
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.205910989
Short name T874
Test name
Test status
Simulation time 502346475 ps
CPU time 0.95 seconds
Started Jul 26 05:45:02 PM PDT 24
Finished Jul 26 05:45:03 PM PDT 24
Peak memory 201420 kb
Host smart-eb537879-220d-48a6-bb74-eda8566e1e46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205910989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.205910989
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4108146684
Short name T836
Test name
Test status
Simulation time 422259772 ps
CPU time 1.54 seconds
Started Jul 26 05:44:52 PM PDT 24
Finished Jul 26 05:44:58 PM PDT 24
Peak memory 201468 kb
Host smart-edd9aa0c-6d2d-4322-b1de-0fe0dc8d5b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108146684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.4108146684
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2050367716
Short name T832
Test name
Test status
Simulation time 4793879728 ps
CPU time 8.08 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:45:02 PM PDT 24
Peak memory 201776 kb
Host smart-e31254e5-9c1f-403e-9e43-5aa1b25fee13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050367716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2050367716
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1604561840
Short name T854
Test name
Test status
Simulation time 557346069 ps
CPU time 4.18 seconds
Started Jul 26 05:45:00 PM PDT 24
Finished Jul 26 05:45:04 PM PDT 24
Peak memory 201724 kb
Host smart-dde7adc2-da4f-4fc9-8511-87aeea349a32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604561840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1604561840
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1482195807
Short name T894
Test name
Test status
Simulation time 4375323988 ps
CPU time 12.2 seconds
Started Jul 26 05:45:01 PM PDT 24
Finished Jul 26 05:45:13 PM PDT 24
Peak memory 201740 kb
Host smart-20eb2565-f4cc-4456-993d-3c5bb48956f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482195807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1482195807
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3269396472
Short name T882
Test name
Test status
Simulation time 417977257 ps
CPU time 2.01 seconds
Started Jul 26 05:45:00 PM PDT 24
Finished Jul 26 05:45:03 PM PDT 24
Peak memory 201508 kb
Host smart-2aec75cc-4542-47b3-b3c8-d640b15dc7a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269396472 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3269396472
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.716277042
Short name T840
Test name
Test status
Simulation time 427637862 ps
CPU time 1.66 seconds
Started Jul 26 05:45:00 PM PDT 24
Finished Jul 26 05:45:02 PM PDT 24
Peak memory 201452 kb
Host smart-7e43ebd0-3bfd-4c3b-a05b-6f2103e73b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716277042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.716277042
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1917356267
Short name T850
Test name
Test status
Simulation time 357661476 ps
CPU time 0.81 seconds
Started Jul 26 05:45:08 PM PDT 24
Finished Jul 26 05:45:08 PM PDT 24
Peak memory 201412 kb
Host smart-9ef2580c-bea1-4a17-9edb-854ef42f0827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917356267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1917356267
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2312263075
Short name T826
Test name
Test status
Simulation time 4507021157 ps
CPU time 3.03 seconds
Started Jul 26 05:45:03 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 201684 kb
Host smart-8b5c0556-5ee4-4ac2-ba86-ba95856a6280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312263075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2312263075
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1545864584
Short name T64
Test name
Test status
Simulation time 441526098 ps
CPU time 1.87 seconds
Started Jul 26 05:44:50 PM PDT 24
Finished Jul 26 05:44:53 PM PDT 24
Peak memory 201812 kb
Host smart-cb6c30ba-49b5-4082-9b9e-f3dc1bad5719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545864584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1545864584
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2445820007
Short name T852
Test name
Test status
Simulation time 8396049911 ps
CPU time 20.18 seconds
Started Jul 26 05:44:55 PM PDT 24
Finished Jul 26 05:45:16 PM PDT 24
Peak memory 201708 kb
Host smart-bdc6a677-49fa-40d1-8a0b-05abf8f96c10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445820007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2445820007
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.578637529
Short name T846
Test name
Test status
Simulation time 596347625 ps
CPU time 1.76 seconds
Started Jul 26 05:44:55 PM PDT 24
Finished Jul 26 05:44:57 PM PDT 24
Peak memory 201528 kb
Host smart-e4e1fe29-a506-413e-ab93-985c8a41aa3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578637529 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.578637529
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.377263601
Short name T900
Test name
Test status
Simulation time 477200798 ps
CPU time 1.77 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:11 PM PDT 24
Peak memory 201384 kb
Host smart-88da36e9-f2dc-4a26-a897-bc2f404ef84e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377263601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.377263601
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1972893569
Short name T816
Test name
Test status
Simulation time 411400255 ps
CPU time 0.86 seconds
Started Jul 26 05:44:55 PM PDT 24
Finished Jul 26 05:44:56 PM PDT 24
Peak memory 201396 kb
Host smart-5dfa4aa7-109b-487d-acd8-d09a05df7465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972893569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1972893569
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.641008424
Short name T822
Test name
Test status
Simulation time 2562550960 ps
CPU time 2.96 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201548 kb
Host smart-74725911-65c9-4e3d-9282-771eea5b471f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641008424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.641008424
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3926296808
Short name T915
Test name
Test status
Simulation time 450280348 ps
CPU time 1.99 seconds
Started Jul 26 05:44:57 PM PDT 24
Finished Jul 26 05:45:00 PM PDT 24
Peak memory 209932 kb
Host smart-ab7dc1dc-0df0-49e6-9893-38ea0e947611
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926296808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3926296808
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3609404972
Short name T336
Test name
Test status
Simulation time 7643832279 ps
CPU time 20.81 seconds
Started Jul 26 05:45:11 PM PDT 24
Finished Jul 26 05:45:32 PM PDT 24
Peak memory 201824 kb
Host smart-0e7cc7ec-69d1-4df0-8019-c4a9e4a0de04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609404972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3609404972
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2378052650
Short name T97
Test name
Test status
Simulation time 546695356 ps
CPU time 1.3 seconds
Started Jul 26 05:45:10 PM PDT 24
Finished Jul 26 05:45:12 PM PDT 24
Peak memory 201644 kb
Host smart-0aab2010-09f2-4f48-941b-e6f7c979b065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378052650 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2378052650
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.662774699
Short name T896
Test name
Test status
Simulation time 438454969 ps
CPU time 1.68 seconds
Started Jul 26 05:45:04 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 201428 kb
Host smart-3fe32d20-9fcf-45ab-84f6-0c448c2d57bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662774699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.662774699
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1786532087
Short name T879
Test name
Test status
Simulation time 2699900074 ps
CPU time 1.47 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:09 PM PDT 24
Peak memory 201556 kb
Host smart-5e69b082-7290-4fa3-807d-577154334103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786532087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1786532087
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1783612780
Short name T853
Test name
Test status
Simulation time 484088916 ps
CPU time 2.68 seconds
Started Jul 26 05:45:02 PM PDT 24
Finished Jul 26 05:45:05 PM PDT 24
Peak memory 201736 kb
Host smart-6e694d9e-bcce-468c-a0c5-e9734340f9a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783612780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1783612780
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1881155501
Short name T67
Test name
Test status
Simulation time 4462124873 ps
CPU time 12.53 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:20 PM PDT 24
Peak memory 201788 kb
Host smart-c0ff9ac3-cc6a-46d9-a868-7c2d87046b98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881155501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1881155501
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.874758052
Short name T848
Test name
Test status
Simulation time 413186204 ps
CPU time 1.4 seconds
Started Jul 26 05:45:08 PM PDT 24
Finished Jul 26 05:45:09 PM PDT 24
Peak memory 201552 kb
Host smart-63c20e48-c16b-4d26-9341-7f994756f7d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874758052 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.874758052
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1781671226
Short name T122
Test name
Test status
Simulation time 361741784 ps
CPU time 1.75 seconds
Started Jul 26 05:45:03 PM PDT 24
Finished Jul 26 05:45:05 PM PDT 24
Peak memory 201384 kb
Host smart-8867f794-3de9-48aa-944e-ee95f7b232eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781671226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1781671226
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4020906836
Short name T855
Test name
Test status
Simulation time 295691559 ps
CPU time 0.92 seconds
Started Jul 26 05:45:16 PM PDT 24
Finished Jul 26 05:45:17 PM PDT 24
Peak memory 201436 kb
Host smart-a898748d-03d5-4327-883e-c67c5bfb84af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020906836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4020906836
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3726298070
Short name T897
Test name
Test status
Simulation time 2974844540 ps
CPU time 6.56 seconds
Started Jul 26 05:45:08 PM PDT 24
Finished Jul 26 05:45:15 PM PDT 24
Peak memory 201768 kb
Host smart-bc3d0d61-5307-4823-8e43-3d71ff0fea80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726298070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3726298070
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2713573762
Short name T893
Test name
Test status
Simulation time 502370335 ps
CPU time 3.25 seconds
Started Jul 26 05:45:03 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 201776 kb
Host smart-4fd757e7-cae9-4d5d-a70b-1f755d0036e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713573762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2713573762
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2635919346
Short name T71
Test name
Test status
Simulation time 8819770469 ps
CPU time 13.39 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:19 PM PDT 24
Peak memory 201680 kb
Host smart-7b815175-65b7-4334-9c19-f3afe92f3c60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635919346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2635919346
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2586264520
Short name T898
Test name
Test status
Simulation time 540369236 ps
CPU time 1.33 seconds
Started Jul 26 05:45:05 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 201552 kb
Host smart-e3f74e4b-981e-4f02-9418-9236c57e7325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586264520 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2586264520
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3582258032
Short name T863
Test name
Test status
Simulation time 474103044 ps
CPU time 1.05 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201424 kb
Host smart-71c4de99-7c79-4d9b-939d-3857cfcf0f3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582258032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3582258032
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4217464536
Short name T899
Test name
Test status
Simulation time 366099856 ps
CPU time 0.82 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201440 kb
Host smart-8eed52ec-eadf-4b7c-b65f-a18337f05147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217464536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4217464536
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3309544584
Short name T50
Test name
Test status
Simulation time 3706671397 ps
CPU time 14.17 seconds
Started Jul 26 05:45:08 PM PDT 24
Finished Jul 26 05:45:22 PM PDT 24
Peak memory 201728 kb
Host smart-af260abe-2f00-49e8-aac3-d5687bcee1f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309544584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3309544584
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.44464903
Short name T875
Test name
Test status
Simulation time 389388176 ps
CPU time 1.93 seconds
Started Jul 26 05:44:58 PM PDT 24
Finished Jul 26 05:45:01 PM PDT 24
Peak memory 201740 kb
Host smart-070e4273-645b-448f-b30b-a3cf877b3f08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44464903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.44464903
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3183389662
Short name T885
Test name
Test status
Simulation time 8476283690 ps
CPU time 6.43 seconds
Started Jul 26 05:45:02 PM PDT 24
Finished Jul 26 05:45:08 PM PDT 24
Peak memory 201780 kb
Host smart-4725d1f7-1ccd-4ea5-b5fd-66204eb93611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183389662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3183389662
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1165790072
Short name T838
Test name
Test status
Simulation time 653096268 ps
CPU time 1.4 seconds
Started Jul 26 05:45:03 PM PDT 24
Finished Jul 26 05:45:05 PM PDT 24
Peak memory 201560 kb
Host smart-07fb009c-dd56-4d4a-8393-6ca666eb6d8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165790072 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1165790072
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3548535929
Short name T110
Test name
Test status
Simulation time 519015703 ps
CPU time 0.98 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201448 kb
Host smart-44de409e-3516-422b-a955-7ef72295da5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548535929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3548535929
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.403665685
Short name T829
Test name
Test status
Simulation time 310629758 ps
CPU time 1.36 seconds
Started Jul 26 05:45:15 PM PDT 24
Finished Jul 26 05:45:17 PM PDT 24
Peak memory 201436 kb
Host smart-dd2f7bb8-6dc2-4053-afcc-d536e10ad957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403665685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.403665685
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.79966086
Short name T856
Test name
Test status
Simulation time 2043404265 ps
CPU time 1.71 seconds
Started Jul 26 05:45:08 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201472 kb
Host smart-9096612a-021e-4608-b3ad-3842194bf01b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79966086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ct
rl_same_csr_outstanding.79966086
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3167166444
Short name T866
Test name
Test status
Simulation time 545307970 ps
CPU time 2.43 seconds
Started Jul 26 05:45:08 PM PDT 24
Finished Jul 26 05:45:11 PM PDT 24
Peak memory 218068 kb
Host smart-d4928b9d-23af-4c50-8940-cdebe8807de8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167166444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3167166444
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3806980104
Short name T53
Test name
Test status
Simulation time 4633295991 ps
CPU time 12.05 seconds
Started Jul 26 05:45:10 PM PDT 24
Finished Jul 26 05:45:22 PM PDT 24
Peak memory 201764 kb
Host smart-e8fdac8d-cc42-4bf0-bc32-710e20ebad11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806980104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3806980104
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3071100769
Short name T815
Test name
Test status
Simulation time 700393111 ps
CPU time 3.53 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201636 kb
Host smart-92c1bd08-41a7-473d-a797-cd40bc80348a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071100769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3071100769
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2325955372
Short name T124
Test name
Test status
Simulation time 6804207911 ps
CPU time 17.45 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201732 kb
Host smart-a3b8b572-9d3d-45fe-b4ed-36cf8d9a4a2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325955372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2325955372
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.936530071
Short name T114
Test name
Test status
Simulation time 1271001236 ps
CPU time 2.22 seconds
Started Jul 26 05:44:50 PM PDT 24
Finished Jul 26 05:44:52 PM PDT 24
Peak memory 201440 kb
Host smart-0633f21b-69c8-4bb4-9ab6-5d6fda5c5768
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936530071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.936530071
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1667274624
Short name T903
Test name
Test status
Simulation time 611873644 ps
CPU time 2.29 seconds
Started Jul 26 05:44:50 PM PDT 24
Finished Jul 26 05:44:53 PM PDT 24
Peak memory 201508 kb
Host smart-cbab4647-9afd-4139-9e5f-af5419997f14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667274624 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1667274624
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3558973600
Short name T119
Test name
Test status
Simulation time 427423004 ps
CPU time 1.13 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 201444 kb
Host smart-a2056f0b-41b9-403f-b902-b3d48f35cbfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558973600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3558973600
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2713507522
Short name T864
Test name
Test status
Simulation time 434523940 ps
CPU time 1.58 seconds
Started Jul 26 05:44:46 PM PDT 24
Finished Jul 26 05:44:48 PM PDT 24
Peak memory 201432 kb
Host smart-6355b18a-a0ac-4b38-947a-9dbc5e4251fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713507522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2713507522
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.875072309
Short name T877
Test name
Test status
Simulation time 2920871551 ps
CPU time 7.18 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:45:01 PM PDT 24
Peak memory 201508 kb
Host smart-d554a111-17a5-4056-a141-f201b1bdb01b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875072309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.875072309
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3732662117
Short name T62
Test name
Test status
Simulation time 720642153 ps
CPU time 1.9 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:44:56 PM PDT 24
Peak memory 201804 kb
Host smart-29f4e4c2-2d8b-4b0e-95f9-b422b09d80b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732662117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3732662117
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1552116429
Short name T839
Test name
Test status
Simulation time 9046862140 ps
CPU time 23.57 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:45:17 PM PDT 24
Peak memory 201808 kb
Host smart-6b9e3ff3-71c4-4c36-84a3-e4b1f0a9c8a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552116429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1552116429
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3691035950
Short name T843
Test name
Test status
Simulation time 474730472 ps
CPU time 1.11 seconds
Started Jul 26 05:45:04 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 201412 kb
Host smart-2d0f57b5-54b3-4de3-b0d7-69fc2721dcf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691035950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3691035950
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.885045558
Short name T886
Test name
Test status
Simulation time 499321295 ps
CPU time 1.78 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:09 PM PDT 24
Peak memory 201312 kb
Host smart-9a65e710-9c73-4875-8700-d2bdaa3fd591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885045558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.885045558
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3671736780
Short name T887
Test name
Test status
Simulation time 532779876 ps
CPU time 1.59 seconds
Started Jul 26 05:45:01 PM PDT 24
Finished Jul 26 05:45:03 PM PDT 24
Peak memory 201420 kb
Host smart-5d3f0542-e4e7-4e64-bf7b-511005370e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671736780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3671736780
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4085608508
Short name T828
Test name
Test status
Simulation time 369417037 ps
CPU time 1.42 seconds
Started Jul 26 05:45:10 PM PDT 24
Finished Jul 26 05:45:12 PM PDT 24
Peak memory 201440 kb
Host smart-b94021a3-8983-44c9-a5b9-75d0581c6ed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085608508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.4085608508
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3563300101
Short name T835
Test name
Test status
Simulation time 333933956 ps
CPU time 1.37 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201420 kb
Host smart-4e2b5fff-3388-4c37-9858-32b936e61dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563300101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3563300101
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3296879114
Short name T845
Test name
Test status
Simulation time 300355995 ps
CPU time 0.78 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:07 PM PDT 24
Peak memory 201420 kb
Host smart-9432b814-56f8-43c5-9222-4fb7f50972a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296879114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3296879114
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.271352549
Short name T817
Test name
Test status
Simulation time 482548620 ps
CPU time 1.71 seconds
Started Jul 26 05:45:04 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 201440 kb
Host smart-fb4ad8c7-bd40-4425-a8b2-b93b6128b97c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271352549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.271352549
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2208963989
Short name T831
Test name
Test status
Simulation time 367819201 ps
CPU time 0.88 seconds
Started Jul 26 05:45:10 PM PDT 24
Finished Jul 26 05:45:11 PM PDT 24
Peak memory 201516 kb
Host smart-99473923-81bd-4bb3-8bf0-bdd510b4fb97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208963989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2208963989
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2052920367
Short name T805
Test name
Test status
Simulation time 310058694 ps
CPU time 0.76 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:08 PM PDT 24
Peak memory 201364 kb
Host smart-b1af86f4-5699-4258-b4e7-b8713bba278a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052920367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2052920367
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3089482176
Short name T814
Test name
Test status
Simulation time 535789871 ps
CPU time 0.93 seconds
Started Jul 26 05:45:02 PM PDT 24
Finished Jul 26 05:45:03 PM PDT 24
Peak memory 201500 kb
Host smart-e2e97a34-53b8-4aa5-a257-c5dc18f79128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089482176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3089482176
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4017552103
Short name T123
Test name
Test status
Simulation time 1043492500 ps
CPU time 3.26 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:57 PM PDT 24
Peak memory 201612 kb
Host smart-cef7c482-e5e0-4b1d-8471-f5fcb0bacf45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017552103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.4017552103
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.67463025
Short name T868
Test name
Test status
Simulation time 26258694317 ps
CPU time 99.23 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:46:33 PM PDT 24
Peak memory 201652 kb
Host smart-6b2e83b9-b871-4687-9eb0-330889dfc54b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67463025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_ba
sh.67463025
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1317180627
Short name T837
Test name
Test status
Simulation time 1238272993 ps
CPU time 3.65 seconds
Started Jul 26 05:44:50 PM PDT 24
Finished Jul 26 05:44:54 PM PDT 24
Peak memory 201388 kb
Host smart-95fbea6a-b7be-4715-b68e-c3e4ce3ee19d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317180627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1317180627
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4151741064
Short name T824
Test name
Test status
Simulation time 327290929 ps
CPU time 1.28 seconds
Started Jul 26 05:44:47 PM PDT 24
Finished Jul 26 05:44:49 PM PDT 24
Peak memory 201632 kb
Host smart-2dbf696f-dfe0-48ce-b346-06c5f8a76946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151741064 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4151741064
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4251123801
Short name T129
Test name
Test status
Simulation time 535834742 ps
CPU time 1.02 seconds
Started Jul 26 05:44:52 PM PDT 24
Finished Jul 26 05:44:54 PM PDT 24
Peak memory 201452 kb
Host smart-e407e5c9-3dd1-4efd-a238-97711610f149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251123801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.4251123801
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2800999104
Short name T818
Test name
Test status
Simulation time 433846732 ps
CPU time 0.84 seconds
Started Jul 26 05:44:44 PM PDT 24
Finished Jul 26 05:44:45 PM PDT 24
Peak memory 201412 kb
Host smart-9c152ced-dc00-4ec6-b123-3d7724fc0295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800999104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2800999104
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2965031785
Short name T130
Test name
Test status
Simulation time 2660429273 ps
CPU time 6.08 seconds
Started Jul 26 05:44:57 PM PDT 24
Finished Jul 26 05:45:03 PM PDT 24
Peak memory 201500 kb
Host smart-fc531f70-4e6d-4e24-b6dd-d611065a9b30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965031785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2965031785
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3050596656
Short name T63
Test name
Test status
Simulation time 675726441 ps
CPU time 2.92 seconds
Started Jul 26 05:45:03 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 201768 kb
Host smart-91c995c8-9862-486a-a3b8-acf05f597ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050596656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3050596656
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.973472374
Short name T884
Test name
Test status
Simulation time 9171831406 ps
CPU time 8.52 seconds
Started Jul 26 05:44:48 PM PDT 24
Finished Jul 26 05:44:57 PM PDT 24
Peak memory 201816 kb
Host smart-43fb7aa5-9ff8-4210-a512-49d00c5d7478
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973472374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.973472374
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.643456770
Short name T870
Test name
Test status
Simulation time 345673585 ps
CPU time 1.05 seconds
Started Jul 26 05:45:26 PM PDT 24
Finished Jul 26 05:45:27 PM PDT 24
Peak memory 201456 kb
Host smart-53250844-1dd0-49a2-b9e8-5e7747f29343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643456770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.643456770
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1688222150
Short name T812
Test name
Test status
Simulation time 306222230 ps
CPU time 1.36 seconds
Started Jul 26 05:45:20 PM PDT 24
Finished Jul 26 05:45:22 PM PDT 24
Peak memory 201476 kb
Host smart-c7333a2e-87b1-4618-9b16-15141aa81ca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688222150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1688222150
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2613557640
Short name T911
Test name
Test status
Simulation time 318952620 ps
CPU time 0.86 seconds
Started Jul 26 05:45:08 PM PDT 24
Finished Jul 26 05:45:09 PM PDT 24
Peak memory 201376 kb
Host smart-e95cda2e-a9e9-4e92-8720-956fadc93c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613557640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2613557640
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1926597110
Short name T830
Test name
Test status
Simulation time 424065482 ps
CPU time 1.05 seconds
Started Jul 26 05:45:38 PM PDT 24
Finished Jul 26 05:45:39 PM PDT 24
Peak memory 201424 kb
Host smart-b20a56ed-be7d-4ce3-9b3e-60f518b11657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926597110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1926597110
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.196689698
Short name T889
Test name
Test status
Simulation time 484770023 ps
CPU time 1.75 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:11 PM PDT 24
Peak memory 201436 kb
Host smart-4e316780-0554-40c4-bf86-4436dbf650df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196689698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.196689698
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2239214339
Short name T862
Test name
Test status
Simulation time 334633703 ps
CPU time 1.16 seconds
Started Jul 26 05:45:02 PM PDT 24
Finished Jul 26 05:45:04 PM PDT 24
Peak memory 201412 kb
Host smart-2195e465-d0b4-4f4d-976a-c02a889a6238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239214339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2239214339
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3492546356
Short name T906
Test name
Test status
Simulation time 481811311 ps
CPU time 1.69 seconds
Started Jul 26 05:45:05 PM PDT 24
Finished Jul 26 05:45:07 PM PDT 24
Peak memory 201364 kb
Host smart-8a8dc42a-0ed5-42cb-aafd-153a5753f00b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492546356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3492546356
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3678160334
Short name T819
Test name
Test status
Simulation time 322605852 ps
CPU time 0.98 seconds
Started Jul 26 05:45:05 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 201412 kb
Host smart-1acc119a-572d-4da2-a3b3-ec14629b759e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678160334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3678160334
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.29561313
Short name T867
Test name
Test status
Simulation time 520300072 ps
CPU time 1.77 seconds
Started Jul 26 05:45:05 PM PDT 24
Finished Jul 26 05:45:07 PM PDT 24
Peak memory 201440 kb
Host smart-f752a336-d5ee-44d4-a44b-e10929664751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29561313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.29561313
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1436163845
Short name T880
Test name
Test status
Simulation time 373037276 ps
CPU time 0.87 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201444 kb
Host smart-b727c658-9cd5-41b0-88f0-0f6fefe6121b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436163845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1436163845
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1364352352
Short name T121
Test name
Test status
Simulation time 866905397 ps
CPU time 3.83 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:57 PM PDT 24
Peak memory 201612 kb
Host smart-2b51d58f-77bf-4fb4-bbdc-561ed37ea44a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364352352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1364352352
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3420802949
Short name T907
Test name
Test status
Simulation time 15332316196 ps
CPU time 12.05 seconds
Started Jul 26 05:44:57 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201664 kb
Host smart-efa20ce5-350f-443c-a06e-ab75340b2a04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420802949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3420802949
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2647767013
Short name T120
Test name
Test status
Simulation time 796369008 ps
CPU time 2.45 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:44:57 PM PDT 24
Peak memory 201460 kb
Host smart-939ebf85-029e-48d1-992e-c052d488ea0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647767013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2647767013
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2334774019
Short name T810
Test name
Test status
Simulation time 380970477 ps
CPU time 1.02 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:54 PM PDT 24
Peak memory 201604 kb
Host smart-ac09516e-030c-4b2e-b92c-6d72975cff50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334774019 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2334774019
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1711507917
Short name T118
Test name
Test status
Simulation time 485460438 ps
CPU time 1.84 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:55 PM PDT 24
Peak memory 201484 kb
Host smart-a30e1270-d251-4391-824b-96add4deec49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711507917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1711507917
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4029561849
Short name T820
Test name
Test status
Simulation time 519050204 ps
CPU time 1.21 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:52 PM PDT 24
Peak memory 201368 kb
Host smart-2393abb1-94f9-4353-a402-f4565fc10676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029561849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.4029561849
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2186643268
Short name T47
Test name
Test status
Simulation time 2485699121 ps
CPU time 5.52 seconds
Started Jul 26 05:45:02 PM PDT 24
Finished Jul 26 05:45:08 PM PDT 24
Peak memory 201548 kb
Host smart-77f9fd41-93c6-42e9-8a5a-8b78d6dbc60c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186643268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2186643268
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3187221448
Short name T914
Test name
Test status
Simulation time 587820502 ps
CPU time 2.01 seconds
Started Jul 26 05:45:03 PM PDT 24
Finished Jul 26 05:45:05 PM PDT 24
Peak memory 201748 kb
Host smart-78d3c3cb-eec4-4597-9e9f-d8e0ca39a579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187221448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3187221448
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2485040428
Short name T54
Test name
Test status
Simulation time 4393308376 ps
CPU time 4.09 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:44:58 PM PDT 24
Peak memory 201708 kb
Host smart-79b48d4e-b078-4a0b-b8eb-38cc2883e62c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485040428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2485040428
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3645635149
Short name T909
Test name
Test status
Simulation time 513375936 ps
CPU time 1.8 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:11 PM PDT 24
Peak memory 201476 kb
Host smart-94833a0c-5736-4a9c-9f7b-1743a4b1aaf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645635149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3645635149
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.490404258
Short name T890
Test name
Test status
Simulation time 405997818 ps
CPU time 1.57 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:08 PM PDT 24
Peak memory 201448 kb
Host smart-44074d54-868c-4df0-ae04-c1c911cf870c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490404258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.490404258
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2181461870
Short name T807
Test name
Test status
Simulation time 472766470 ps
CPU time 1.84 seconds
Started Jul 26 05:45:02 PM PDT 24
Finished Jul 26 05:45:04 PM PDT 24
Peak memory 201392 kb
Host smart-80a73df6-b3ef-4e3f-8256-202a7b14fd0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181461870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2181461870
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1760836409
Short name T833
Test name
Test status
Simulation time 384046402 ps
CPU time 1.53 seconds
Started Jul 26 05:45:10 PM PDT 24
Finished Jul 26 05:45:12 PM PDT 24
Peak memory 201436 kb
Host smart-fd489971-1bdb-4b77-9fe8-45aa0101c1d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760836409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1760836409
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2957591441
Short name T912
Test name
Test status
Simulation time 453769859 ps
CPU time 1.61 seconds
Started Jul 26 05:45:03 PM PDT 24
Finished Jul 26 05:45:04 PM PDT 24
Peak memory 201472 kb
Host smart-69f0a00b-fa38-4a83-986d-801f2e6e1702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957591441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2957591441
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2403916351
Short name T809
Test name
Test status
Simulation time 375445136 ps
CPU time 1.5 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:11 PM PDT 24
Peak memory 201440 kb
Host smart-263a207a-16d1-478d-bfca-0953eec8fb2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403916351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2403916351
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.746847086
Short name T849
Test name
Test status
Simulation time 446226136 ps
CPU time 0.93 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:07 PM PDT 24
Peak memory 201416 kb
Host smart-fcc8a843-68a5-40ec-acc0-21322a9adb79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746847086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.746847086
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3095200704
Short name T878
Test name
Test status
Simulation time 442061487 ps
CPU time 1.54 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:11 PM PDT 24
Peak memory 201476 kb
Host smart-43db1b82-f687-459a-8193-6f7920bf20f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095200704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3095200704
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.347976983
Short name T883
Test name
Test status
Simulation time 542151706 ps
CPU time 0.77 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:07 PM PDT 24
Peak memory 201448 kb
Host smart-b0396598-62f7-4b5e-a8dd-e627cff4ac3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347976983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.347976983
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.156143948
Short name T806
Test name
Test status
Simulation time 471428880 ps
CPU time 1.62 seconds
Started Jul 26 05:45:13 PM PDT 24
Finished Jul 26 05:45:14 PM PDT 24
Peak memory 201380 kb
Host smart-a020cae9-9c83-4792-b293-5c118b9d2751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156143948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.156143948
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1572457914
Short name T87
Test name
Test status
Simulation time 329287131 ps
CPU time 1.27 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:44:56 PM PDT 24
Peak memory 201612 kb
Host smart-77fd92a1-2cb7-46a2-b0b1-81aca2088df4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572457914 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1572457914
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3089540141
Short name T117
Test name
Test status
Simulation time 502909081 ps
CPU time 1.9 seconds
Started Jul 26 05:44:54 PM PDT 24
Finished Jul 26 05:44:57 PM PDT 24
Peak memory 201416 kb
Host smart-e3dbe95d-e205-4233-a3ec-39e70097938f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089540141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3089540141
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3034312946
Short name T916
Test name
Test status
Simulation time 330304149 ps
CPU time 1.04 seconds
Started Jul 26 05:44:59 PM PDT 24
Finished Jul 26 05:45:00 PM PDT 24
Peak memory 201408 kb
Host smart-066ce2e6-440e-4cf6-bf50-2724ce457fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034312946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3034312946
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2924260068
Short name T847
Test name
Test status
Simulation time 3304460381 ps
CPU time 4.53 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:44:55 PM PDT 24
Peak memory 201780 kb
Host smart-86df3989-ae6c-4fbd-bf72-31a498bc14c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924260068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2924260068
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2180999703
Short name T865
Test name
Test status
Simulation time 564037063 ps
CPU time 2.56 seconds
Started Jul 26 05:45:03 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 211016 kb
Host smart-035ce74a-fcc8-434c-b2a0-f3f7f3850c20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180999703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2180999703
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3434609278
Short name T52
Test name
Test status
Simulation time 9103891819 ps
CPU time 16.75 seconds
Started Jul 26 05:44:56 PM PDT 24
Finished Jul 26 05:45:13 PM PDT 24
Peak memory 201704 kb
Host smart-cd50e147-978e-4820-983e-32f0219b061d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434609278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3434609278
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1230657117
Short name T918
Test name
Test status
Simulation time 432043216 ps
CPU time 1.3 seconds
Started Jul 26 05:44:52 PM PDT 24
Finished Jul 26 05:44:53 PM PDT 24
Peak memory 201612 kb
Host smart-b75b894c-bc4d-448b-88c1-629afba5ae5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230657117 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1230657117
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3411043205
Short name T126
Test name
Test status
Simulation time 434248113 ps
CPU time 1.84 seconds
Started Jul 26 05:45:04 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 201384 kb
Host smart-ad7f61af-66fa-4c85-a723-12c179acc4b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411043205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3411043205
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1765254697
Short name T895
Test name
Test status
Simulation time 327927065 ps
CPU time 1.34 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:08 PM PDT 24
Peak memory 201384 kb
Host smart-33ec99d0-4b6f-4a74-843a-c14469a214ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765254697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1765254697
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1972483966
Short name T48
Test name
Test status
Simulation time 4788687452 ps
CPU time 16.4 seconds
Started Jul 26 05:44:49 PM PDT 24
Finished Jul 26 05:45:06 PM PDT 24
Peak memory 201780 kb
Host smart-e7306713-66fc-45f7-a6c5-4b9ca4e423bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972483966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1972483966
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.783393251
Short name T61
Test name
Test status
Simulation time 408054042 ps
CPU time 2.27 seconds
Started Jul 26 05:44:57 PM PDT 24
Finished Jul 26 05:45:00 PM PDT 24
Peak memory 201820 kb
Host smart-f14c60ee-427e-445d-b579-48db034ad5f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783393251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.783393251
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1795257392
Short name T841
Test name
Test status
Simulation time 4711933217 ps
CPU time 13.13 seconds
Started Jul 26 05:44:51 PM PDT 24
Finished Jul 26 05:45:04 PM PDT 24
Peak memory 201752 kb
Host smart-3e3ea1d3-3d1d-4fe2-af5a-f997c944d5f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795257392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1795257392
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.526833235
Short name T821
Test name
Test status
Simulation time 439816958 ps
CPU time 1.97 seconds
Started Jul 26 05:45:01 PM PDT 24
Finished Jul 26 05:45:03 PM PDT 24
Peak memory 201588 kb
Host smart-9ea13395-8b24-40bc-abce-12c7d67ab7b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526833235 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.526833235
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2740192113
Short name T128
Test name
Test status
Simulation time 608934713 ps
CPU time 1.17 seconds
Started Jul 26 05:45:01 PM PDT 24
Finished Jul 26 05:45:02 PM PDT 24
Peak memory 201452 kb
Host smart-2c1cde3f-9875-40ce-a169-0ddc8bb9091b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740192113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2740192113
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2386301174
Short name T804
Test name
Test status
Simulation time 364237228 ps
CPU time 0.79 seconds
Started Jul 26 05:45:09 PM PDT 24
Finished Jul 26 05:45:10 PM PDT 24
Peak memory 201316 kb
Host smart-386bf65c-37ad-4dc4-82ff-c2f72d3d991f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386301174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2386301174
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1249528183
Short name T901
Test name
Test status
Simulation time 2912174985 ps
CPU time 1.31 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:08 PM PDT 24
Peak memory 201548 kb
Host smart-0699701e-15af-4e18-b042-1440d417b13c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249528183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1249528183
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3921849258
Short name T891
Test name
Test status
Simulation time 437968807 ps
CPU time 2.82 seconds
Started Jul 26 05:44:53 PM PDT 24
Finished Jul 26 05:44:56 PM PDT 24
Peak memory 218116 kb
Host smart-f1e58dd0-1c2e-47ad-9555-40db79f9dbdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921849258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3921849258
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1131204067
Short name T908
Test name
Test status
Simulation time 3925012169 ps
CPU time 3.69 seconds
Started Jul 26 05:44:59 PM PDT 24
Finished Jul 26 05:45:03 PM PDT 24
Peak memory 201716 kb
Host smart-c7ab8437-89bc-4efc-ba21-28493cb84eb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131204067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1131204067
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1449848071
Short name T69
Test name
Test status
Simulation time 355656389 ps
CPU time 1.71 seconds
Started Jul 26 05:44:57 PM PDT 24
Finished Jul 26 05:44:59 PM PDT 24
Peak memory 201544 kb
Host smart-997611aa-d2e0-44fa-ae4a-83789f82fb12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449848071 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1449848071
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.812280442
Short name T125
Test name
Test status
Simulation time 320485262 ps
CPU time 1.47 seconds
Started Jul 26 05:44:58 PM PDT 24
Finished Jul 26 05:44:59 PM PDT 24
Peak memory 201420 kb
Host smart-ddf205e7-046d-4e93-acfa-f411a46a28e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812280442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.812280442
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.466265274
Short name T902
Test name
Test status
Simulation time 498569121 ps
CPU time 1.36 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:08 PM PDT 24
Peak memory 201408 kb
Host smart-29eb1c4e-f233-4046-8372-d7bda4648812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466265274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.466265274
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.591562364
Short name T844
Test name
Test status
Simulation time 4462947542 ps
CPU time 9.82 seconds
Started Jul 26 05:45:06 PM PDT 24
Finished Jul 26 05:45:16 PM PDT 24
Peak memory 201784 kb
Host smart-f0391a5d-210a-4b65-8177-6a24e6c22acf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591562364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.591562364
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3358922801
Short name T910
Test name
Test status
Simulation time 590595892 ps
CPU time 3.9 seconds
Started Jul 26 05:44:57 PM PDT 24
Finished Jul 26 05:45:01 PM PDT 24
Peak memory 218072 kb
Host smart-e4fff41d-8ce2-4765-a4ce-7fcd6e1e5a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358922801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3358922801
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.517153302
Short name T871
Test name
Test status
Simulation time 533831000 ps
CPU time 1.64 seconds
Started Jul 26 05:44:48 PM PDT 24
Finished Jul 26 05:44:50 PM PDT 24
Peak memory 201592 kb
Host smart-e567fccc-70c5-4e9f-b928-eeb2783169d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517153302 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.517153302
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4273120850
Short name T116
Test name
Test status
Simulation time 566668790 ps
CPU time 1.46 seconds
Started Jul 26 05:45:02 PM PDT 24
Finished Jul 26 05:45:04 PM PDT 24
Peak memory 201428 kb
Host smart-6573e36c-1871-4c79-a1f1-d1b59b0f0b7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273120850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4273120850
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1173157570
Short name T876
Test name
Test status
Simulation time 358937406 ps
CPU time 0.7 seconds
Started Jul 26 05:45:01 PM PDT 24
Finished Jul 26 05:45:02 PM PDT 24
Peak memory 201448 kb
Host smart-d6fe5170-1d2d-425e-b290-ee5a986feea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173157570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1173157570
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.633212894
Short name T825
Test name
Test status
Simulation time 2055655139 ps
CPU time 8.38 seconds
Started Jul 26 05:45:07 PM PDT 24
Finished Jul 26 05:45:15 PM PDT 24
Peak memory 201492 kb
Host smart-cc18b09e-7a21-45ce-96a5-a0dc82a4619b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633212894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.633212894
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2013857822
Short name T66
Test name
Test status
Simulation time 5862285429 ps
CPU time 3.12 seconds
Started Jul 26 05:44:56 PM PDT 24
Finished Jul 26 05:45:00 PM PDT 24
Peak memory 201704 kb
Host smart-9921bd8c-346b-41d9-bfab-55f06a584bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013857822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2013857822
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2293719344
Short name T769
Test name
Test status
Simulation time 291042090 ps
CPU time 1.34 seconds
Started Jul 26 06:49:21 PM PDT 24
Finished Jul 26 06:49:22 PM PDT 24
Peak memory 200964 kb
Host smart-1f2f4d5e-c787-4c5a-a9e6-092c3dff5c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293719344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2293719344
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1343475738
Short name T275
Test name
Test status
Simulation time 361771475147 ps
CPU time 204.15 seconds
Started Jul 26 06:49:22 PM PDT 24
Finished Jul 26 06:52:46 PM PDT 24
Peak memory 201124 kb
Host smart-914f0458-8261-4202-a3d1-4a8663975f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343475738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1343475738
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2811000750
Short name T163
Test name
Test status
Simulation time 334804684674 ps
CPU time 146.33 seconds
Started Jul 26 06:49:19 PM PDT 24
Finished Jul 26 06:51:46 PM PDT 24
Peak memory 201172 kb
Host smart-c3cb0f38-02ef-496e-b050-0bd8282e4894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811000750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2811000750
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.674870162
Short name T616
Test name
Test status
Simulation time 160624207481 ps
CPU time 103.41 seconds
Started Jul 26 06:49:20 PM PDT 24
Finished Jul 26 06:51:03 PM PDT 24
Peak memory 201208 kb
Host smart-658b5632-f927-4a0c-a249-7661d27bf793
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=674870162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.674870162
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2821608537
Short name T186
Test name
Test status
Simulation time 483888762704 ps
CPU time 201.76 seconds
Started Jul 26 06:49:21 PM PDT 24
Finished Jul 26 06:52:43 PM PDT 24
Peak memory 201220 kb
Host smart-108abbfe-5cea-4a33-96da-cae2f47ee8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821608537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2821608537
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2046889324
Short name T548
Test name
Test status
Simulation time 323126731769 ps
CPU time 382.61 seconds
Started Jul 26 06:49:22 PM PDT 24
Finished Jul 26 06:55:45 PM PDT 24
Peak memory 201124 kb
Host smart-d1a1a9ae-b7dc-4ba8-a153-3ab29ae64160
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046889324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2046889324
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3744181612
Short name T328
Test name
Test status
Simulation time 181621413705 ps
CPU time 390.72 seconds
Started Jul 26 06:49:19 PM PDT 24
Finished Jul 26 06:55:50 PM PDT 24
Peak memory 201208 kb
Host smart-16c43c72-e5fc-4edf-b85c-979085614207
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744181612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3744181612
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2064983005
Short name T457
Test name
Test status
Simulation time 380048792622 ps
CPU time 829.39 seconds
Started Jul 26 06:49:21 PM PDT 24
Finished Jul 26 07:03:10 PM PDT 24
Peak memory 201148 kb
Host smart-9d929c00-dae5-48ca-9c05-e9e5263529dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064983005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2064983005
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3872434926
Short name T204
Test name
Test status
Simulation time 78262421462 ps
CPU time 318.8 seconds
Started Jul 26 06:49:18 PM PDT 24
Finished Jul 26 06:54:37 PM PDT 24
Peak memory 201700 kb
Host smart-42c3d40e-f27b-438b-a739-da10e6efb3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872434926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3872434926
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.710948470
Short name T641
Test name
Test status
Simulation time 43316154759 ps
CPU time 109.51 seconds
Started Jul 26 06:49:20 PM PDT 24
Finished Jul 26 06:51:10 PM PDT 24
Peak memory 200976 kb
Host smart-bb0ab12d-7498-49db-83e2-d66cb14d8214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710948470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.710948470
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4289282635
Short name T451
Test name
Test status
Simulation time 4351700164 ps
CPU time 3.2 seconds
Started Jul 26 06:49:18 PM PDT 24
Finished Jul 26 06:49:21 PM PDT 24
Peak memory 201000 kb
Host smart-ecf4d05e-cf6d-4658-b1c3-a6a33bca9b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289282635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4289282635
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2449285719
Short name T59
Test name
Test status
Simulation time 4203369397 ps
CPU time 10.52 seconds
Started Jul 26 06:49:20 PM PDT 24
Finished Jul 26 06:49:31 PM PDT 24
Peak memory 216800 kb
Host smart-18fc3a4d-665a-4e6f-b1d6-27377de2c0d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449285719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2449285719
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3552721291
Short name T103
Test name
Test status
Simulation time 5744548097 ps
CPU time 7.85 seconds
Started Jul 26 06:49:20 PM PDT 24
Finished Jul 26 06:49:28 PM PDT 24
Peak memory 201024 kb
Host smart-691224ee-9ba3-4248-951d-ed063a202117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552721291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3552721291
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.881617839
Short name T476
Test name
Test status
Simulation time 169888416082 ps
CPU time 267.69 seconds
Started Jul 26 06:49:22 PM PDT 24
Finished Jul 26 06:53:50 PM PDT 24
Peak memory 201176 kb
Host smart-d82e0595-c137-4c3a-8914-8025ae017c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881617839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.881617839
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2392958509
Short name T22
Test name
Test status
Simulation time 32959467211 ps
CPU time 25.46 seconds
Started Jul 26 06:49:22 PM PDT 24
Finished Jul 26 06:49:48 PM PDT 24
Peak memory 201304 kb
Host smart-0a19b99c-805d-418d-aebe-be8f471798a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392958509 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2392958509
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.4119093474
Short name T319
Test name
Test status
Simulation time 348761388564 ps
CPU time 785.08 seconds
Started Jul 26 06:49:18 PM PDT 24
Finished Jul 26 07:02:23 PM PDT 24
Peak memory 201120 kb
Host smart-d63459be-6a50-49ff-aa8e-ccc4e2b024da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119093474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.4119093474
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.163962957
Short name T610
Test name
Test status
Simulation time 499171077800 ps
CPU time 339.59 seconds
Started Jul 26 06:49:19 PM PDT 24
Finished Jul 26 06:54:59 PM PDT 24
Peak memory 201188 kb
Host smart-ec4ee8b7-90d2-493e-baf6-84f9156c1dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163962957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.163962957
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.175055186
Short name T588
Test name
Test status
Simulation time 167079883637 ps
CPU time 290.15 seconds
Started Jul 26 06:49:21 PM PDT 24
Finished Jul 26 06:54:11 PM PDT 24
Peak memory 201208 kb
Host smart-3f11c8ed-c7c5-4e54-9fe5-5ee5249dcb34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=175055186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.175055186
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.328379372
Short name T297
Test name
Test status
Simulation time 488740398820 ps
CPU time 1084.53 seconds
Started Jul 26 06:49:19 PM PDT 24
Finished Jul 26 07:07:24 PM PDT 24
Peak memory 201168 kb
Host smart-4c019151-f5a0-44dd-9f7b-5564d2573bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328379372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.328379372
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3449341838
Short name T417
Test name
Test status
Simulation time 329125100120 ps
CPU time 701.14 seconds
Started Jul 26 06:49:22 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 201148 kb
Host smart-bf2619d5-001f-4fe7-9b38-b457ed7e3a16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449341838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3449341838
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.4218998099
Short name T295
Test name
Test status
Simulation time 543642025119 ps
CPU time 679.93 seconds
Started Jul 26 06:49:21 PM PDT 24
Finished Jul 26 07:00:42 PM PDT 24
Peak memory 201224 kb
Host smart-27316c84-9e4c-4620-9a52-618515b90ef6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218998099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.4218998099
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2082055734
Short name T518
Test name
Test status
Simulation time 591716553048 ps
CPU time 1453.69 seconds
Started Jul 26 06:49:18 PM PDT 24
Finished Jul 26 07:13:32 PM PDT 24
Peak memory 201176 kb
Host smart-9ce23599-d949-4ac2-b8b6-e45e01ada0e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082055734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2082055734
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2308018549
Short name T209
Test name
Test status
Simulation time 82577332069 ps
CPU time 259.44 seconds
Started Jul 26 06:49:22 PM PDT 24
Finished Jul 26 06:53:41 PM PDT 24
Peak memory 201672 kb
Host smart-a411e0b2-b0af-4b08-836e-443ac569edf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308018549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2308018549
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.394976730
Short name T764
Test name
Test status
Simulation time 45758630752 ps
CPU time 99.12 seconds
Started Jul 26 06:49:18 PM PDT 24
Finished Jul 26 06:50:58 PM PDT 24
Peak memory 200964 kb
Host smart-8054d0c8-248b-49e2-973a-1ff8898799b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394976730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.394976730
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1837913142
Short name T362
Test name
Test status
Simulation time 3108913412 ps
CPU time 4.53 seconds
Started Jul 26 06:49:19 PM PDT 24
Finished Jul 26 06:49:23 PM PDT 24
Peak memory 201040 kb
Host smart-4050e42c-75fc-4297-942d-e13b504aa44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837913142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1837913142
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.303387172
Short name T58
Test name
Test status
Simulation time 4728730142 ps
CPU time 11.71 seconds
Started Jul 26 06:49:27 PM PDT 24
Finished Jul 26 06:49:39 PM PDT 24
Peak memory 216756 kb
Host smart-4ec8b589-bdbd-41db-a09d-9cbc050c5e86
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303387172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.303387172
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1785873739
Short name T725
Test name
Test status
Simulation time 5637077250 ps
CPU time 14.25 seconds
Started Jul 26 06:49:18 PM PDT 24
Finished Jul 26 06:49:33 PM PDT 24
Peak memory 201000 kb
Host smart-3d9c83b0-2b86-49a4-a93f-1dd3483e2f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785873739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1785873739
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1263664773
Short name T191
Test name
Test status
Simulation time 274781756639 ps
CPU time 931.96 seconds
Started Jul 26 06:49:25 PM PDT 24
Finished Jul 26 07:04:57 PM PDT 24
Peak memory 209848 kb
Host smart-9b8512bb-87a9-4fa6-81be-3fda45ba5d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263664773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1263664773
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1853282660
Short name T282
Test name
Test status
Simulation time 122172156321 ps
CPU time 315.17 seconds
Started Jul 26 06:49:29 PM PDT 24
Finished Jul 26 06:54:44 PM PDT 24
Peak memory 217212 kb
Host smart-85611ec9-27d9-4c4d-8b86-50b96210a0cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853282660 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1853282660
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2285917305
Short name T672
Test name
Test status
Simulation time 369031172 ps
CPU time 1.42 seconds
Started Jul 26 06:49:59 PM PDT 24
Finished Jul 26 06:50:00 PM PDT 24
Peak memory 200928 kb
Host smart-b517a230-de38-461f-95ed-f933cdbb5d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285917305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2285917305
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4199523060
Short name T495
Test name
Test status
Simulation time 521908537730 ps
CPU time 444.4 seconds
Started Jul 26 06:49:54 PM PDT 24
Finished Jul 26 06:57:19 PM PDT 24
Peak memory 201164 kb
Host smart-be2b49a7-813d-4c4b-988c-ba58cfa35d37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199523060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4199523060
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2851956561
Short name T551
Test name
Test status
Simulation time 157328630035 ps
CPU time 376.38 seconds
Started Jul 26 06:50:02 PM PDT 24
Finished Jul 26 06:56:19 PM PDT 24
Peak memory 201240 kb
Host smart-03f95aa3-fc40-4d1d-b102-b1925c5792c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851956561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2851956561
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1075468480
Short name T553
Test name
Test status
Simulation time 329942631597 ps
CPU time 163.2 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:52:43 PM PDT 24
Peak memory 201184 kb
Host smart-9d707246-d89a-47da-bacc-41abb1229c4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075468480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1075468480
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2051186850
Short name T385
Test name
Test status
Simulation time 332366937182 ps
CPU time 122.95 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:52:02 PM PDT 24
Peak memory 201208 kb
Host smart-c65266f2-e219-4fe0-b631-e8fe51ff3ee9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051186850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2051186850
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.317223281
Short name T459
Test name
Test status
Simulation time 395313813590 ps
CPU time 471.94 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:57:50 PM PDT 24
Peak memory 201164 kb
Host smart-985919c9-aac5-4e69-988f-d262a6e24c46
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317223281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.317223281
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2612650766
Short name T153
Test name
Test status
Simulation time 28916693878 ps
CPU time 58.66 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:50:59 PM PDT 24
Peak memory 201020 kb
Host smart-53790736-7678-4610-9f81-7f0446ab8975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612650766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2612650766
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1457464499
Short name T397
Test name
Test status
Simulation time 3419498303 ps
CPU time 8.72 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:50:09 PM PDT 24
Peak memory 201068 kb
Host smart-fb0fa48f-5be7-4aff-bac9-0addb6d2b3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457464499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1457464499
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3082998382
Short name T735
Test name
Test status
Simulation time 6029747740 ps
CPU time 7.38 seconds
Started Jul 26 06:50:03 PM PDT 24
Finished Jul 26 06:50:10 PM PDT 24
Peak memory 201032 kb
Host smart-8f2feed6-80e7-4548-ac27-db53e536ecd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082998382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3082998382
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1267532391
Short name T625
Test name
Test status
Simulation time 487880105424 ps
CPU time 1105.65 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 07:08:26 PM PDT 24
Peak memory 201192 kb
Host smart-dfc8eac4-d96a-4de1-aef3-a7fac902ac60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267532391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1267532391
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3124390769
Short name T198
Test name
Test status
Simulation time 159543144752 ps
CPU time 231.62 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:53:52 PM PDT 24
Peak memory 218108 kb
Host smart-c4f70d3c-d9a9-4354-beed-f3e0ec1ea866
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124390769 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3124390769
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.783909386
Short name T416
Test name
Test status
Simulation time 499624692 ps
CPU time 1.16 seconds
Started Jul 26 06:50:08 PM PDT 24
Finished Jul 26 06:50:09 PM PDT 24
Peak memory 200952 kb
Host smart-925fe042-6e0f-45cb-9811-775b6f0b4003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783909386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.783909386
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3101208729
Short name T228
Test name
Test status
Simulation time 499794732366 ps
CPU time 272.86 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:54:33 PM PDT 24
Peak memory 201152 kb
Host smart-24ed572f-2aa9-4d53-b1e5-32453af77ccf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101208729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3101208729
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3136321552
Short name T315
Test name
Test status
Simulation time 492720643379 ps
CPU time 1191.28 seconds
Started Jul 26 06:50:04 PM PDT 24
Finished Jul 26 07:09:55 PM PDT 24
Peak memory 201212 kb
Host smart-5006cded-4992-42b8-b2b6-0a29c4a4ccfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136321552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3136321552
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1585613062
Short name T167
Test name
Test status
Simulation time 328018323576 ps
CPU time 129.48 seconds
Started Jul 26 06:50:04 PM PDT 24
Finished Jul 26 06:52:14 PM PDT 24
Peak memory 201284 kb
Host smart-66e1dc2f-1c4e-4429-8c33-5a25bf69b6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585613062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1585613062
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2236740311
Short name T555
Test name
Test status
Simulation time 160351103484 ps
CPU time 171.33 seconds
Started Jul 26 06:50:02 PM PDT 24
Finished Jul 26 06:52:54 PM PDT 24
Peak memory 201200 kb
Host smart-e62ce537-4dbc-4113-b21c-ecc01c10e155
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236740311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2236740311
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3081249835
Short name T756
Test name
Test status
Simulation time 163906682980 ps
CPU time 95.12 seconds
Started Jul 26 06:50:04 PM PDT 24
Finished Jul 26 06:51:39 PM PDT 24
Peak memory 201280 kb
Host smart-2611d55b-8b93-4628-a1c2-71d275922a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081249835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3081249835
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2829890204
Short name T162
Test name
Test status
Simulation time 163902920576 ps
CPU time 69.72 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:51:10 PM PDT 24
Peak memory 201164 kb
Host smart-0c44c723-6f83-4e24-89e0-5b74aab41a5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829890204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2829890204
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1080859023
Short name T621
Test name
Test status
Simulation time 351595974403 ps
CPU time 226.3 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:53:45 PM PDT 24
Peak memory 201224 kb
Host smart-fdbb28ff-79c7-4002-92f9-09b000887f7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080859023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1080859023
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1658126518
Short name T436
Test name
Test status
Simulation time 201266936168 ps
CPU time 464.05 seconds
Started Jul 26 06:50:01 PM PDT 24
Finished Jul 26 06:57:45 PM PDT 24
Peak memory 201152 kb
Host smart-88661223-a891-4466-984e-7cea9ea5847c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658126518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1658126518
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1861724980
Short name T28
Test name
Test status
Simulation time 127174199657 ps
CPU time 486.95 seconds
Started Jul 26 06:50:03 PM PDT 24
Finished Jul 26 06:58:10 PM PDT 24
Peak memory 201632 kb
Host smart-9d7732d2-639e-49a2-89cc-4cbf48223c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861724980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1861724980
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.4211196404
Short name T101
Test name
Test status
Simulation time 38098901830 ps
CPU time 23.87 seconds
Started Jul 26 06:50:01 PM PDT 24
Finished Jul 26 06:50:25 PM PDT 24
Peak memory 200972 kb
Host smart-e33531f8-2280-4e67-9d13-f8880cf7080c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211196404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.4211196404
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.639502400
Short name T1
Test name
Test status
Simulation time 5536766275 ps
CPU time 13.98 seconds
Started Jul 26 06:50:02 PM PDT 24
Finished Jul 26 06:50:16 PM PDT 24
Peak memory 200988 kb
Host smart-a35c732e-19cd-494c-9794-65abb5aefbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639502400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.639502400
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.4190733718
Short name T675
Test name
Test status
Simulation time 5718657511 ps
CPU time 13.07 seconds
Started Jul 26 06:50:04 PM PDT 24
Finished Jul 26 06:50:17 PM PDT 24
Peak memory 201068 kb
Host smart-35b622c4-d1a1-4096-a942-7fafe142f3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190733718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.4190733718
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3776593114
Short name T268
Test name
Test status
Simulation time 179203306671 ps
CPU time 419 seconds
Started Jul 26 06:49:54 PM PDT 24
Finished Jul 26 06:56:53 PM PDT 24
Peak memory 201196 kb
Host smart-ca8b3527-3e4f-409a-b57b-35fdcd17214e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776593114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3776593114
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2570744500
Short name T36
Test name
Test status
Simulation time 62921571828 ps
CPU time 144.42 seconds
Started Jul 26 06:50:02 PM PDT 24
Finished Jul 26 06:52:27 PM PDT 24
Peak memory 201360 kb
Host smart-b78f1fe6-d224-4509-8dc0-3870e4b66a72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570744500 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2570744500
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2943054613
Short name T700
Test name
Test status
Simulation time 301258766 ps
CPU time 1.28 seconds
Started Jul 26 06:50:06 PM PDT 24
Finished Jul 26 06:50:07 PM PDT 24
Peak memory 200968 kb
Host smart-b8d3c6c1-733e-46af-92cb-4f0a8fe27a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943054613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2943054613
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3993736354
Short name T665
Test name
Test status
Simulation time 385960124728 ps
CPU time 214 seconds
Started Jul 26 06:50:10 PM PDT 24
Finished Jul 26 06:53:44 PM PDT 24
Peak memory 201228 kb
Host smart-e54c9a94-2c31-43c6-9741-a7c87878d3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993736354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3993736354
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2393810657
Short name T631
Test name
Test status
Simulation time 491622218059 ps
CPU time 1176.83 seconds
Started Jul 26 06:50:09 PM PDT 24
Finished Jul 26 07:09:46 PM PDT 24
Peak memory 201168 kb
Host smart-7561ac24-68ac-4d94-98e7-4892f9ae9e40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393810657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2393810657
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1858621078
Short name T173
Test name
Test status
Simulation time 494619354444 ps
CPU time 130.33 seconds
Started Jul 26 06:50:09 PM PDT 24
Finished Jul 26 06:52:19 PM PDT 24
Peak memory 201116 kb
Host smart-07d31f79-093d-4ddb-a363-e1de988db1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858621078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1858621078
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3705881453
Short name T773
Test name
Test status
Simulation time 162933747175 ps
CPU time 371.61 seconds
Started Jul 26 06:50:07 PM PDT 24
Finished Jul 26 06:56:19 PM PDT 24
Peak memory 201152 kb
Host smart-78b08b06-19fb-4117-bb08-139d70b08851
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705881453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3705881453
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1400706604
Short name T320
Test name
Test status
Simulation time 186566142458 ps
CPU time 32.41 seconds
Started Jul 26 06:50:13 PM PDT 24
Finished Jul 26 06:50:46 PM PDT 24
Peak memory 201132 kb
Host smart-d0e8dad0-69a9-4b6a-8b07-b62996f188af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400706604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1400706604
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1712768096
Short name T492
Test name
Test status
Simulation time 625558096381 ps
CPU time 381.23 seconds
Started Jul 26 06:50:08 PM PDT 24
Finished Jul 26 06:56:29 PM PDT 24
Peak memory 201208 kb
Host smart-394d38ca-7140-4db2-863b-ffde22d7cb38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712768096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1712768096
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2630585899
Short name T78
Test name
Test status
Simulation time 71485667615 ps
CPU time 256.76 seconds
Started Jul 26 06:50:09 PM PDT 24
Finished Jul 26 06:54:26 PM PDT 24
Peak memory 201616 kb
Host smart-7ce5ab18-cb76-406c-91c1-dae7d24f25df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630585899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2630585899
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2311558641
Short name T664
Test name
Test status
Simulation time 31868273280 ps
CPU time 24.36 seconds
Started Jul 26 06:50:05 PM PDT 24
Finished Jul 26 06:50:29 PM PDT 24
Peak memory 201040 kb
Host smart-d931d724-9e67-469b-bca4-911ba899feaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311558641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2311558641
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.4280346031
Short name T777
Test name
Test status
Simulation time 5198660921 ps
CPU time 6.91 seconds
Started Jul 26 06:50:08 PM PDT 24
Finished Jul 26 06:50:15 PM PDT 24
Peak memory 200968 kb
Host smart-3e471187-45c3-4e6f-9c2b-3a2e3d7fdd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280346031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.4280346031
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.695704398
Short name T377
Test name
Test status
Simulation time 5896702170 ps
CPU time 13.18 seconds
Started Jul 26 06:50:08 PM PDT 24
Finished Jul 26 06:50:21 PM PDT 24
Peak memory 201052 kb
Host smart-1dc7779c-b05a-408b-a2b8-e48fdee2e979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695704398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.695704398
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1860045008
Short name T364
Test name
Test status
Simulation time 470956880 ps
CPU time 0.85 seconds
Started Jul 26 06:50:16 PM PDT 24
Finished Jul 26 06:50:17 PM PDT 24
Peak memory 200920 kb
Host smart-13495c9e-de0e-4819-8533-333ca66376c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860045008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1860045008
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3020102500
Short name T670
Test name
Test status
Simulation time 181725942580 ps
CPU time 390.29 seconds
Started Jul 26 06:50:15 PM PDT 24
Finished Jul 26 06:56:45 PM PDT 24
Peak memory 201256 kb
Host smart-8228e1f9-8164-4d53-a3ea-f583fcab9b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020102500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3020102500
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1679994080
Short name T587
Test name
Test status
Simulation time 334940447251 ps
CPU time 49.05 seconds
Started Jul 26 06:50:08 PM PDT 24
Finished Jul 26 06:50:57 PM PDT 24
Peak memory 201232 kb
Host smart-b2270865-bc73-4ee0-8f12-0f25c56b3af7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679994080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1679994080
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3147598182
Short name T747
Test name
Test status
Simulation time 483443845672 ps
CPU time 210.85 seconds
Started Jul 26 06:50:10 PM PDT 24
Finished Jul 26 06:53:41 PM PDT 24
Peak memory 201136 kb
Host smart-670b0252-c8b9-4183-9f21-2d93f0e0dcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147598182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3147598182
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.964641235
Short name T698
Test name
Test status
Simulation time 163683546934 ps
CPU time 367.71 seconds
Started Jul 26 06:50:11 PM PDT 24
Finished Jul 26 06:56:18 PM PDT 24
Peak memory 201132 kb
Host smart-00230457-1962-4a62-8228-028ce9e0c699
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=964641235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.964641235
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1700230165
Short name T771
Test name
Test status
Simulation time 390940619617 ps
CPU time 914.5 seconds
Started Jul 26 06:50:12 PM PDT 24
Finished Jul 26 07:05:27 PM PDT 24
Peak memory 201128 kb
Host smart-90ab9627-b4be-4d36-bff9-ce21fd34e523
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700230165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1700230165
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3891791909
Short name T88
Test name
Test status
Simulation time 211555108152 ps
CPU time 130.5 seconds
Started Jul 26 06:50:14 PM PDT 24
Finished Jul 26 06:52:24 PM PDT 24
Peak memory 201120 kb
Host smart-ea2f2816-a525-403b-a23e-50287a8b1947
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891791909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3891791909
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2201867211
Short name T569
Test name
Test status
Simulation time 93879916629 ps
CPU time 493.76 seconds
Started Jul 26 06:50:18 PM PDT 24
Finished Jul 26 06:58:32 PM PDT 24
Peak memory 201592 kb
Host smart-4175b089-62b7-4b1e-bbc8-3f8d5012c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201867211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2201867211
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1153232521
Short name T395
Test name
Test status
Simulation time 46516363218 ps
CPU time 112.07 seconds
Started Jul 26 06:50:17 PM PDT 24
Finished Jul 26 06:52:10 PM PDT 24
Peak memory 200996 kb
Host smart-46967d5c-2607-4511-afb0-d8ee0c80b178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153232521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1153232521
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1471622007
Short name T482
Test name
Test status
Simulation time 3282877875 ps
CPU time 2.5 seconds
Started Jul 26 06:50:18 PM PDT 24
Finished Jul 26 06:50:20 PM PDT 24
Peak memory 201012 kb
Host smart-16970591-d41c-4010-a7a9-ea8c9d8fa085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471622007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1471622007
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.4009987208
Short name T400
Test name
Test status
Simulation time 6037828877 ps
CPU time 8.46 seconds
Started Jul 26 06:50:13 PM PDT 24
Finished Jul 26 06:50:22 PM PDT 24
Peak memory 200988 kb
Host smart-74c4c8ba-926e-4d1d-9437-814b6624604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009987208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.4009987208
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4062484591
Short name T18
Test name
Test status
Simulation time 72695240182 ps
CPU time 131.53 seconds
Started Jul 26 06:50:16 PM PDT 24
Finished Jul 26 06:52:27 PM PDT 24
Peak memory 210168 kb
Host smart-d7a7cdbf-9d4d-42a0-a4e9-6eb48b10fc94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062484591 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.4062484591
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2972889523
Short name T611
Test name
Test status
Simulation time 472234132 ps
CPU time 1.13 seconds
Started Jul 26 06:50:25 PM PDT 24
Finished Jul 26 06:50:26 PM PDT 24
Peak memory 200968 kb
Host smart-12f7ef32-0038-4584-92f9-537ac5518e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972889523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2972889523
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.682801326
Short name T585
Test name
Test status
Simulation time 329654347128 ps
CPU time 395.06 seconds
Started Jul 26 06:50:17 PM PDT 24
Finished Jul 26 06:56:52 PM PDT 24
Peak memory 201136 kb
Host smart-fbb995f3-1821-4bed-82d4-7dc6092c2bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682801326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.682801326
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2150098808
Short name T488
Test name
Test status
Simulation time 500070592991 ps
CPU time 280.6 seconds
Started Jul 26 06:50:18 PM PDT 24
Finished Jul 26 06:54:59 PM PDT 24
Peak memory 201216 kb
Host smart-66f13f30-53be-42b2-8e59-7eedd37d3356
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150098808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2150098808
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3519074055
Short name T557
Test name
Test status
Simulation time 163492059176 ps
CPU time 97.52 seconds
Started Jul 26 06:50:18 PM PDT 24
Finished Jul 26 06:51:55 PM PDT 24
Peak memory 201224 kb
Host smart-c1c1ced9-b6f4-4cb5-b414-0cdbef21517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519074055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3519074055
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1421989994
Short name T737
Test name
Test status
Simulation time 489206280173 ps
CPU time 1113.71 seconds
Started Jul 26 06:50:16 PM PDT 24
Finished Jul 26 07:08:50 PM PDT 24
Peak memory 201156 kb
Host smart-802c600d-4237-443d-954d-828d43edd15d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421989994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1421989994
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3666695402
Short name T776
Test name
Test status
Simulation time 370203072019 ps
CPU time 220.89 seconds
Started Jul 26 06:50:17 PM PDT 24
Finished Jul 26 06:53:58 PM PDT 24
Peak memory 201132 kb
Host smart-608f7292-95da-4149-8193-26430b433b8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666695402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3666695402
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3956408866
Short name T724
Test name
Test status
Simulation time 202203746040 ps
CPU time 140.07 seconds
Started Jul 26 06:50:26 PM PDT 24
Finished Jul 26 06:52:46 PM PDT 24
Peak memory 201120 kb
Host smart-9ded365c-0716-4c17-b193-ce35c26926cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956408866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3956408866
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.576181640
Short name T692
Test name
Test status
Simulation time 104839086398 ps
CPU time 456.53 seconds
Started Jul 26 06:50:23 PM PDT 24
Finished Jul 26 06:58:00 PM PDT 24
Peak memory 201584 kb
Host smart-9312c6b1-f7ae-470d-89ed-1a87e8011d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576181640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.576181640
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3895600618
Short name T184
Test name
Test status
Simulation time 21767008579 ps
CPU time 9.08 seconds
Started Jul 26 06:50:29 PM PDT 24
Finished Jul 26 06:50:39 PM PDT 24
Peak memory 200996 kb
Host smart-7ac994d0-dcf8-4e50-a6a2-01ccede80b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895600618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3895600618
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.544071699
Short name T432
Test name
Test status
Simulation time 3006180881 ps
CPU time 2.87 seconds
Started Jul 26 06:50:25 PM PDT 24
Finished Jul 26 06:50:28 PM PDT 24
Peak memory 200992 kb
Host smart-fe83bb4b-f71c-49f5-a7d9-bf92768befb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544071699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.544071699
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3658965899
Short name T356
Test name
Test status
Simulation time 5728672439 ps
CPU time 8.86 seconds
Started Jul 26 06:50:16 PM PDT 24
Finished Jul 26 06:50:25 PM PDT 24
Peak memory 201020 kb
Host smart-b91152c7-8c8c-4747-89b5-54e4eb7ad1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658965899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3658965899
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.39540330
Short name T565
Test name
Test status
Simulation time 410459214376 ps
CPU time 307.16 seconds
Started Jul 26 06:50:26 PM PDT 24
Finished Jul 26 06:55:33 PM PDT 24
Peak memory 201740 kb
Host smart-7e51f83b-c07f-4d29-a4aa-1a763425b2ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39540330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.39540330
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1714005503
Short name T729
Test name
Test status
Simulation time 366862871 ps
CPU time 1.47 seconds
Started Jul 26 06:50:43 PM PDT 24
Finished Jul 26 06:50:45 PM PDT 24
Peak memory 200952 kb
Host smart-454d9daa-84d8-4ca9-8aeb-7c4485600555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714005503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1714005503
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1181611553
Short name T242
Test name
Test status
Simulation time 178738525086 ps
CPU time 372.41 seconds
Started Jul 26 06:50:34 PM PDT 24
Finished Jul 26 06:56:47 PM PDT 24
Peak memory 201296 kb
Host smart-b78a2b33-f163-4043-8908-7ab0783c46ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181611553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1181611553
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3939618449
Short name T179
Test name
Test status
Simulation time 323150937217 ps
CPU time 183.06 seconds
Started Jul 26 06:50:26 PM PDT 24
Finished Jul 26 06:53:30 PM PDT 24
Peak memory 201256 kb
Host smart-a0e485a1-c26c-443c-8fdd-d4269fe74ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939618449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3939618449
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.395085014
Short name T751
Test name
Test status
Simulation time 497935061631 ps
CPU time 589.9 seconds
Started Jul 26 06:50:24 PM PDT 24
Finished Jul 26 07:00:14 PM PDT 24
Peak memory 201160 kb
Host smart-ae6a0236-1a44-4d70-88e5-5d17da8e9953
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=395085014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.395085014
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2929145627
Short name T734
Test name
Test status
Simulation time 486848486878 ps
CPU time 526.77 seconds
Started Jul 26 06:50:25 PM PDT 24
Finished Jul 26 06:59:12 PM PDT 24
Peak memory 201176 kb
Host smart-06676b94-afdc-4641-841d-dde43036bf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929145627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2929145627
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1167023307
Short name T175
Test name
Test status
Simulation time 165221228841 ps
CPU time 91.14 seconds
Started Jul 26 06:50:31 PM PDT 24
Finished Jul 26 06:52:02 PM PDT 24
Peak memory 201160 kb
Host smart-6a6b8713-1706-48e3-8581-99165e4800e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167023307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1167023307
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3782458505
Short name T758
Test name
Test status
Simulation time 202345614639 ps
CPU time 107.13 seconds
Started Jul 26 06:50:32 PM PDT 24
Finished Jul 26 06:52:20 PM PDT 24
Peak memory 201112 kb
Host smart-26f7ad7a-61e5-405a-a8c0-d286badbe9b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782458505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3782458505
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.398037244
Short name T522
Test name
Test status
Simulation time 95241485182 ps
CPU time 375.02 seconds
Started Jul 26 06:50:33 PM PDT 24
Finished Jul 26 06:56:48 PM PDT 24
Peak memory 201872 kb
Host smart-c0f4867a-f150-46ac-a394-c2c9fe7e34c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398037244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.398037244
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.378579858
Short name T583
Test name
Test status
Simulation time 27399462087 ps
CPU time 16.27 seconds
Started Jul 26 06:50:33 PM PDT 24
Finished Jul 26 06:50:50 PM PDT 24
Peak memory 200964 kb
Host smart-8db1979a-06f3-4cb0-9c45-c1e4514cb0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378579858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.378579858
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.412443798
Short name T479
Test name
Test status
Simulation time 5248851701 ps
CPU time 6.96 seconds
Started Jul 26 06:50:34 PM PDT 24
Finished Jul 26 06:50:41 PM PDT 24
Peak memory 200932 kb
Host smart-1d46462e-f0e9-42ad-82f9-e6cda8496a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412443798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.412443798
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1120181835
Short name T520
Test name
Test status
Simulation time 5668422499 ps
CPU time 6.95 seconds
Started Jul 26 06:50:30 PM PDT 24
Finished Jul 26 06:50:37 PM PDT 24
Peak memory 201016 kb
Host smart-4ed0e27d-5f19-4bde-b7af-90091a24172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120181835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1120181835
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3995770471
Short name T85
Test name
Test status
Simulation time 138509776114 ps
CPU time 274.74 seconds
Started Jul 26 06:50:35 PM PDT 24
Finished Jul 26 06:55:10 PM PDT 24
Peak memory 209940 kb
Host smart-bff450c5-63f6-48be-b37f-ba0acd0b492f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995770471 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3995770471
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.4180920771
Short name T600
Test name
Test status
Simulation time 298820915 ps
CPU time 0.96 seconds
Started Jul 26 06:50:45 PM PDT 24
Finished Jul 26 06:50:46 PM PDT 24
Peak memory 200972 kb
Host smart-5ca8ab78-2321-41b9-9296-505694d229be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180920771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.4180920771
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3476859616
Short name T739
Test name
Test status
Simulation time 513351336628 ps
CPU time 289.81 seconds
Started Jul 26 06:50:45 PM PDT 24
Finished Jul 26 06:55:35 PM PDT 24
Peak memory 201224 kb
Host smart-424184fc-ab20-4c71-8e9f-f6ebab12b57d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476859616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3476859616
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1544148659
Short name T699
Test name
Test status
Simulation time 333335476115 ps
CPU time 61.5 seconds
Started Jul 26 06:50:42 PM PDT 24
Finished Jul 26 06:51:44 PM PDT 24
Peak memory 201172 kb
Host smart-50997062-a8f0-4847-a071-7a302c0f3082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544148659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1544148659
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.4149495138
Short name T138
Test name
Test status
Simulation time 495868322448 ps
CPU time 574.46 seconds
Started Jul 26 06:50:43 PM PDT 24
Finished Jul 26 07:00:17 PM PDT 24
Peak memory 201196 kb
Host smart-a52e6a26-bc12-4816-b5ac-c19781f7ff16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149495138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.4149495138
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3153470532
Short name T543
Test name
Test status
Simulation time 322708982504 ps
CPU time 379.18 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 06:57:04 PM PDT 24
Peak memory 201180 kb
Host smart-5b3ea225-5f7a-486f-99bc-572f0bf64b9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153470532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3153470532
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1563549508
Short name T570
Test name
Test status
Simulation time 165838141873 ps
CPU time 28.55 seconds
Started Jul 26 06:50:43 PM PDT 24
Finished Jul 26 06:51:12 PM PDT 24
Peak memory 201428 kb
Host smart-3311240f-5aac-4e71-9e84-ae01bf04bc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563549508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1563549508
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1305849832
Short name T401
Test name
Test status
Simulation time 163677557383 ps
CPU time 390.57 seconds
Started Jul 26 06:50:46 PM PDT 24
Finished Jul 26 06:57:17 PM PDT 24
Peak memory 200976 kb
Host smart-484d1eed-352d-4ff2-9419-4c55002ab242
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305849832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1305849832
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.926345358
Short name T743
Test name
Test status
Simulation time 370019397342 ps
CPU time 178.52 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 06:53:43 PM PDT 24
Peak memory 201188 kb
Host smart-8de1ecfa-d704-45b5-85ef-cfa0ff475eb7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926345358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.926345358
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2829194020
Short name T473
Test name
Test status
Simulation time 603695472660 ps
CPU time 1406.24 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 07:14:10 PM PDT 24
Peak memory 201124 kb
Host smart-163e1dae-0fe7-429a-987a-d433bf44a404
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829194020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2829194020
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1809570742
Short name T390
Test name
Test status
Simulation time 68774401205 ps
CPU time 290.43 seconds
Started Jul 26 06:50:43 PM PDT 24
Finished Jul 26 06:55:34 PM PDT 24
Peak memory 201528 kb
Host smart-e6437616-af62-482f-bb99-69e940b1118d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809570742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1809570742
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.805075741
Short name T409
Test name
Test status
Simulation time 29000287775 ps
CPU time 17.58 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 06:51:02 PM PDT 24
Peak memory 200880 kb
Host smart-683c4fbf-60bf-4e77-81e9-ce20fffb57d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805075741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.805075741
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1341389067
Short name T433
Test name
Test status
Simulation time 5338502112 ps
CPU time 13.82 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 06:50:58 PM PDT 24
Peak memory 200996 kb
Host smart-64ff682b-448f-46d7-b8bb-cb3770554524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341389067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1341389067
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3685293474
Short name T351
Test name
Test status
Simulation time 5965798894 ps
CPU time 4.31 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 06:50:49 PM PDT 24
Peak memory 201028 kb
Host smart-27718559-433c-411f-bd1c-41cbdcbbefb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685293474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3685293474
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.369669371
Short name T676
Test name
Test status
Simulation time 196052979890 ps
CPU time 169.92 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 06:53:34 PM PDT 24
Peak memory 201116 kb
Host smart-35549eca-696e-4a62-a986-6ecc6b661ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369669371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
369669371
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2421253913
Short name T733
Test name
Test status
Simulation time 197741167996 ps
CPU time 210.06 seconds
Started Jul 26 06:50:43 PM PDT 24
Finished Jul 26 06:54:14 PM PDT 24
Peak memory 216504 kb
Host smart-346cc7d7-5148-4cf2-816b-79603abc5c88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421253913 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2421253913
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1365003899
Short name T485
Test name
Test status
Simulation time 405681174 ps
CPU time 1.52 seconds
Started Jul 26 06:50:52 PM PDT 24
Finished Jul 26 06:50:54 PM PDT 24
Peak memory 201008 kb
Host smart-dc0d7454-c0bc-4267-8ed1-926517c07135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365003899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1365003899
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.841880990
Short name T134
Test name
Test status
Simulation time 336265539486 ps
CPU time 759.82 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 07:03:25 PM PDT 24
Peak memory 201220 kb
Host smart-f14f5add-5a3d-434f-8352-79bf7cd4f850
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841880990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.841880990
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1200179790
Short name T713
Test name
Test status
Simulation time 351111003722 ps
CPU time 367.87 seconds
Started Jul 26 06:50:42 PM PDT 24
Finished Jul 26 06:56:50 PM PDT 24
Peak memory 201140 kb
Host smart-b9aeeb20-840f-4d5d-af4a-12a51ca4b91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200179790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1200179790
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2708857455
Short name T278
Test name
Test status
Simulation time 169566522787 ps
CPU time 94.07 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 06:52:18 PM PDT 24
Peak memory 201172 kb
Host smart-6992afa0-2867-48f5-8b37-209df7c033b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708857455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2708857455
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3375979673
Short name T547
Test name
Test status
Simulation time 329009013992 ps
CPU time 716.76 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 07:02:41 PM PDT 24
Peak memory 201152 kb
Host smart-7a12523c-7d0c-4752-99cf-4d4f8ae0396f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375979673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3375979673
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2204405429
Short name T674
Test name
Test status
Simulation time 331819085465 ps
CPU time 716.2 seconds
Started Jul 26 06:50:46 PM PDT 24
Finished Jul 26 07:02:42 PM PDT 24
Peak memory 201000 kb
Host smart-71ec9d42-fa1b-4601-bc51-b5f70de6c024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204405429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2204405429
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.565276033
Short name T683
Test name
Test status
Simulation time 164700824179 ps
CPU time 106.61 seconds
Started Jul 26 06:50:43 PM PDT 24
Finished Jul 26 06:52:30 PM PDT 24
Peak memory 201160 kb
Host smart-fd5fc13c-7a5d-419e-8e93-3c713546eeca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=565276033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.565276033
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.665817602
Short name T165
Test name
Test status
Simulation time 179891979956 ps
CPU time 105.05 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 06:52:29 PM PDT 24
Peak memory 201132 kb
Host smart-7b371a2e-29a3-4239-9361-88d29c8e0b6c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665817602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.665817602
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3367260375
Short name T537
Test name
Test status
Simulation time 387327554600 ps
CPU time 451.38 seconds
Started Jul 26 06:50:44 PM PDT 24
Finished Jul 26 06:58:16 PM PDT 24
Peak memory 201176 kb
Host smart-b4c12855-f3a1-4832-9e75-36217741a8bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367260375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3367260375
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.298312146
Short name T46
Test name
Test status
Simulation time 88130616143 ps
CPU time 350.34 seconds
Started Jul 26 06:50:52 PM PDT 24
Finished Jul 26 06:56:43 PM PDT 24
Peak memory 201608 kb
Host smart-3b728089-9615-4080-b47a-2109761d5876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298312146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.298312146
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3442032849
Short name T671
Test name
Test status
Simulation time 30649356444 ps
CPU time 63.2 seconds
Started Jul 26 06:50:43 PM PDT 24
Finished Jul 26 06:51:46 PM PDT 24
Peak memory 201076 kb
Host smart-f30cd7c3-b348-4db9-ae93-bbbc4964b508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442032849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3442032849
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1790069983
Short name T757
Test name
Test status
Simulation time 3005729750 ps
CPU time 2.42 seconds
Started Jul 26 06:50:45 PM PDT 24
Finished Jul 26 06:50:47 PM PDT 24
Peak memory 200952 kb
Host smart-71ac72ac-7b07-4d67-80cd-c1066cd44bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790069983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1790069983
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2653956398
Short name T566
Test name
Test status
Simulation time 5810478155 ps
CPU time 7.29 seconds
Started Jul 26 06:50:43 PM PDT 24
Finished Jul 26 06:50:51 PM PDT 24
Peak memory 201028 kb
Host smart-5390e919-fb4d-4037-a20b-7bebbcaa9831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653956398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2653956398
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.85234630
Short name T19
Test name
Test status
Simulation time 83933251407 ps
CPU time 89.82 seconds
Started Jul 26 06:50:54 PM PDT 24
Finished Jul 26 06:52:24 PM PDT 24
Peak memory 201792 kb
Host smart-113eb79d-3b8c-4d73-a392-e2a951e37422
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85234630 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.85234630
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1451244244
Short name T421
Test name
Test status
Simulation time 475348019 ps
CPU time 1.18 seconds
Started Jul 26 06:51:06 PM PDT 24
Finished Jul 26 06:51:07 PM PDT 24
Peak memory 200920 kb
Host smart-47642710-2141-42c5-9019-0820b6b74746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451244244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1451244244
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2754546099
Short name T100
Test name
Test status
Simulation time 596555075360 ps
CPU time 898.65 seconds
Started Jul 26 06:50:52 PM PDT 24
Finished Jul 26 07:05:51 PM PDT 24
Peak memory 201120 kb
Host smart-b0b2f4af-692e-49ad-9596-f34ad6f24707
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754546099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2754546099
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2196956040
Short name T655
Test name
Test status
Simulation time 321872023567 ps
CPU time 683.3 seconds
Started Jul 26 06:50:54 PM PDT 24
Finished Jul 26 07:02:18 PM PDT 24
Peak memory 201144 kb
Host smart-000301d1-ff29-4015-a2b7-25563cd74643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196956040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2196956040
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2647604702
Short name T513
Test name
Test status
Simulation time 168211904926 ps
CPU time 32.09 seconds
Started Jul 26 06:50:54 PM PDT 24
Finished Jul 26 06:51:26 PM PDT 24
Peak memory 201072 kb
Host smart-6bb6a95f-1f93-4a3d-9cb1-df5132df10dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647604702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2647604702
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3623632942
Short name T243
Test name
Test status
Simulation time 162978642022 ps
CPU time 92.95 seconds
Started Jul 26 06:50:53 PM PDT 24
Finished Jul 26 06:52:26 PM PDT 24
Peak memory 201144 kb
Host smart-df00482e-da14-4a99-98e3-2582b9fdd5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623632942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3623632942
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3860605509
Short name T380
Test name
Test status
Simulation time 330556061061 ps
CPU time 407.37 seconds
Started Jul 26 06:50:54 PM PDT 24
Finished Jul 26 06:57:41 PM PDT 24
Peak memory 201160 kb
Host smart-b2ef8df6-ba91-45a8-82f0-825673b853de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860605509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3860605509
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1693655121
Short name T196
Test name
Test status
Simulation time 533517998540 ps
CPU time 1076.51 seconds
Started Jul 26 06:50:54 PM PDT 24
Finished Jul 26 07:08:50 PM PDT 24
Peak memory 201172 kb
Host smart-94d05995-8ca3-4ccf-bbfb-1ba8c7df2154
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693655121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1693655121
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1046086413
Short name T498
Test name
Test status
Simulation time 402054761098 ps
CPU time 429.58 seconds
Started Jul 26 06:50:52 PM PDT 24
Finished Jul 26 06:58:02 PM PDT 24
Peak memory 201224 kb
Host smart-1589e6f9-5c7e-4de2-b99e-a993d02083ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046086413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1046086413
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2637355782
Short name T197
Test name
Test status
Simulation time 79833754589 ps
CPU time 294.71 seconds
Started Jul 26 06:50:52 PM PDT 24
Finished Jul 26 06:55:47 PM PDT 24
Peak memory 201684 kb
Host smart-f8afdd88-51a3-4d4b-8001-2fd6cc30d474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637355782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2637355782
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.326418808
Short name T544
Test name
Test status
Simulation time 28686551564 ps
CPU time 69.97 seconds
Started Jul 26 06:50:52 PM PDT 24
Finished Jul 26 06:52:02 PM PDT 24
Peak memory 200972 kb
Host smart-c45daac1-944d-43c0-8e07-4b265d8f359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326418808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.326418808
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2887537673
Short name T471
Test name
Test status
Simulation time 3978983417 ps
CPU time 2.57 seconds
Started Jul 26 06:50:53 PM PDT 24
Finished Jul 26 06:50:55 PM PDT 24
Peak memory 201024 kb
Host smart-1db2c7c4-aab7-40d6-b1cd-235fbaad9ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887537673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2887537673
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4006115659
Short name T460
Test name
Test status
Simulation time 6182130838 ps
CPU time 14.47 seconds
Started Jul 26 06:50:51 PM PDT 24
Finished Jul 26 06:51:06 PM PDT 24
Peak memory 201020 kb
Host smart-d89bb323-6cac-4e0f-a7db-044d95e763c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006115659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4006115659
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2633401266
Short name T245
Test name
Test status
Simulation time 343272600487 ps
CPU time 222.11 seconds
Started Jul 26 06:50:52 PM PDT 24
Finished Jul 26 06:54:34 PM PDT 24
Peak memory 201232 kb
Host smart-658d4f42-b5fa-4a31-b52a-a7c058e86cda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633401266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2633401266
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2943252331
Short name T17
Test name
Test status
Simulation time 19285376344 ps
CPU time 23.1 seconds
Started Jul 26 06:50:52 PM PDT 24
Finished Jul 26 06:51:15 PM PDT 24
Peak memory 201308 kb
Host smart-2ea27837-6a0e-461d-934e-82346a1f52af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943252331 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2943252331
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1216616924
Short name T81
Test name
Test status
Simulation time 380210242 ps
CPU time 0.8 seconds
Started Jul 26 06:51:07 PM PDT 24
Finished Jul 26 06:51:07 PM PDT 24
Peak memory 200920 kb
Host smart-a97d672d-6a1f-43f0-98db-ef4fb856ab24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216616924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1216616924
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1126728668
Short name T284
Test name
Test status
Simulation time 161069694247 ps
CPU time 173.99 seconds
Started Jul 26 06:51:03 PM PDT 24
Finished Jul 26 06:53:57 PM PDT 24
Peak memory 201236 kb
Host smart-673134a0-1edb-4575-bc14-2709ea5f8113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126728668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1126728668
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.724069622
Short name T256
Test name
Test status
Simulation time 321315561838 ps
CPU time 147.1 seconds
Started Jul 26 06:51:02 PM PDT 24
Finished Jul 26 06:53:29 PM PDT 24
Peak memory 201188 kb
Host smart-346b609c-8ca0-40ee-a9a5-8a641e2fb9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724069622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.724069622
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.278917027
Short name T176
Test name
Test status
Simulation time 330393445008 ps
CPU time 184.07 seconds
Started Jul 26 06:51:02 PM PDT 24
Finished Jul 26 06:54:06 PM PDT 24
Peak memory 201120 kb
Host smart-840b6334-61ce-4632-9af4-dc3674e0aaaa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=278917027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.278917027
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3717100359
Short name T387
Test name
Test status
Simulation time 330033251594 ps
CPU time 121.64 seconds
Started Jul 26 06:51:02 PM PDT 24
Finished Jul 26 06:53:04 PM PDT 24
Peak memory 201228 kb
Host smart-50d2f648-0fe2-4277-9f41-794381f29822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717100359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3717100359
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3400093837
Short name T789
Test name
Test status
Simulation time 165939383164 ps
CPU time 121.42 seconds
Started Jul 26 06:51:04 PM PDT 24
Finished Jul 26 06:53:05 PM PDT 24
Peak memory 201160 kb
Host smart-89dd1a73-2080-4399-8001-12eabadfc248
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400093837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3400093837
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3879390473
Short name T726
Test name
Test status
Simulation time 527238378086 ps
CPU time 1148.6 seconds
Started Jul 26 06:51:06 PM PDT 24
Finished Jul 26 07:10:15 PM PDT 24
Peak memory 201120 kb
Host smart-40dd2183-0b2c-4b7f-8f5e-e46477d5c527
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879390473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3879390473
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3000853251
Short name T799
Test name
Test status
Simulation time 399802843211 ps
CPU time 942.18 seconds
Started Jul 26 06:51:04 PM PDT 24
Finished Jul 26 07:06:46 PM PDT 24
Peak memory 201188 kb
Host smart-26c6e8ac-e364-45d6-9b89-eef2fb9fc632
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000853251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3000853251
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3019613315
Short name T748
Test name
Test status
Simulation time 114110023671 ps
CPU time 604.7 seconds
Started Jul 26 06:51:04 PM PDT 24
Finished Jul 26 07:01:09 PM PDT 24
Peak memory 201588 kb
Host smart-0a070684-a913-48e9-9a3b-744e37e75b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019613315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3019613315
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2774219948
Short name T779
Test name
Test status
Simulation time 40900366001 ps
CPU time 97.75 seconds
Started Jul 26 06:51:05 PM PDT 24
Finished Jul 26 06:52:43 PM PDT 24
Peak memory 200980 kb
Host smart-154065b5-e029-406a-9a12-9d9d0c377222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774219948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2774219948
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.682261804
Short name T444
Test name
Test status
Simulation time 4230856513 ps
CPU time 3.02 seconds
Started Jul 26 06:51:02 PM PDT 24
Finished Jul 26 06:51:05 PM PDT 24
Peak memory 200988 kb
Host smart-8108d96b-dd30-480b-9c5a-f70131dc31c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682261804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.682261804
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3342759790
Short name T695
Test name
Test status
Simulation time 5560564138 ps
CPU time 4.28 seconds
Started Jul 26 06:51:03 PM PDT 24
Finished Jul 26 06:51:07 PM PDT 24
Peak memory 201020 kb
Host smart-5457faa6-9ae6-4467-a717-45821b507f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342759790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3342759790
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2184981312
Short name T538
Test name
Test status
Simulation time 33896220315 ps
CPU time 80.52 seconds
Started Jul 26 06:51:06 PM PDT 24
Finished Jul 26 06:52:26 PM PDT 24
Peak memory 200996 kb
Host smart-bb57b499-6ae0-4a03-ba35-c570ff707ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184981312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2184981312
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2629924675
Short name T348
Test name
Test status
Simulation time 471508187 ps
CPU time 1.58 seconds
Started Jul 26 06:49:28 PM PDT 24
Finished Jul 26 06:49:30 PM PDT 24
Peak memory 200960 kb
Host smart-efeec107-08e8-47dd-8d9b-0e3063677986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629924675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2629924675
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2806469583
Short name T556
Test name
Test status
Simulation time 162801671165 ps
CPU time 350.25 seconds
Started Jul 26 06:49:23 PM PDT 24
Finished Jul 26 06:55:14 PM PDT 24
Peak memory 201304 kb
Host smart-14116670-dd3e-41e1-b89a-c5e273d38389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806469583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2806469583
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1778318493
Short name T702
Test name
Test status
Simulation time 487366631310 ps
CPU time 1128.86 seconds
Started Jul 26 06:49:27 PM PDT 24
Finished Jul 26 07:08:16 PM PDT 24
Peak memory 201148 kb
Host smart-6d1e57cc-392d-42c7-a1ee-0576320142c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778318493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1778318493
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1795998141
Short name T234
Test name
Test status
Simulation time 333985137122 ps
CPU time 775.29 seconds
Started Jul 26 06:49:28 PM PDT 24
Finished Jul 26 07:02:23 PM PDT 24
Peak memory 201236 kb
Host smart-1c14cf02-cba8-42a7-9351-ca389836c5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795998141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1795998141
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3800599859
Short name T503
Test name
Test status
Simulation time 323609517545 ps
CPU time 760.73 seconds
Started Jul 26 06:49:26 PM PDT 24
Finished Jul 26 07:02:07 PM PDT 24
Peak memory 201200 kb
Host smart-048c3cf4-cfd9-4f4a-8a5d-b80cc7da0c89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800599859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3800599859
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1315698721
Short name T711
Test name
Test status
Simulation time 189163726462 ps
CPU time 220.99 seconds
Started Jul 26 06:49:27 PM PDT 24
Finished Jul 26 06:53:08 PM PDT 24
Peak memory 201168 kb
Host smart-6f226faa-bc72-4def-b936-1e88de933b60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315698721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1315698721
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1439308865
Short name T525
Test name
Test status
Simulation time 211577629896 ps
CPU time 118.98 seconds
Started Jul 26 06:49:29 PM PDT 24
Finished Jul 26 06:51:28 PM PDT 24
Peak memory 201128 kb
Host smart-21168624-5aa1-431a-9d63-76f25a8ab9b3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439308865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1439308865
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3705064829
Short name T500
Test name
Test status
Simulation time 105436551013 ps
CPU time 545.25 seconds
Started Jul 26 06:49:28 PM PDT 24
Finished Jul 26 06:58:33 PM PDT 24
Peak memory 201612 kb
Host smart-dfac00a9-026e-4ec5-9f03-67e18aafec96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705064829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3705064829
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.4003021027
Short name T788
Test name
Test status
Simulation time 33183158429 ps
CPU time 41.13 seconds
Started Jul 26 06:49:26 PM PDT 24
Finished Jul 26 06:50:08 PM PDT 24
Peak memory 200984 kb
Host smart-b29b8934-6e2e-4801-9204-93ad103bce42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003021027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.4003021027
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2821908839
Short name T717
Test name
Test status
Simulation time 4305459055 ps
CPU time 10.26 seconds
Started Jul 26 06:49:28 PM PDT 24
Finished Jul 26 06:49:39 PM PDT 24
Peak memory 201008 kb
Host smart-db4bcc26-4b0a-41bd-92da-87968cff84cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821908839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2821908839
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2217737437
Short name T73
Test name
Test status
Simulation time 4025132590 ps
CPU time 6.93 seconds
Started Jul 26 06:49:25 PM PDT 24
Finished Jul 26 06:49:32 PM PDT 24
Peak memory 216812 kb
Host smart-58484b2b-9671-4743-90ac-d9398265a33f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217737437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2217737437
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2290587373
Short name T709
Test name
Test status
Simulation time 5822592747 ps
CPU time 4.08 seconds
Started Jul 26 06:49:26 PM PDT 24
Finished Jul 26 06:49:30 PM PDT 24
Peak memory 201004 kb
Host smart-2e943f27-791d-4f93-9352-ccc4dd1dd6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290587373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2290587373
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1362826127
Short name T662
Test name
Test status
Simulation time 171165840641 ps
CPU time 391.01 seconds
Started Jul 26 06:49:25 PM PDT 24
Finished Jul 26 06:55:56 PM PDT 24
Peak memory 201256 kb
Host smart-4c8528bb-a6ca-4191-84ad-384a2c2d6d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362826127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1362826127
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3851598437
Short name T56
Test name
Test status
Simulation time 596861779025 ps
CPU time 180.78 seconds
Started Jul 26 06:49:26 PM PDT 24
Finished Jul 26 06:52:27 PM PDT 24
Peak memory 209568 kb
Host smart-66194372-98a7-4093-8d55-f38aef52675d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851598437 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3851598437
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1759440967
Short name T359
Test name
Test status
Simulation time 401956445 ps
CPU time 1.51 seconds
Started Jul 26 06:51:13 PM PDT 24
Finished Jul 26 06:51:14 PM PDT 24
Peak memory 201012 kb
Host smart-e739c1e3-5901-4d9a-b3f1-e049bea9bc2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759440967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1759440967
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2790151121
Short name T663
Test name
Test status
Simulation time 181572374500 ps
CPU time 364.31 seconds
Started Jul 26 06:51:10 PM PDT 24
Finished Jul 26 06:57:14 PM PDT 24
Peak memory 201132 kb
Host smart-c7789a1e-35ee-48f9-948a-0eedf465ba59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790151121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2790151121
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2975936724
Short name T323
Test name
Test status
Simulation time 531752219622 ps
CPU time 1226.48 seconds
Started Jul 26 06:51:12 PM PDT 24
Finished Jul 26 07:11:39 PM PDT 24
Peak memory 201208 kb
Host smart-27dd17d6-b199-4f79-af21-3e687e862cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975936724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2975936724
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.262961854
Short name T590
Test name
Test status
Simulation time 173901893471 ps
CPU time 106.38 seconds
Started Jul 26 06:51:12 PM PDT 24
Finished Jul 26 06:52:59 PM PDT 24
Peak memory 201136 kb
Host smart-ec8eed1d-b57c-493e-a36c-aa81c7af7587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262961854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.262961854
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3813308130
Short name T780
Test name
Test status
Simulation time 497719277979 ps
CPU time 1110.87 seconds
Started Jul 26 06:51:10 PM PDT 24
Finished Jul 26 07:09:41 PM PDT 24
Peak memory 201196 kb
Host smart-da47802f-0e31-4261-baa5-d3718c060b6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813308130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3813308130
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3346906699
Short name T330
Test name
Test status
Simulation time 167310475458 ps
CPU time 133.24 seconds
Started Jul 26 06:51:05 PM PDT 24
Finished Jul 26 06:53:18 PM PDT 24
Peak memory 201152 kb
Host smart-484643eb-253e-4c70-a94a-f0a11a077fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346906699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3346906699
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.4262809695
Short name T426
Test name
Test status
Simulation time 333430743883 ps
CPU time 802.72 seconds
Started Jul 26 06:51:12 PM PDT 24
Finished Jul 26 07:04:34 PM PDT 24
Peak memory 201160 kb
Host smart-a6c62b14-abcf-4622-aa06-b7947568d15c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262809695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.4262809695
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.595622752
Short name T311
Test name
Test status
Simulation time 170533680179 ps
CPU time 404.98 seconds
Started Jul 26 06:51:11 PM PDT 24
Finished Jul 26 06:57:56 PM PDT 24
Peak memory 201164 kb
Host smart-ec781986-eccb-41b8-ba3b-d517ec23dc86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595622752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.595622752
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3893117843
Short name T448
Test name
Test status
Simulation time 414034576160 ps
CPU time 233.78 seconds
Started Jul 26 06:51:12 PM PDT 24
Finished Jul 26 06:55:06 PM PDT 24
Peak memory 201120 kb
Host smart-5fac2bdb-417b-46dd-a0b9-a96c40cb0051
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893117843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3893117843
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3314056326
Short name T687
Test name
Test status
Simulation time 66801396643 ps
CPU time 269.39 seconds
Started Jul 26 06:51:12 PM PDT 24
Finished Jul 26 06:55:42 PM PDT 24
Peak memory 201584 kb
Host smart-a7ce11c5-1686-4aba-b541-d53b2b41e403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314056326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3314056326
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2475413233
Short name T608
Test name
Test status
Simulation time 34352584703 ps
CPU time 79.49 seconds
Started Jul 26 06:51:11 PM PDT 24
Finished Jul 26 06:52:30 PM PDT 24
Peak memory 201008 kb
Host smart-1c3325c0-6d09-4f85-8dc7-e2813100d648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475413233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2475413233
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.4079431627
Short name T419
Test name
Test status
Simulation time 3470643977 ps
CPU time 2.71 seconds
Started Jul 26 06:51:11 PM PDT 24
Finished Jul 26 06:51:14 PM PDT 24
Peak memory 201040 kb
Host smart-df8902e3-e38f-4fdb-9bf7-d5a229020ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079431627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.4079431627
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3824526351
Short name T392
Test name
Test status
Simulation time 5901012151 ps
CPU time 14.28 seconds
Started Jul 26 06:51:04 PM PDT 24
Finished Jul 26 06:51:18 PM PDT 24
Peak memory 201072 kb
Host smart-9e402259-7ac4-48c2-85f7-e87dbf9f3527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824526351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3824526351
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1001137810
Short name T660
Test name
Test status
Simulation time 455219426 ps
CPU time 1.66 seconds
Started Jul 26 06:51:26 PM PDT 24
Finished Jul 26 06:51:28 PM PDT 24
Peak memory 200924 kb
Host smart-0b2743a8-3f27-4483-97fe-40a333762cd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001137810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1001137810
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2212665271
Short name T248
Test name
Test status
Simulation time 499433795985 ps
CPU time 196.23 seconds
Started Jul 26 06:51:18 PM PDT 24
Finished Jul 26 06:54:34 PM PDT 24
Peak memory 201136 kb
Host smart-6c330eac-2b25-4363-9798-20f067a384f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212665271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2212665271
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.934093412
Short name T483
Test name
Test status
Simulation time 361829189166 ps
CPU time 787.28 seconds
Started Jul 26 06:51:18 PM PDT 24
Finished Jul 26 07:04:26 PM PDT 24
Peak memory 201172 kb
Host smart-6ac9b8e7-ffd0-449d-8c1a-5abde114c0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934093412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.934093412
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3325456134
Short name T768
Test name
Test status
Simulation time 333567201787 ps
CPU time 205.55 seconds
Started Jul 26 06:51:15 PM PDT 24
Finished Jul 26 06:54:40 PM PDT 24
Peak memory 201252 kb
Host smart-e8b59cab-035e-4da3-8e6b-461c338be0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325456134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3325456134
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1386684460
Short name T188
Test name
Test status
Simulation time 331733991680 ps
CPU time 212.28 seconds
Started Jul 26 06:51:18 PM PDT 24
Finished Jul 26 06:54:51 PM PDT 24
Peak memory 201160 kb
Host smart-cb5abdb2-3551-4202-99c0-1ca76d78d4f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386684460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1386684460
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2811755675
Short name T321
Test name
Test status
Simulation time 163086988560 ps
CPU time 92.4 seconds
Started Jul 26 06:51:10 PM PDT 24
Finished Jul 26 06:52:43 PM PDT 24
Peak memory 201152 kb
Host smart-dae77d3c-d7cb-4f88-a43d-9750403fc80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811755675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2811755675
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3407802269
Short name T346
Test name
Test status
Simulation time 490676700372 ps
CPU time 608.95 seconds
Started Jul 26 06:51:10 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 201152 kb
Host smart-a11c3710-ae52-4ae1-bbcc-c1d240599249
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407802269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3407802269
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1698587430
Short name T697
Test name
Test status
Simulation time 192244379558 ps
CPU time 112.74 seconds
Started Jul 26 06:51:19 PM PDT 24
Finished Jul 26 06:53:11 PM PDT 24
Peak memory 201248 kb
Host smart-05ac2b9e-2160-42ac-8fd3-5ffa5b543010
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698587430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1698587430
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3936291279
Short name T494
Test name
Test status
Simulation time 588556971709 ps
CPU time 1341.04 seconds
Started Jul 26 06:51:21 PM PDT 24
Finished Jul 26 07:13:42 PM PDT 24
Peak memory 201140 kb
Host smart-1971b150-dbef-4502-9066-95c5bc6f2aca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936291279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3936291279
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.513581368
Short name T79
Test name
Test status
Simulation time 102114538600 ps
CPU time 316.47 seconds
Started Jul 26 06:51:27 PM PDT 24
Finished Jul 26 06:56:44 PM PDT 24
Peak memory 201672 kb
Host smart-5cc9b819-0310-4193-acc4-ebef24f87259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513581368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.513581368
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2692634106
Short name T442
Test name
Test status
Simulation time 37649774143 ps
CPU time 89.38 seconds
Started Jul 26 06:51:27 PM PDT 24
Finished Jul 26 06:52:57 PM PDT 24
Peak memory 200956 kb
Host smart-f5d8ccb3-b797-4f0d-8b64-76cf885d5dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692634106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2692634106
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1934254239
Short name T93
Test name
Test status
Simulation time 5106913515 ps
CPU time 7.03 seconds
Started Jul 26 06:51:18 PM PDT 24
Finished Jul 26 06:51:25 PM PDT 24
Peak memory 200952 kb
Host smart-eca46a5e-ccf4-48bd-b2a3-7675ca23ddab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934254239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1934254239
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.853259005
Short name T581
Test name
Test status
Simulation time 5990106564 ps
CPU time 8.06 seconds
Started Jul 26 06:51:13 PM PDT 24
Finished Jul 26 06:51:21 PM PDT 24
Peak memory 201096 kb
Host smart-8465f843-1d00-46da-bab2-cf003955a932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853259005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.853259005
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1941530711
Short name T26
Test name
Test status
Simulation time 342093918376 ps
CPU time 798.14 seconds
Started Jul 26 06:51:26 PM PDT 24
Finished Jul 26 07:04:44 PM PDT 24
Peak memory 201112 kb
Host smart-a4378ce7-e3ad-4a93-a9e9-373118c35a3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941530711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1941530711
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1267292557
Short name T21
Test name
Test status
Simulation time 98544659346 ps
CPU time 102.49 seconds
Started Jul 26 06:51:29 PM PDT 24
Finished Jul 26 06:53:11 PM PDT 24
Peak memory 209524 kb
Host smart-077f59b9-a543-440f-b45f-c2fbd587ead8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267292557 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1267292557
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4207706847
Short name T576
Test name
Test status
Simulation time 355724123 ps
CPU time 0.89 seconds
Started Jul 26 06:51:37 PM PDT 24
Finished Jul 26 06:51:38 PM PDT 24
Peak memory 200976 kb
Host smart-0f74dc21-aef0-4c3e-9504-702f08dddd74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207706847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4207706847
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1225393809
Short name T715
Test name
Test status
Simulation time 347578817188 ps
CPU time 814.86 seconds
Started Jul 26 06:51:27 PM PDT 24
Finished Jul 26 07:05:02 PM PDT 24
Peak memory 201016 kb
Host smart-8a77944c-68e8-4b2a-a60e-5ff7214106a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225393809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1225393809
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3807369328
Short name T689
Test name
Test status
Simulation time 488630030968 ps
CPU time 282.73 seconds
Started Jul 26 06:51:28 PM PDT 24
Finished Jul 26 06:56:11 PM PDT 24
Peak memory 201244 kb
Host smart-a4742327-73fa-41e8-aaba-c16d5f6412ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807369328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3807369328
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3349976734
Short name T770
Test name
Test status
Simulation time 328129876796 ps
CPU time 212.23 seconds
Started Jul 26 06:51:29 PM PDT 24
Finished Jul 26 06:55:01 PM PDT 24
Peak memory 201180 kb
Host smart-d112b311-7cf5-43d9-b73f-311c401dd85e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349976734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3349976734
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3958893097
Short name T252
Test name
Test status
Simulation time 164081881850 ps
CPU time 374.63 seconds
Started Jul 26 06:51:27 PM PDT 24
Finished Jul 26 06:57:41 PM PDT 24
Peak memory 201176 kb
Host smart-19fb8de3-3411-45c1-850c-1204d28fdac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958893097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3958893097
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3158431243
Short name T381
Test name
Test status
Simulation time 490534521694 ps
CPU time 297.32 seconds
Started Jul 26 06:51:24 PM PDT 24
Finished Jul 26 06:56:22 PM PDT 24
Peak memory 201184 kb
Host smart-efdf5f9e-e498-4ac1-b48e-fc2529d641d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158431243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3158431243
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.255016143
Short name T76
Test name
Test status
Simulation time 408326438682 ps
CPU time 428.03 seconds
Started Jul 26 06:51:28 PM PDT 24
Finished Jul 26 06:58:36 PM PDT 24
Peak memory 201148 kb
Host smart-5f42e1cd-68e3-4f02-8857-4180e82778c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255016143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.255016143
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.816916621
Short name T203
Test name
Test status
Simulation time 91631553449 ps
CPU time 521.93 seconds
Started Jul 26 06:51:37 PM PDT 24
Finished Jul 26 07:00:19 PM PDT 24
Peak memory 201616 kb
Host smart-c3902ce6-e550-4fe7-a688-a31ae292da54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816916621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.816916621
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3962394843
Short name T720
Test name
Test status
Simulation time 23658172130 ps
CPU time 11.26 seconds
Started Jul 26 06:51:36 PM PDT 24
Finished Jul 26 06:51:47 PM PDT 24
Peak memory 201008 kb
Host smart-5391406e-2fc5-4728-a8b9-d6d32c2f0032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962394843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3962394843
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2193127449
Short name T531
Test name
Test status
Simulation time 4295596282 ps
CPU time 11.14 seconds
Started Jul 26 06:51:34 PM PDT 24
Finished Jul 26 06:51:45 PM PDT 24
Peak memory 201060 kb
Host smart-edda50b9-5687-40e0-8077-b68ab09f2102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193127449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2193127449
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.192912243
Short name T561
Test name
Test status
Simulation time 5787284877 ps
CPU time 2.41 seconds
Started Jul 26 06:51:28 PM PDT 24
Finished Jul 26 06:51:30 PM PDT 24
Peak memory 201092 kb
Host smart-54b55225-ef59-4f95-9be8-a43ffe7b4833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192912243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.192912243
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3434411285
Short name T238
Test name
Test status
Simulation time 352286756527 ps
CPU time 620.61 seconds
Started Jul 26 06:51:34 PM PDT 24
Finished Jul 26 07:01:55 PM PDT 24
Peak memory 201188 kb
Host smart-d0dfb847-ed76-4621-81b5-e520bc49a9ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434411285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3434411285
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.4276208692
Short name T604
Test name
Test status
Simulation time 399302174 ps
CPU time 0.85 seconds
Started Jul 26 06:51:45 PM PDT 24
Finished Jul 26 06:51:46 PM PDT 24
Peak memory 200960 kb
Host smart-015fe394-b89d-4917-a65b-f8d3077327f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276208692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.4276208692
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2414560140
Short name T790
Test name
Test status
Simulation time 167176222512 ps
CPU time 88.98 seconds
Started Jul 26 06:51:36 PM PDT 24
Finished Jul 26 06:53:05 PM PDT 24
Peak memory 201172 kb
Host smart-25f8e200-6081-4fc1-bc29-68fb6d80c0da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414560140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2414560140
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.372087884
Short name T578
Test name
Test status
Simulation time 170363027782 ps
CPU time 179.63 seconds
Started Jul 26 06:51:38 PM PDT 24
Finished Jul 26 06:54:37 PM PDT 24
Peak memory 201136 kb
Host smart-8c32e85a-21cc-43c9-a26f-611856f87d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372087884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.372087884
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3427558449
Short name T415
Test name
Test status
Simulation time 324099328849 ps
CPU time 744.38 seconds
Started Jul 26 06:51:36 PM PDT 24
Finished Jul 26 07:04:00 PM PDT 24
Peak memory 201204 kb
Host smart-8795a5f0-53b6-42f7-973a-cc4408334bb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427558449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3427558449
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1127593102
Short name T82
Test name
Test status
Simulation time 393365328078 ps
CPU time 210.41 seconds
Started Jul 26 06:51:36 PM PDT 24
Finished Jul 26 06:55:07 PM PDT 24
Peak memory 201248 kb
Host smart-f2d351b6-7df3-4dca-aded-b07ffc5554e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127593102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1127593102
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3956881344
Short name T795
Test name
Test status
Simulation time 403151290682 ps
CPU time 497.46 seconds
Started Jul 26 06:51:37 PM PDT 24
Finished Jul 26 06:59:55 PM PDT 24
Peak memory 201132 kb
Host smart-43858cea-94f2-4902-b04b-743f8620d1f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956881344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3956881344
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1292259771
Short name T765
Test name
Test status
Simulation time 73792538525 ps
CPU time 403.85 seconds
Started Jul 26 06:51:43 PM PDT 24
Finished Jul 26 06:58:27 PM PDT 24
Peak memory 201920 kb
Host smart-c0dedf2e-e582-449a-a2ee-c85dc207f105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292259771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1292259771
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3020094513
Short name T693
Test name
Test status
Simulation time 24069758239 ps
CPU time 13.81 seconds
Started Jul 26 06:52:07 PM PDT 24
Finished Jul 26 06:52:21 PM PDT 24
Peak memory 200920 kb
Host smart-211b58eb-abb3-43a8-ae2d-da58101b3620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020094513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3020094513
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2090667817
Short name T586
Test name
Test status
Simulation time 3840338530 ps
CPU time 2.87 seconds
Started Jul 26 06:51:45 PM PDT 24
Finished Jul 26 06:51:48 PM PDT 24
Peak memory 200976 kb
Host smart-e4a38774-40b1-4f70-87e3-939df0a7b18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090667817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2090667817
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.186559311
Short name T371
Test name
Test status
Simulation time 5714209504 ps
CPU time 14.05 seconds
Started Jul 26 06:51:37 PM PDT 24
Finished Jul 26 06:51:51 PM PDT 24
Peak memory 201056 kb
Host smart-7bb0e2b2-14cc-459b-b6f8-0aeebb5ef610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186559311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.186559311
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.355076417
Short name T316
Test name
Test status
Simulation time 174478968664 ps
CPU time 108.51 seconds
Started Jul 26 06:51:45 PM PDT 24
Finished Jul 26 06:53:34 PM PDT 24
Peak memory 201172 kb
Host smart-64e0f9c5-45ef-4c32-b072-06badef4b7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355076417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
355076417
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2281388379
Short name T158
Test name
Test status
Simulation time 121994344887 ps
CPU time 175.05 seconds
Started Jul 26 06:51:44 PM PDT 24
Finished Jul 26 06:54:39 PM PDT 24
Peak memory 217128 kb
Host smart-28203cd2-fcc9-4fe1-970e-809288c2d5ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281388379 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2281388379
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3523243829
Short name T753
Test name
Test status
Simulation time 492386575 ps
CPU time 1.69 seconds
Started Jul 26 06:51:56 PM PDT 24
Finished Jul 26 06:51:57 PM PDT 24
Peak memory 200968 kb
Host smart-af15e484-d6dc-4e7c-8036-0f6990df304d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523243829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3523243829
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2391274536
Short name T558
Test name
Test status
Simulation time 173313257598 ps
CPU time 92.81 seconds
Started Jul 26 06:51:54 PM PDT 24
Finished Jul 26 06:53:27 PM PDT 24
Peak memory 201212 kb
Host smart-d202b44e-1d14-4910-8bc6-92ee1bf3525c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391274536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2391274536
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1008806597
Short name T192
Test name
Test status
Simulation time 346215039249 ps
CPU time 199.51 seconds
Started Jul 26 06:51:54 PM PDT 24
Finished Jul 26 06:55:13 PM PDT 24
Peak memory 201484 kb
Host smart-48a68152-b83f-4446-85fd-51ec0563e958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008806597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1008806597
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.540600050
Short name T13
Test name
Test status
Simulation time 328608351061 ps
CPU time 605.28 seconds
Started Jul 26 06:51:45 PM PDT 24
Finished Jul 26 07:01:50 PM PDT 24
Peak memory 201144 kb
Host smart-2fdee1a8-2dac-4bc5-b123-72216f438f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540600050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.540600050
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.177343674
Short name T369
Test name
Test status
Simulation time 160759447311 ps
CPU time 199.28 seconds
Started Jul 26 06:51:45 PM PDT 24
Finished Jul 26 06:55:05 PM PDT 24
Peak memory 201172 kb
Host smart-50c805c0-3a62-4171-b6e5-83af028b316c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=177343674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.177343674
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.361034509
Short name T740
Test name
Test status
Simulation time 329318409427 ps
CPU time 375.14 seconds
Started Jul 26 06:51:45 PM PDT 24
Finished Jul 26 06:58:00 PM PDT 24
Peak memory 201248 kb
Host smart-86979ead-d699-4aa9-815e-6fa5b4c6ef20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361034509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.361034509
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.4109509401
Short name T563
Test name
Test status
Simulation time 491938447160 ps
CPU time 239.03 seconds
Started Jul 26 06:51:43 PM PDT 24
Finished Jul 26 06:55:42 PM PDT 24
Peak memory 201164 kb
Host smart-fdb40b3e-32c7-429d-b6dd-ac33e2ba05e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109509401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.4109509401
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.4070465555
Short name T194
Test name
Test status
Simulation time 586139816341 ps
CPU time 322.94 seconds
Started Jul 26 06:51:53 PM PDT 24
Finished Jul 26 06:57:16 PM PDT 24
Peak memory 201200 kb
Host smart-173b9ea8-596c-45df-8bcb-948866f3095b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070465555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.4070465555
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.424777735
Short name T679
Test name
Test status
Simulation time 396251182069 ps
CPU time 424.76 seconds
Started Jul 26 06:51:53 PM PDT 24
Finished Jul 26 06:58:58 PM PDT 24
Peak memory 201164 kb
Host smart-bcfd3012-de84-4a56-9960-d203278b8f9f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424777735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.424777735
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.441613861
Short name T738
Test name
Test status
Simulation time 90389961145 ps
CPU time 382.45 seconds
Started Jul 26 06:51:54 PM PDT 24
Finished Jul 26 06:58:17 PM PDT 24
Peak memory 201628 kb
Host smart-c93fa41e-47d0-4468-990b-631fd3f1d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441613861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.441613861
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.332732905
Short name T140
Test name
Test status
Simulation time 24839696682 ps
CPU time 26.97 seconds
Started Jul 26 06:51:55 PM PDT 24
Finished Jul 26 06:52:22 PM PDT 24
Peak memory 200972 kb
Host smart-04343c4d-63ab-4b26-bd3c-f6b6fcb50a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332732905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.332732905
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.710893130
Short name T386
Test name
Test status
Simulation time 4782209287 ps
CPU time 11.31 seconds
Started Jul 26 06:51:56 PM PDT 24
Finished Jul 26 06:52:07 PM PDT 24
Peak memory 200956 kb
Host smart-bece49fb-4c76-4b64-9457-3e08db4366c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710893130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.710893130
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3546599513
Short name T133
Test name
Test status
Simulation time 5901881375 ps
CPU time 14.67 seconds
Started Jul 26 06:51:46 PM PDT 24
Finished Jul 26 06:52:01 PM PDT 24
Peak memory 201028 kb
Host smart-791ff494-69d1-43a0-a4e9-ff11c9e5ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546599513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3546599513
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1737916524
Short name T205
Test name
Test status
Simulation time 1522692479637 ps
CPU time 2007.08 seconds
Started Jul 26 06:51:55 PM PDT 24
Finished Jul 26 07:25:22 PM PDT 24
Peak memory 212632 kb
Host smart-a24ea2b1-18b3-471f-9c4b-5f5568c87043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737916524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1737916524
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1275258916
Short name T40
Test name
Test status
Simulation time 505720507820 ps
CPU time 187.94 seconds
Started Jul 26 06:51:56 PM PDT 24
Finished Jul 26 06:55:05 PM PDT 24
Peak memory 209992 kb
Host smart-c5bbe635-a3cf-4c9f-9e62-2709d5e9737c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275258916 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1275258916
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.500869500
Short name T536
Test name
Test status
Simulation time 430044683 ps
CPU time 0.73 seconds
Started Jul 26 06:52:13 PM PDT 24
Finished Jul 26 06:52:14 PM PDT 24
Peak memory 200964 kb
Host smart-3a0dc2d4-5b99-412a-a2fd-1f781791e1df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500869500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.500869500
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1835223524
Short name T148
Test name
Test status
Simulation time 353124338717 ps
CPU time 156.29 seconds
Started Jul 26 06:52:03 PM PDT 24
Finished Jul 26 06:54:40 PM PDT 24
Peak memory 201088 kb
Host smart-1122a177-a7b9-4139-a640-3e27f12c906e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835223524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1835223524
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.399577182
Short name T438
Test name
Test status
Simulation time 167986558786 ps
CPU time 397.18 seconds
Started Jul 26 06:52:03 PM PDT 24
Finished Jul 26 06:58:40 PM PDT 24
Peak memory 201180 kb
Host smart-83f2d432-1e25-49e0-af57-befbc966e3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399577182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.399577182
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3581773647
Short name T270
Test name
Test status
Simulation time 334328517111 ps
CPU time 202.94 seconds
Started Jul 26 06:51:53 PM PDT 24
Finished Jul 26 06:55:16 PM PDT 24
Peak memory 201252 kb
Host smart-86cb9f65-d2e9-4127-aa4c-fb80f75d780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581773647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3581773647
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.4208879450
Short name T430
Test name
Test status
Simulation time 486981295191 ps
CPU time 538.45 seconds
Started Jul 26 06:51:55 PM PDT 24
Finished Jul 26 07:00:53 PM PDT 24
Peak memory 201160 kb
Host smart-5278d6a2-ebbd-4cfb-9aae-cf171717b26f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208879450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.4208879450
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3960772394
Short name T475
Test name
Test status
Simulation time 487473078114 ps
CPU time 1073.08 seconds
Started Jul 26 06:51:54 PM PDT 24
Finished Jul 26 07:09:47 PM PDT 24
Peak memory 201176 kb
Host smart-e192b048-d9e3-4928-9316-1c4f5cea4acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960772394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3960772394
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.437003756
Short name T412
Test name
Test status
Simulation time 488821208052 ps
CPU time 1213.48 seconds
Started Jul 26 06:51:55 PM PDT 24
Finished Jul 26 07:12:08 PM PDT 24
Peak memory 201164 kb
Host smart-219df4df-623a-41e0-ae53-0bbc3bf5cfd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=437003756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.437003756
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2673490764
Short name T224
Test name
Test status
Simulation time 339425359833 ps
CPU time 720.82 seconds
Started Jul 26 06:52:03 PM PDT 24
Finished Jul 26 07:04:04 PM PDT 24
Peak memory 201156 kb
Host smart-da142bbf-3ff8-4ce5-b604-bc671f68e59a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673490764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2673490764
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1202454524
Short name T461
Test name
Test status
Simulation time 610889048366 ps
CPU time 1436.1 seconds
Started Jul 26 06:52:04 PM PDT 24
Finished Jul 26 07:16:01 PM PDT 24
Peak memory 201212 kb
Host smart-1ce94476-5890-4920-81f9-a03ab642d102
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202454524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1202454524
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1272451396
Short name T609
Test name
Test status
Simulation time 123278857846 ps
CPU time 530.34 seconds
Started Jul 26 06:52:13 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 201644 kb
Host smart-2b573af5-6955-4d4c-a14f-3e9bc2a0a388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272451396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1272451396
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2402860327
Short name T624
Test name
Test status
Simulation time 29892196206 ps
CPU time 20.73 seconds
Started Jul 26 06:52:12 PM PDT 24
Finished Jul 26 06:52:33 PM PDT 24
Peak memory 201020 kb
Host smart-e7259936-5303-4792-bd4d-c86d7327db7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402860327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2402860327
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.421869769
Short name T423
Test name
Test status
Simulation time 3013556969 ps
CPU time 4.1 seconds
Started Jul 26 06:52:19 PM PDT 24
Finished Jul 26 06:52:23 PM PDT 24
Peak memory 200980 kb
Host smart-b17003ca-4e0e-451f-8249-d994d998c24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421869769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.421869769
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1652408906
Short name T763
Test name
Test status
Simulation time 5911736115 ps
CPU time 4.21 seconds
Started Jul 26 06:51:54 PM PDT 24
Finished Jul 26 06:51:59 PM PDT 24
Peak memory 201044 kb
Host smart-f0612e0b-d9b5-4349-a2ce-6282fa04021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652408906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1652408906
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2903069651
Short name T443
Test name
Test status
Simulation time 316756451 ps
CPU time 0.82 seconds
Started Jul 26 06:52:23 PM PDT 24
Finished Jul 26 06:52:23 PM PDT 24
Peak memory 200952 kb
Host smart-b7ef3e43-ec5a-432c-bf06-c53067e7ed23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903069651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2903069651
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.4253846375
Short name T259
Test name
Test status
Simulation time 528396753419 ps
CPU time 612.97 seconds
Started Jul 26 06:52:23 PM PDT 24
Finished Jul 26 07:02:36 PM PDT 24
Peak memory 201212 kb
Host smart-702a80c3-873b-40a4-b046-cf919c75c094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253846375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.4253846375
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3549003009
Short name T137
Test name
Test status
Simulation time 330060778826 ps
CPU time 201.58 seconds
Started Jul 26 06:52:14 PM PDT 24
Finished Jul 26 06:55:36 PM PDT 24
Peak memory 201284 kb
Host smart-f95673aa-ac26-43fd-a9f5-93603d8d35c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549003009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3549003009
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3449275453
Short name T501
Test name
Test status
Simulation time 164617810698 ps
CPU time 104.41 seconds
Started Jul 26 06:52:14 PM PDT 24
Finished Jul 26 06:53:59 PM PDT 24
Peak memory 201152 kb
Host smart-a2849083-ee5f-4d94-b976-9211c1f4a061
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449275453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3449275453
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3378246633
Short name T156
Test name
Test status
Simulation time 162331069775 ps
CPU time 91 seconds
Started Jul 26 06:52:13 PM PDT 24
Finished Jul 26 06:53:44 PM PDT 24
Peak memory 201244 kb
Host smart-6cb76aae-ecec-4c4c-9c70-135cc4fd3c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378246633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3378246633
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1027230239
Short name T603
Test name
Test status
Simulation time 328535305475 ps
CPU time 801.77 seconds
Started Jul 26 06:52:13 PM PDT 24
Finished Jul 26 07:05:35 PM PDT 24
Peak memory 201180 kb
Host smart-9723e921-b022-4ccc-8d40-120d82540d21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027230239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1027230239
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.483852267
Short name T647
Test name
Test status
Simulation time 191902234895 ps
CPU time 463.94 seconds
Started Jul 26 06:52:18 PM PDT 24
Finished Jul 26 07:00:03 PM PDT 24
Peak memory 201228 kb
Host smart-ef2ece6f-5966-4e3e-af93-eb465d49928b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483852267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.483852267
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.897468582
Short name T614
Test name
Test status
Simulation time 408470720206 ps
CPU time 251.86 seconds
Started Jul 26 06:52:23 PM PDT 24
Finished Jul 26 06:56:35 PM PDT 24
Peak memory 201160 kb
Host smart-45630260-84dc-4431-b198-ed4c3a10fe84
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897468582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.897468582
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3835725691
Short name T573
Test name
Test status
Simulation time 86383497893 ps
CPU time 514.6 seconds
Started Jul 26 06:52:22 PM PDT 24
Finished Jul 26 07:00:56 PM PDT 24
Peak memory 201612 kb
Host smart-c15da9b9-4303-4ba4-866b-e97b7585f51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835725691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3835725691
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3737505688
Short name T596
Test name
Test status
Simulation time 40973187289 ps
CPU time 94.54 seconds
Started Jul 26 06:52:23 PM PDT 24
Finished Jul 26 06:53:58 PM PDT 24
Peak memory 201032 kb
Host smart-af29c61f-d596-4fd9-b50d-d289bc81389c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737505688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3737505688
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2168263808
Short name T766
Test name
Test status
Simulation time 5299966534 ps
CPU time 6.23 seconds
Started Jul 26 06:52:23 PM PDT 24
Finished Jul 26 06:52:29 PM PDT 24
Peak memory 201020 kb
Host smart-18aef231-15d2-40a4-9ec4-28f5b6ea44af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168263808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2168263808
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2245906238
Short name T372
Test name
Test status
Simulation time 5715511255 ps
CPU time 14.23 seconds
Started Jul 26 06:52:15 PM PDT 24
Finished Jul 26 06:52:30 PM PDT 24
Peak memory 201036 kb
Host smart-8e7ef058-5e63-4524-8972-6c9ccab3ed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245906238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2245906238
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3437813695
Short name T286
Test name
Test status
Simulation time 227302356829 ps
CPU time 528.84 seconds
Started Jul 26 06:52:26 PM PDT 24
Finished Jul 26 07:01:15 PM PDT 24
Peak memory 201184 kb
Host smart-1ddf767a-67ef-494b-aab0-93796df46364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437813695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3437813695
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3418210787
Short name T704
Test name
Test status
Simulation time 66892990851 ps
CPU time 186.72 seconds
Started Jul 26 06:52:21 PM PDT 24
Finished Jul 26 06:55:28 PM PDT 24
Peak memory 217584 kb
Host smart-c88e5fde-ce69-4faa-9ff5-cb963aa93fae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418210787 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3418210787
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3469422575
Short name T4
Test name
Test status
Simulation time 432078401 ps
CPU time 1.62 seconds
Started Jul 26 06:52:41 PM PDT 24
Finished Jul 26 06:52:43 PM PDT 24
Peak memory 201036 kb
Host smart-58da0b33-952e-4714-b123-b41013365268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469422575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3469422575
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3167737908
Short name T784
Test name
Test status
Simulation time 176211088501 ps
CPU time 301.07 seconds
Started Jul 26 06:52:34 PM PDT 24
Finished Jul 26 06:57:35 PM PDT 24
Peak memory 201152 kb
Host smart-c6801892-50c8-4853-bad0-857a3b39e758
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167737908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3167737908
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.414985926
Short name T132
Test name
Test status
Simulation time 373652308262 ps
CPU time 197.45 seconds
Started Jul 26 06:52:32 PM PDT 24
Finished Jul 26 06:55:49 PM PDT 24
Peak memory 201160 kb
Host smart-85db4a11-716a-49dc-a35a-fe910c5a555b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414985926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.414985926
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4108245043
Short name T519
Test name
Test status
Simulation time 328323360963 ps
CPU time 73.03 seconds
Started Jul 26 06:52:33 PM PDT 24
Finished Jul 26 06:53:46 PM PDT 24
Peak memory 201140 kb
Host smart-ba133c37-e01a-4380-b061-f9fff1c9f7a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108245043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.4108245043
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.538173726
Short name T686
Test name
Test status
Simulation time 170447698084 ps
CPU time 109.14 seconds
Started Jul 26 06:52:35 PM PDT 24
Finished Jul 26 06:54:24 PM PDT 24
Peak memory 201228 kb
Host smart-09583eff-ec21-4f4a-8374-08a3a082998b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538173726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.538173726
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4066012133
Short name T636
Test name
Test status
Simulation time 496781460894 ps
CPU time 134.61 seconds
Started Jul 26 06:52:32 PM PDT 24
Finished Jul 26 06:54:46 PM PDT 24
Peak memory 201144 kb
Host smart-7b5a8089-f8af-4cae-84cd-7b6aed11efa1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066012133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4066012133
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1292224356
Short name T793
Test name
Test status
Simulation time 351509478370 ps
CPU time 747.49 seconds
Started Jul 26 06:52:32 PM PDT 24
Finished Jul 26 07:04:59 PM PDT 24
Peak memory 201204 kb
Host smart-a34b3f3a-340a-4904-91de-fad97cf46344
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292224356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1292224356
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.302406782
Short name T626
Test name
Test status
Simulation time 195403622192 ps
CPU time 241.31 seconds
Started Jul 26 06:52:31 PM PDT 24
Finished Jul 26 06:56:33 PM PDT 24
Peak memory 201140 kb
Host smart-8531e5b0-265c-4284-8095-b940e785b429
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302406782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.302406782
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3195826435
Short name T92
Test name
Test status
Simulation time 83776501618 ps
CPU time 415.33 seconds
Started Jul 26 06:52:32 PM PDT 24
Finished Jul 26 06:59:27 PM PDT 24
Peak memory 201588 kb
Host smart-aaa1e9a1-d6a2-44fc-910b-3387eeb0ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195826435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3195826435
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1676658000
Short name T470
Test name
Test status
Simulation time 30031345269 ps
CPU time 44.44 seconds
Started Jul 26 06:52:31 PM PDT 24
Finished Jul 26 06:53:16 PM PDT 24
Peak memory 200972 kb
Host smart-44bb6f7d-45dc-4790-b825-fd930a144955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676658000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1676658000
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3867059252
Short name T643
Test name
Test status
Simulation time 4085862150 ps
CPU time 2.67 seconds
Started Jul 26 06:52:33 PM PDT 24
Finished Jul 26 06:52:36 PM PDT 24
Peak memory 201060 kb
Host smart-a239eef5-e42f-4f59-93c2-4923790fcca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867059252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3867059252
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2003221735
Short name T594
Test name
Test status
Simulation time 5998565953 ps
CPU time 13.66 seconds
Started Jul 26 06:52:21 PM PDT 24
Finished Jul 26 06:52:35 PM PDT 24
Peak memory 201032 kb
Host smart-aae4879a-cb8f-4bab-8622-1ec0b6ed2d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003221735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2003221735
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1063134808
Short name T454
Test name
Test status
Simulation time 374377344169 ps
CPU time 841.09 seconds
Started Jul 26 06:52:42 PM PDT 24
Finished Jul 26 07:06:44 PM PDT 24
Peak memory 201200 kb
Host smart-817cb6ab-e6d3-46d6-b905-d92c9777aa48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063134808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1063134808
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1338780469
Short name T108
Test name
Test status
Simulation time 224823059252 ps
CPU time 159.54 seconds
Started Jul 26 06:52:35 PM PDT 24
Finished Jul 26 06:55:14 PM PDT 24
Peak memory 218088 kb
Host smart-563765b5-7753-4217-80cb-0312d22e897b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338780469 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1338780469
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.4053836778
Short name T554
Test name
Test status
Simulation time 544939885 ps
CPU time 0.91 seconds
Started Jul 26 06:52:52 PM PDT 24
Finished Jul 26 06:52:53 PM PDT 24
Peak memory 200924 kb
Host smart-2d026148-b48c-4c1e-9df0-ca3cce6dc4b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053836778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.4053836778
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2897491332
Short name T168
Test name
Test status
Simulation time 424316403632 ps
CPU time 206.96 seconds
Started Jul 26 06:52:42 PM PDT 24
Finished Jul 26 06:56:09 PM PDT 24
Peak memory 201208 kb
Host smart-1bc2fc81-8166-4ca3-aae3-47de8c236181
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897491332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2897491332
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1859307016
Short name T262
Test name
Test status
Simulation time 331147025724 ps
CPU time 681.75 seconds
Started Jul 26 06:52:42 PM PDT 24
Finished Jul 26 07:04:03 PM PDT 24
Peak memory 201228 kb
Host smart-8100e5d5-83b2-4aaf-83d6-11b3741a8b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859307016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1859307016
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1509609153
Short name T772
Test name
Test status
Simulation time 319679267367 ps
CPU time 698.5 seconds
Started Jul 26 06:52:42 PM PDT 24
Finished Jul 26 07:04:20 PM PDT 24
Peak memory 201152 kb
Host smart-2370d212-c68c-4a18-86e4-cb7a59336fd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509609153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1509609153
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1086253157
Short name T181
Test name
Test status
Simulation time 496727689053 ps
CPU time 145.33 seconds
Started Jul 26 06:52:40 PM PDT 24
Finished Jul 26 06:55:06 PM PDT 24
Peak memory 201216 kb
Host smart-cbbf1148-2ce6-45f0-b62f-6484bcd1e01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086253157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1086253157
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3752364902
Short name T484
Test name
Test status
Simulation time 336476264162 ps
CPU time 785.46 seconds
Started Jul 26 06:52:42 PM PDT 24
Finished Jul 26 07:05:48 PM PDT 24
Peak memory 201208 kb
Host smart-6f9d8a51-0428-4e0c-a065-a90b5ec58077
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752364902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3752364902
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.289525265
Short name T172
Test name
Test status
Simulation time 517030134589 ps
CPU time 310.13 seconds
Started Jul 26 06:52:42 PM PDT 24
Finished Jul 26 06:57:52 PM PDT 24
Peak memory 201124 kb
Host smart-a842a6cd-3be5-4b71-9eca-29829d2f6d4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289525265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.289525265
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1526248708
Short name T507
Test name
Test status
Simulation time 194936973042 ps
CPU time 59.73 seconds
Started Jul 26 06:52:42 PM PDT 24
Finished Jul 26 06:53:42 PM PDT 24
Peak memory 201112 kb
Host smart-0ad234d3-7c97-40f3-9ced-1469bb08157b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526248708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1526248708
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2039120843
Short name T340
Test name
Test status
Simulation time 74849111537 ps
CPU time 269.23 seconds
Started Jul 26 06:52:51 PM PDT 24
Finished Jul 26 06:57:20 PM PDT 24
Peak memory 201680 kb
Host smart-b3b4acbd-bb41-496a-92b5-bd16fd248759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039120843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2039120843
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3786055636
Short name T499
Test name
Test status
Simulation time 44846973475 ps
CPU time 105.93 seconds
Started Jul 26 06:52:52 PM PDT 24
Finished Jul 26 06:54:38 PM PDT 24
Peak memory 201040 kb
Host smart-72ccc45a-245c-432c-9ec9-993dbf7d885f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786055636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3786055636
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1996017053
Short name T411
Test name
Test status
Simulation time 3924387576 ps
CPU time 3.22 seconds
Started Jul 26 06:52:58 PM PDT 24
Finished Jul 26 06:53:01 PM PDT 24
Peak memory 200980 kb
Host smart-334a0ede-77d9-412e-a4ef-e4e53fe887bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996017053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1996017053
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.4140245810
Short name T361
Test name
Test status
Simulation time 5848611113 ps
CPU time 7.77 seconds
Started Jul 26 06:52:43 PM PDT 24
Finished Jul 26 06:52:51 PM PDT 24
Peak memory 201028 kb
Host smart-636c742d-2385-4173-9216-436cfaa77606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140245810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.4140245810
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.839280974
Short name T785
Test name
Test status
Simulation time 260696093536 ps
CPU time 432.87 seconds
Started Jul 26 06:52:53 PM PDT 24
Finished Jul 26 07:00:06 PM PDT 24
Peak memory 201620 kb
Host smart-b1e1e12e-0529-45de-9753-f6cea10bcc48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839280974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
839280974
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1043826760
Short name T791
Test name
Test status
Simulation time 77865738438 ps
CPU time 40.93 seconds
Started Jul 26 06:52:52 PM PDT 24
Finished Jul 26 06:53:33 PM PDT 24
Peak memory 201360 kb
Host smart-ef7d5c23-62d6-4230-9b57-a306504a7e8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043826760 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1043826760
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3961822047
Short name T366
Test name
Test status
Simulation time 362596573 ps
CPU time 0.82 seconds
Started Jul 26 06:53:06 PM PDT 24
Finished Jul 26 06:53:07 PM PDT 24
Peak memory 200944 kb
Host smart-defbe640-57c8-4b33-9489-b9d1823bc91c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961822047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3961822047
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1672331852
Short name T431
Test name
Test status
Simulation time 163010656436 ps
CPU time 92.16 seconds
Started Jul 26 06:53:07 PM PDT 24
Finished Jul 26 06:54:39 PM PDT 24
Peak memory 201236 kb
Host smart-eecffad9-2ef5-4b89-81a4-042dbc873708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672331852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1672331852
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.853662835
Short name T280
Test name
Test status
Simulation time 489609091530 ps
CPU time 1179.74 seconds
Started Jul 26 06:53:07 PM PDT 24
Finished Jul 26 07:12:47 PM PDT 24
Peak memory 201168 kb
Host smart-86d46d4f-dfad-45f3-b2ed-4931ddc62897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853662835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.853662835
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2591509337
Short name T512
Test name
Test status
Simulation time 163269908587 ps
CPU time 274.54 seconds
Started Jul 26 06:53:07 PM PDT 24
Finished Jul 26 06:57:42 PM PDT 24
Peak memory 201168 kb
Host smart-ace93f21-3034-4dd2-99d7-82ab00e15f68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591509337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2591509337
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.738050241
Short name T291
Test name
Test status
Simulation time 161972057663 ps
CPU time 360.19 seconds
Started Jul 26 06:52:54 PM PDT 24
Finished Jul 26 06:58:54 PM PDT 24
Peak memory 201232 kb
Host smart-4d7fde2f-25f1-4f4c-9dde-f3b34ae9cb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738050241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.738050241
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1637093230
Short name T102
Test name
Test status
Simulation time 165073772581 ps
CPU time 101.37 seconds
Started Jul 26 06:52:51 PM PDT 24
Finished Jul 26 06:54:32 PM PDT 24
Peak memory 201304 kb
Host smart-5a6902f8-4138-4eaf-a06f-f4b4db87b569
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637093230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1637093230
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2973849766
Short name T271
Test name
Test status
Simulation time 359477893891 ps
CPU time 713.61 seconds
Started Jul 26 06:53:07 PM PDT 24
Finished Jul 26 07:05:01 PM PDT 24
Peak memory 201168 kb
Host smart-e932caec-a6ef-49f8-a210-0dbb55183e2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973849766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2973849766
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.272251902
Short name T767
Test name
Test status
Simulation time 420942603135 ps
CPU time 408.44 seconds
Started Jul 26 06:53:06 PM PDT 24
Finished Jul 26 06:59:55 PM PDT 24
Peak memory 201128 kb
Host smart-1ad47a72-6d04-4514-bf77-dff0af30b9ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272251902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.272251902
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2273434821
Short name T803
Test name
Test status
Simulation time 82305746332 ps
CPU time 247.82 seconds
Started Jul 26 06:53:06 PM PDT 24
Finished Jul 26 06:57:14 PM PDT 24
Peak memory 201628 kb
Host smart-b5346116-3ad2-4939-bfbf-4450517a6fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273434821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2273434821
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1784927653
Short name T496
Test name
Test status
Simulation time 38270319669 ps
CPU time 89.73 seconds
Started Jul 26 06:53:05 PM PDT 24
Finished Jul 26 06:54:35 PM PDT 24
Peak memory 201044 kb
Host smart-1ff12346-e765-42c6-99a3-b663a2d6387d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784927653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1784927653
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2257673718
Short name T344
Test name
Test status
Simulation time 3476292365 ps
CPU time 2.8 seconds
Started Jul 26 06:53:07 PM PDT 24
Finished Jul 26 06:53:10 PM PDT 24
Peak memory 200900 kb
Host smart-88277ce7-aab4-4c18-bcbc-da8acd97a7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257673718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2257673718
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3103349600
Short name T350
Test name
Test status
Simulation time 6025168757 ps
CPU time 8.08 seconds
Started Jul 26 06:52:52 PM PDT 24
Finished Jul 26 06:53:00 PM PDT 24
Peak memory 201044 kb
Host smart-5f1a9778-e130-49df-b542-da30573f7a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103349600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3103349600
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2280655122
Short name T541
Test name
Test status
Simulation time 375675849191 ps
CPU time 409.42 seconds
Started Jul 26 06:53:06 PM PDT 24
Finished Jul 26 06:59:56 PM PDT 24
Peak memory 201196 kb
Host smart-970ce326-6306-4130-800e-a30f725a940d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280655122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2280655122
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.4191470430
Short name T559
Test name
Test status
Simulation time 477620989 ps
CPU time 0.89 seconds
Started Jul 26 06:49:34 PM PDT 24
Finished Jul 26 06:49:35 PM PDT 24
Peak memory 200980 kb
Host smart-51535b0b-f2b5-4fb8-bf93-b3f845d067b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191470430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.4191470430
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.49169404
Short name T219
Test name
Test status
Simulation time 340096303485 ps
CPU time 77.96 seconds
Started Jul 26 06:49:25 PM PDT 24
Finished Jul 26 06:50:43 PM PDT 24
Peak memory 201316 kb
Host smart-10c30376-a4c0-457b-80d1-2615fbc51a2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49169404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating
.49169404
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.4042551308
Short name T269
Test name
Test status
Simulation time 165227180217 ps
CPU time 186.22 seconds
Started Jul 26 06:49:24 PM PDT 24
Finished Jul 26 06:52:30 PM PDT 24
Peak memory 201132 kb
Host smart-228f7877-304d-41a8-a2d6-4fdc97811526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042551308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.4042551308
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.4215465535
Short name T95
Test name
Test status
Simulation time 497143577409 ps
CPU time 967.39 seconds
Started Jul 26 06:49:26 PM PDT 24
Finished Jul 26 07:05:34 PM PDT 24
Peak memory 201208 kb
Host smart-1e76965c-669a-4f8f-8f9e-9d904cef0efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215465535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.4215465535
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3643617910
Short name T469
Test name
Test status
Simulation time 165834439984 ps
CPU time 204.36 seconds
Started Jul 26 06:49:25 PM PDT 24
Finished Jul 26 06:52:50 PM PDT 24
Peak memory 201116 kb
Host smart-c4a38031-2ba7-4710-9e04-d836199fb71f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643617910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3643617910
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2966962539
Short name T635
Test name
Test status
Simulation time 162764141587 ps
CPU time 56.05 seconds
Started Jul 26 06:49:28 PM PDT 24
Finished Jul 26 06:50:24 PM PDT 24
Peak memory 201216 kb
Host smart-51cdc60d-4106-4eb6-aba6-796eccb164a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966962539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2966962539
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.112062626
Short name T455
Test name
Test status
Simulation time 169960887809 ps
CPU time 380.73 seconds
Started Jul 26 06:49:26 PM PDT 24
Finished Jul 26 06:55:47 PM PDT 24
Peak memory 201144 kb
Host smart-31ac1284-90f2-464f-bc67-ff591dd55021
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112062626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.112062626
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.831434894
Short name T383
Test name
Test status
Simulation time 405400149542 ps
CPU time 878.06 seconds
Started Jul 26 06:49:27 PM PDT 24
Finished Jul 26 07:04:06 PM PDT 24
Peak memory 201264 kb
Host smart-cd735ea3-09ed-4977-8760-85050845697e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831434894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.831434894
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3071492557
Short name T338
Test name
Test status
Simulation time 117426277984 ps
CPU time 344.32 seconds
Started Jul 26 06:49:38 PM PDT 24
Finished Jul 26 06:55:22 PM PDT 24
Peak memory 201656 kb
Host smart-6e45de2a-5310-4d50-aec9-8152d5cdcb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071492557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3071492557
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3046089509
Short name T601
Test name
Test status
Simulation time 42288028286 ps
CPU time 24.37 seconds
Started Jul 26 06:49:33 PM PDT 24
Finished Jul 26 06:49:58 PM PDT 24
Peak memory 201012 kb
Host smart-cb6a7a6b-59c8-48a4-8649-ef78810e3a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046089509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3046089509
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3694863688
Short name T458
Test name
Test status
Simulation time 5194010137 ps
CPU time 12.74 seconds
Started Jul 26 06:49:33 PM PDT 24
Finished Jul 26 06:49:46 PM PDT 24
Peak memory 200960 kb
Host smart-11ad83a2-d913-499d-84e7-e1ce1c1e63b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694863688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3694863688
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2520390201
Short name T74
Test name
Test status
Simulation time 8784844153 ps
CPU time 9.65 seconds
Started Jul 26 06:49:38 PM PDT 24
Finished Jul 26 06:49:47 PM PDT 24
Peak memory 217864 kb
Host smart-0e9248e5-5c89-49e0-a64e-b84b64e79093
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520390201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2520390201
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1604123232
Short name T491
Test name
Test status
Simulation time 6002159615 ps
CPU time 3.6 seconds
Started Jul 26 06:49:28 PM PDT 24
Finished Jul 26 06:49:32 PM PDT 24
Peak memory 201028 kb
Host smart-9b6bbd28-4137-40a6-8553-130ac7ab831e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604123232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1604123232
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1123154944
Short name T657
Test name
Test status
Simulation time 393319047375 ps
CPU time 407.29 seconds
Started Jul 26 06:49:33 PM PDT 24
Finished Jul 26 06:56:21 PM PDT 24
Peak memory 210020 kb
Host smart-20e0066c-f563-493d-be8b-8d6d211d3bef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123154944 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1123154944
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3173433236
Short name T376
Test name
Test status
Simulation time 483909354 ps
CPU time 1.71 seconds
Started Jul 26 06:53:20 PM PDT 24
Finished Jul 26 06:53:22 PM PDT 24
Peak memory 200920 kb
Host smart-418f3475-f3da-46db-945f-98b13e083044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173433236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3173433236
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1005296634
Short name T584
Test name
Test status
Simulation time 158045965253 ps
CPU time 396.98 seconds
Started Jul 26 06:53:17 PM PDT 24
Finished Jul 26 06:59:55 PM PDT 24
Peak memory 201172 kb
Host smart-bb8138d3-ab14-4f20-947a-6ea4a762fe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005296634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1005296634
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2403129077
Short name T592
Test name
Test status
Simulation time 489685841237 ps
CPU time 275.38 seconds
Started Jul 26 06:53:07 PM PDT 24
Finished Jul 26 06:57:42 PM PDT 24
Peak memory 201240 kb
Host smart-ab575861-f537-4d91-8ae8-d6ef12fa1711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403129077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2403129077
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3347999054
Short name T574
Test name
Test status
Simulation time 159772433140 ps
CPU time 372 seconds
Started Jul 26 06:53:06 PM PDT 24
Finished Jul 26 06:59:18 PM PDT 24
Peak memory 201148 kb
Host smart-214a1a95-9c6e-4386-a3f1-534e8721bd78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347999054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3347999054
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1973498043
Short name T277
Test name
Test status
Simulation time 163561557092 ps
CPU time 343.64 seconds
Started Jul 26 06:53:07 PM PDT 24
Finished Jul 26 06:58:50 PM PDT 24
Peak memory 201188 kb
Host smart-701f8fc5-4f51-4680-9d6e-6805ff862be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973498043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1973498043
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1653061413
Short name T691
Test name
Test status
Simulation time 163727041708 ps
CPU time 94.12 seconds
Started Jul 26 06:53:05 PM PDT 24
Finished Jul 26 06:54:39 PM PDT 24
Peak memory 201152 kb
Host smart-27d5d311-1d77-4f29-b9c6-03ddf3c3ca33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653061413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1653061413
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2022127774
Short name T310
Test name
Test status
Simulation time 175553599074 ps
CPU time 403.83 seconds
Started Jul 26 06:53:07 PM PDT 24
Finished Jul 26 06:59:51 PM PDT 24
Peak memory 201132 kb
Host smart-f91bcba2-c9f5-4bff-b458-c9e067024f77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022127774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2022127774
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1142074999
Short name T640
Test name
Test status
Simulation time 204244146941 ps
CPU time 383.37 seconds
Started Jul 26 06:53:18 PM PDT 24
Finished Jul 26 06:59:42 PM PDT 24
Peak memory 201212 kb
Host smart-b855538f-ee59-422c-bd44-176381fb3f53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142074999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1142074999
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2622406738
Short name T802
Test name
Test status
Simulation time 112637694745 ps
CPU time 403.53 seconds
Started Jul 26 06:53:19 PM PDT 24
Finished Jul 26 07:00:02 PM PDT 24
Peak memory 201628 kb
Host smart-39dbc991-b903-48d4-85c6-f2a8cf243990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622406738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2622406738
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3354834058
Short name T8
Test name
Test status
Simulation time 32482203249 ps
CPU time 5.78 seconds
Started Jul 26 06:53:18 PM PDT 24
Finished Jul 26 06:53:24 PM PDT 24
Peak memory 201060 kb
Host smart-9667c8be-ed16-40a0-8527-121c55b4c20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354834058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3354834058
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.567391491
Short name T696
Test name
Test status
Simulation time 3190246453 ps
CPU time 2.07 seconds
Started Jul 26 06:53:17 PM PDT 24
Finished Jul 26 06:53:19 PM PDT 24
Peak memory 200848 kb
Host smart-b0a3adcb-3c0f-4273-b1b6-eb14bdcf14b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567391491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.567391491
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.4093251587
Short name T96
Test name
Test status
Simulation time 5965168522 ps
CPU time 7.05 seconds
Started Jul 26 06:53:07 PM PDT 24
Finished Jul 26 06:53:14 PM PDT 24
Peak memory 201032 kb
Host smart-dbdab83b-5395-481e-989e-3883fe90b425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093251587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.4093251587
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2702395351
Short name T467
Test name
Test status
Simulation time 6109911648 ps
CPU time 3.97 seconds
Started Jul 26 06:53:26 PM PDT 24
Finished Jul 26 06:53:30 PM PDT 24
Peak memory 201000 kb
Host smart-d60a096d-7bfc-44ba-893f-7efc975e2486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702395351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2702395351
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.576075371
Short name T15
Test name
Test status
Simulation time 229415009942 ps
CPU time 182.42 seconds
Started Jul 26 06:53:19 PM PDT 24
Finished Jul 26 06:56:22 PM PDT 24
Peak memory 209940 kb
Host smart-1fe76275-a583-477f-ad63-5a3db510432a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576075371 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.576075371
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1217412374
Short name T477
Test name
Test status
Simulation time 544565442 ps
CPU time 0.94 seconds
Started Jul 26 06:53:17 PM PDT 24
Finished Jul 26 06:53:18 PM PDT 24
Peak memory 200952 kb
Host smart-af5724a0-da51-4bfc-8d09-c80f6509d40a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217412374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1217412374
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3803991092
Short name T613
Test name
Test status
Simulation time 334171473191 ps
CPU time 203.29 seconds
Started Jul 26 06:53:19 PM PDT 24
Finished Jul 26 06:56:42 PM PDT 24
Peak memory 201120 kb
Host smart-1fbc8021-5719-4faf-9b94-f85b73064810
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803991092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3803991092
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.778720830
Short name T265
Test name
Test status
Simulation time 163786484539 ps
CPU time 369.73 seconds
Started Jul 26 06:53:19 PM PDT 24
Finished Jul 26 06:59:29 PM PDT 24
Peak memory 201164 kb
Host smart-7076f26a-5bdf-4165-b6fe-3d3415229b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778720830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.778720830
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.74215548
Short name T182
Test name
Test status
Simulation time 492283120541 ps
CPU time 80.34 seconds
Started Jul 26 06:53:27 PM PDT 24
Finished Jul 26 06:54:47 PM PDT 24
Peak memory 201136 kb
Host smart-78e719ab-6e02-4bae-b073-4830f763de5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74215548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.74215548
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1706735661
Short name T598
Test name
Test status
Simulation time 162009762611 ps
CPU time 180.32 seconds
Started Jul 26 06:53:18 PM PDT 24
Finished Jul 26 06:56:19 PM PDT 24
Peak memory 201148 kb
Host smart-05c49fe2-943f-44b7-93f2-5a9e604cddea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706735661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1706735661
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3378549740
Short name T540
Test name
Test status
Simulation time 162190343457 ps
CPU time 96.88 seconds
Started Jul 26 06:53:25 PM PDT 24
Finished Jul 26 06:55:02 PM PDT 24
Peak memory 201144 kb
Host smart-90871e01-f03d-41a6-a398-8106c538d8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378549740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3378549740
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4261253940
Short name T413
Test name
Test status
Simulation time 161170853946 ps
CPU time 356.78 seconds
Started Jul 26 06:53:18 PM PDT 24
Finished Jul 26 06:59:15 PM PDT 24
Peak memory 201140 kb
Host smart-ad5c87dc-473c-490c-8ff6-076544070136
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261253940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4261253940
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2452093324
Short name T44
Test name
Test status
Simulation time 184815806430 ps
CPU time 395.13 seconds
Started Jul 26 06:53:18 PM PDT 24
Finished Jul 26 06:59:53 PM PDT 24
Peak memory 201180 kb
Host smart-5d0929fa-5fcf-4ddc-abeb-09beba847ba4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452093324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2452093324
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.4194241170
Short name T189
Test name
Test status
Simulation time 398587691910 ps
CPU time 215.16 seconds
Started Jul 26 06:53:18 PM PDT 24
Finished Jul 26 06:56:53 PM PDT 24
Peak memory 201144 kb
Host smart-5158d388-130f-4cee-963c-1dc6e52c802f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194241170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.4194241170
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3224203587
Short name T649
Test name
Test status
Simulation time 121663820784 ps
CPU time 615.4 seconds
Started Jul 26 06:53:26 PM PDT 24
Finished Jul 26 07:03:41 PM PDT 24
Peak memory 201584 kb
Host smart-816dd499-9611-4b43-bc45-0ea929722ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224203587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3224203587
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3275368132
Short name T428
Test name
Test status
Simulation time 30164651482 ps
CPU time 71.74 seconds
Started Jul 26 06:53:21 PM PDT 24
Finished Jul 26 06:54:32 PM PDT 24
Peak memory 200980 kb
Host smart-3cf3c378-de92-411f-b451-f66a2e19da46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275368132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3275368132
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2603842853
Short name T388
Test name
Test status
Simulation time 3520813052 ps
CPU time 8.77 seconds
Started Jul 26 06:53:18 PM PDT 24
Finished Jul 26 06:53:27 PM PDT 24
Peak memory 200980 kb
Host smart-ae0e9838-53d2-404a-ada9-afc2acdf0415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603842853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2603842853
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3059377655
Short name T786
Test name
Test status
Simulation time 5698477125 ps
CPU time 6.94 seconds
Started Jul 26 06:53:18 PM PDT 24
Finished Jul 26 06:53:25 PM PDT 24
Peak memory 201028 kb
Host smart-eccfe321-bb38-41bd-984b-69037090b1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059377655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3059377655
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2446146814
Short name T394
Test name
Test status
Simulation time 275134333187 ps
CPU time 817.41 seconds
Started Jul 26 06:53:16 PM PDT 24
Finished Jul 26 07:06:54 PM PDT 24
Peak memory 209816 kb
Host smart-f449d509-9d4d-4386-8404-779045198f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446146814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2446146814
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3696314290
Short name T304
Test name
Test status
Simulation time 38372442897 ps
CPU time 49.6 seconds
Started Jul 26 06:53:26 PM PDT 24
Finished Jul 26 06:54:16 PM PDT 24
Peak memory 209912 kb
Host smart-07ad7901-23ee-4bc2-9de9-4f34b8f1fea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696314290 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3696314290
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2162168369
Short name T542
Test name
Test status
Simulation time 531837139 ps
CPU time 1.7 seconds
Started Jul 26 06:53:29 PM PDT 24
Finished Jul 26 06:53:31 PM PDT 24
Peak memory 200924 kb
Host smart-6e9aa7f8-a3e3-4278-af12-0e5f36ed0f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162168369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2162168369
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1169238434
Short name T623
Test name
Test status
Simulation time 350815711663 ps
CPU time 358.76 seconds
Started Jul 26 06:53:29 PM PDT 24
Finished Jul 26 06:59:29 PM PDT 24
Peak memory 201108 kb
Host smart-ebe8a652-804a-4a49-b6bd-600b50ca1810
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169238434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1169238434
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2145105442
Short name T718
Test name
Test status
Simulation time 332418988648 ps
CPU time 370.93 seconds
Started Jul 26 06:53:20 PM PDT 24
Finished Jul 26 06:59:31 PM PDT 24
Peak memory 201200 kb
Host smart-cf9c0da0-7c98-4256-b93b-d54c9b73ce87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145105442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2145105442
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1356079509
Short name T607
Test name
Test status
Simulation time 322635110327 ps
CPU time 81 seconds
Started Jul 26 06:53:28 PM PDT 24
Finished Jul 26 06:54:49 PM PDT 24
Peak memory 201156 kb
Host smart-cdb0e17c-0e6a-4f89-bec1-527f8b4c2313
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356079509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1356079509
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2778099087
Short name T253
Test name
Test status
Simulation time 497381738512 ps
CPU time 267.51 seconds
Started Jul 26 06:53:17 PM PDT 24
Finished Jul 26 06:57:45 PM PDT 24
Peak memory 201172 kb
Host smart-a1f4e26d-79bc-4551-a403-32fd678e259d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778099087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2778099087
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3843702665
Short name T89
Test name
Test status
Simulation time 164706929389 ps
CPU time 100.75 seconds
Started Jul 26 06:53:18 PM PDT 24
Finished Jul 26 06:54:59 PM PDT 24
Peak memory 201228 kb
Host smart-6d82c494-0d4b-450c-aab0-2d58efaabf8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843702665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3843702665
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1760153903
Short name T599
Test name
Test status
Simulation time 202217736144 ps
CPU time 472.78 seconds
Started Jul 26 06:53:29 PM PDT 24
Finished Jul 26 07:01:21 PM PDT 24
Peak memory 201100 kb
Host smart-9365bb54-acb8-4fc6-9d82-d765e14cead3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760153903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1760153903
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3162612285
Short name T450
Test name
Test status
Simulation time 415878230718 ps
CPU time 291.14 seconds
Started Jul 26 06:53:31 PM PDT 24
Finished Jul 26 06:58:22 PM PDT 24
Peak memory 201104 kb
Host smart-c04f6f41-d10d-4945-b064-8512fb231eb9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162612285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3162612285
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.12925212
Short name T593
Test name
Test status
Simulation time 84790154599 ps
CPU time 305.07 seconds
Started Jul 26 06:53:28 PM PDT 24
Finished Jul 26 06:58:34 PM PDT 24
Peak memory 201592 kb
Host smart-c00b2ff8-0e18-435d-8d3e-686ab7997550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12925212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.12925212
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.395921430
Short name T661
Test name
Test status
Simulation time 43785908926 ps
CPU time 46.6 seconds
Started Jul 26 06:53:30 PM PDT 24
Finished Jul 26 06:54:16 PM PDT 24
Peak memory 201024 kb
Host smart-e21c57f6-09ae-4bba-b05d-b1b494457e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395921430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.395921430
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4223231318
Short name T354
Test name
Test status
Simulation time 4409644828 ps
CPU time 1.61 seconds
Started Jul 26 06:53:29 PM PDT 24
Finished Jul 26 06:53:31 PM PDT 24
Peak memory 200996 kb
Host smart-b28c3ff2-e6c6-4c93-be66-f23f115ae2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223231318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4223231318
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2753319626
Short name T645
Test name
Test status
Simulation time 6032531141 ps
CPU time 8.02 seconds
Started Jul 26 06:53:26 PM PDT 24
Finished Jul 26 06:53:34 PM PDT 24
Peak memory 201000 kb
Host smart-9b62c593-8c87-4bab-9106-c88cffdcc60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753319626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2753319626
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3046551763
Short name T580
Test name
Test status
Simulation time 495248314990 ps
CPU time 1115.03 seconds
Started Jul 26 06:53:29 PM PDT 24
Finished Jul 26 07:12:05 PM PDT 24
Peak memory 201168 kb
Host smart-f76d1e5d-5c68-4736-99a0-2dfbd22c8bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046551763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3046551763
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1761339866
Short name T294
Test name
Test status
Simulation time 445877622368 ps
CPU time 336.6 seconds
Started Jul 26 06:53:27 PM PDT 24
Finished Jul 26 06:59:04 PM PDT 24
Peak memory 210068 kb
Host smart-b8d61629-6455-46a0-9c52-0496c1223d8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761339866 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1761339866
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3457669375
Short name T745
Test name
Test status
Simulation time 281555805 ps
CPU time 1.24 seconds
Started Jul 26 06:53:38 PM PDT 24
Finished Jul 26 06:53:39 PM PDT 24
Peak memory 200984 kb
Host smart-f49d2118-e28c-4f30-86b6-b7301416e026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457669375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3457669375
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2576491718
Short name T229
Test name
Test status
Simulation time 160888736699 ps
CPU time 177.63 seconds
Started Jul 26 06:53:38 PM PDT 24
Finished Jul 26 06:56:36 PM PDT 24
Peak memory 201200 kb
Host smart-3705b9f4-9a29-4244-ba11-4ec4f8687bf0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576491718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2576491718
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2783552407
Short name T688
Test name
Test status
Simulation time 415103434515 ps
CPU time 524.12 seconds
Started Jul 26 06:53:40 PM PDT 24
Finished Jul 26 07:02:24 PM PDT 24
Peak memory 201108 kb
Host smart-e0497983-80e0-40f6-845b-50511b518686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783552407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2783552407
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3034565753
Short name T749
Test name
Test status
Simulation time 486560434254 ps
CPU time 1057.78 seconds
Started Jul 26 06:53:29 PM PDT 24
Finished Jul 26 07:11:07 PM PDT 24
Peak memory 201132 kb
Host smart-6fd90b86-ad04-4a2c-bd0c-58e34f7bc5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034565753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3034565753
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3724040584
Short name T694
Test name
Test status
Simulation time 167527988744 ps
CPU time 106.65 seconds
Started Jul 26 06:53:28 PM PDT 24
Finished Jul 26 06:55:15 PM PDT 24
Peak memory 201200 kb
Host smart-dfb6a9f1-4ad1-43da-99a5-9efd2064ba99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724040584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3724040584
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2497324696
Short name T595
Test name
Test status
Simulation time 318875221452 ps
CPU time 205.3 seconds
Started Jul 26 06:53:29 PM PDT 24
Finished Jul 26 06:56:55 PM PDT 24
Peak memory 201192 kb
Host smart-f36d278f-fc85-4c72-8c17-f6e04fc65a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497324696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2497324696
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1685231145
Short name T434
Test name
Test status
Simulation time 494675044328 ps
CPU time 307.79 seconds
Started Jul 26 06:53:29 PM PDT 24
Finished Jul 26 06:58:37 PM PDT 24
Peak memory 201184 kb
Host smart-372eb18d-b39c-47d4-b183-6901a8a2cd8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685231145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1685231145
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.948109652
Short name T139
Test name
Test status
Simulation time 172669049626 ps
CPU time 368.58 seconds
Started Jul 26 06:53:38 PM PDT 24
Finished Jul 26 06:59:47 PM PDT 24
Peak memory 201156 kb
Host smart-4b304e67-67e3-47b4-af48-6abe8429bb8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948109652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.948109652
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1554887037
Short name T358
Test name
Test status
Simulation time 577627974434 ps
CPU time 596.52 seconds
Started Jul 26 06:53:40 PM PDT 24
Finished Jul 26 07:03:36 PM PDT 24
Peak memory 201168 kb
Host smart-8b8047fe-eea9-4ac2-918c-8c13a581e37d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554887037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1554887037
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3416564551
Short name T199
Test name
Test status
Simulation time 76854455745 ps
CPU time 315.2 seconds
Started Jul 26 06:53:38 PM PDT 24
Finished Jul 26 06:58:53 PM PDT 24
Peak memory 201720 kb
Host smart-668d8183-54c8-4a88-a32e-c6641f116b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416564551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3416564551
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1673825779
Short name T355
Test name
Test status
Simulation time 31160113232 ps
CPU time 74.54 seconds
Started Jul 26 06:53:40 PM PDT 24
Finished Jul 26 06:54:54 PM PDT 24
Peak memory 200964 kb
Host smart-16f2873d-ade1-46bc-9a6b-1b470742f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673825779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1673825779
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1948176155
Short name T606
Test name
Test status
Simulation time 3010083494 ps
CPU time 4.4 seconds
Started Jul 26 06:53:39 PM PDT 24
Finished Jul 26 06:53:44 PM PDT 24
Peak memory 200984 kb
Host smart-26fd2aae-1740-4038-99e2-97917d91a86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948176155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1948176155
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1488999450
Short name T429
Test name
Test status
Simulation time 5964183165 ps
CPU time 7.48 seconds
Started Jul 26 06:53:30 PM PDT 24
Finished Jul 26 06:53:37 PM PDT 24
Peak memory 201044 kb
Host smart-ab463675-6709-4f4e-9976-3a6bc847f049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488999450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1488999450
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3545137212
Short name T106
Test name
Test status
Simulation time 574663140995 ps
CPU time 332.6 seconds
Started Jul 26 06:53:39 PM PDT 24
Finished Jul 26 06:59:11 PM PDT 24
Peak memory 218000 kb
Host smart-ba294912-d38e-4a1c-a15d-447a2dc1c0fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545137212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3545137212
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1328132641
Short name T98
Test name
Test status
Simulation time 104747422672 ps
CPU time 121.34 seconds
Started Jul 26 06:53:38 PM PDT 24
Finished Jul 26 06:55:40 PM PDT 24
Peak memory 217640 kb
Host smart-7a359925-49ea-44e0-a8d6-5dc35fee8e4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328132641 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1328132641
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2067949871
Short name T508
Test name
Test status
Simulation time 318155099 ps
CPU time 1.23 seconds
Started Jul 26 06:53:47 PM PDT 24
Finished Jul 26 06:53:49 PM PDT 24
Peak memory 200856 kb
Host smart-c7c90429-2377-40aa-b63a-31fe37b7fb9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067949871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2067949871
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3210038503
Short name T150
Test name
Test status
Simulation time 431066829424 ps
CPU time 262.84 seconds
Started Jul 26 06:53:48 PM PDT 24
Finished Jul 26 06:58:11 PM PDT 24
Peak memory 201160 kb
Host smart-89f9c974-1b15-49eb-8138-646d751793b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210038503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3210038503
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3158187314
Short name T285
Test name
Test status
Simulation time 326771550039 ps
CPU time 743.18 seconds
Started Jul 26 06:53:44 PM PDT 24
Finished Jul 26 07:06:07 PM PDT 24
Peak memory 201156 kb
Host smart-8cfd7848-2338-457f-b176-60bca34c7dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158187314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3158187314
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2852194750
Short name T195
Test name
Test status
Simulation time 328377164140 ps
CPU time 193.88 seconds
Started Jul 26 06:53:39 PM PDT 24
Finished Jul 26 06:56:53 PM PDT 24
Peak memory 201180 kb
Host smart-280efc16-31fa-483b-8ca9-0b4207505e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852194750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2852194750
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.659224790
Short name T730
Test name
Test status
Simulation time 327303003936 ps
CPU time 401.41 seconds
Started Jul 26 06:53:39 PM PDT 24
Finished Jul 26 07:00:20 PM PDT 24
Peak memory 201176 kb
Host smart-89d66b5f-025b-493f-b9a9-628f0d864002
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=659224790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.659224790
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3854131885
Short name T539
Test name
Test status
Simulation time 174878706638 ps
CPU time 351.12 seconds
Started Jul 26 06:53:42 PM PDT 24
Finished Jul 26 06:59:33 PM PDT 24
Peak memory 201164 kb
Host smart-ec95369f-7e6b-49f5-ab00-c096237039d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854131885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3854131885
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1510170916
Short name T577
Test name
Test status
Simulation time 495073053320 ps
CPU time 259.42 seconds
Started Jul 26 06:53:38 PM PDT 24
Finished Jul 26 06:57:57 PM PDT 24
Peak memory 201164 kb
Host smart-164dabbd-525c-432d-bd8f-b858f7b39e8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510170916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1510170916
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2279303899
Short name T658
Test name
Test status
Simulation time 194001007036 ps
CPU time 474.31 seconds
Started Jul 26 06:53:40 PM PDT 24
Finished Jul 26 07:01:34 PM PDT 24
Peak memory 201124 kb
Host smart-4c06d700-2684-42da-a40b-00ca8b02c222
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279303899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2279303899
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3376939850
Short name T515
Test name
Test status
Simulation time 396325454959 ps
CPU time 246.18 seconds
Started Jul 26 06:53:40 PM PDT 24
Finished Jul 26 06:57:46 PM PDT 24
Peak memory 201148 kb
Host smart-44740437-815f-43ae-9e71-8b4f671ec631
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376939850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3376939850
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3162607544
Short name T560
Test name
Test status
Simulation time 80055931031 ps
CPU time 396.73 seconds
Started Jul 26 06:53:47 PM PDT 24
Finished Jul 26 07:00:24 PM PDT 24
Peak memory 201676 kb
Host smart-14ec70fd-c83b-4b57-9999-02f7d9c60fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162607544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3162607544
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1364917768
Short name T723
Test name
Test status
Simulation time 33745815730 ps
CPU time 58.09 seconds
Started Jul 26 06:53:50 PM PDT 24
Finished Jul 26 06:54:48 PM PDT 24
Peak memory 201004 kb
Host smart-630325e4-701c-4953-8967-c43093a99358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364917768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1364917768
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.260842600
Short name T391
Test name
Test status
Simulation time 3902780684 ps
CPU time 9.63 seconds
Started Jul 26 06:53:47 PM PDT 24
Finished Jul 26 06:53:56 PM PDT 24
Peak memory 200996 kb
Host smart-f5137557-f8e6-445c-aed2-3131d2c5cabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260842600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.260842600
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2672465011
Short name T722
Test name
Test status
Simulation time 5829762263 ps
CPU time 15.18 seconds
Started Jul 26 06:53:39 PM PDT 24
Finished Jul 26 06:53:54 PM PDT 24
Peak memory 201048 kb
Host smart-6f42d3b3-ca5a-4823-8608-b9279590f7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672465011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2672465011
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2617316613
Short name T39
Test name
Test status
Simulation time 76041413490 ps
CPU time 76.36 seconds
Started Jul 26 06:53:46 PM PDT 24
Finished Jul 26 06:55:03 PM PDT 24
Peak memory 209516 kb
Host smart-926e9a0a-139e-4802-9434-c6526c130018
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617316613 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2617316613
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.605645097
Short name T562
Test name
Test status
Simulation time 310925298 ps
CPU time 1.3 seconds
Started Jul 26 06:53:56 PM PDT 24
Finished Jul 26 06:53:57 PM PDT 24
Peak memory 200920 kb
Host smart-abd51bf9-c34e-4c16-805c-21d533c56aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605645097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.605645097
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1475656388
Short name T272
Test name
Test status
Simulation time 334718173170 ps
CPU time 381.04 seconds
Started Jul 26 06:53:55 PM PDT 24
Finished Jul 26 07:00:16 PM PDT 24
Peak memory 201216 kb
Host smart-e4897737-cf4c-4c6e-a4cd-c4d604f3a728
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475656388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1475656388
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2132042021
Short name T761
Test name
Test status
Simulation time 350255846410 ps
CPU time 427.86 seconds
Started Jul 26 06:53:55 PM PDT 24
Finished Jul 26 07:01:03 PM PDT 24
Peak memory 201432 kb
Host smart-381c427c-33eb-4ed7-a926-75a8fb5003bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132042021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2132042021
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3230802358
Short name T144
Test name
Test status
Simulation time 162918426181 ps
CPU time 103.23 seconds
Started Jul 26 06:53:47 PM PDT 24
Finished Jul 26 06:55:30 PM PDT 24
Peak memory 201200 kb
Host smart-5df82c75-fb06-4959-927b-0be5417ad294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230802358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3230802358
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.4129056476
Short name T650
Test name
Test status
Simulation time 161616926395 ps
CPU time 37.7 seconds
Started Jul 26 06:53:55 PM PDT 24
Finished Jul 26 06:54:33 PM PDT 24
Peak memory 201232 kb
Host smart-3e1bced1-0d74-43f8-b370-8cec02752f69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129056476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.4129056476
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.4203357098
Short name T668
Test name
Test status
Simulation time 497374472518 ps
CPU time 1095.94 seconds
Started Jul 26 06:53:46 PM PDT 24
Finished Jul 26 07:12:02 PM PDT 24
Peak memory 201192 kb
Host smart-5523bac0-c90f-4b44-9bb8-21fca9ffef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203357098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.4203357098
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2767869929
Short name T24
Test name
Test status
Simulation time 502318448095 ps
CPU time 300.6 seconds
Started Jul 26 06:53:47 PM PDT 24
Finished Jul 26 06:58:47 PM PDT 24
Peak memory 201200 kb
Host smart-682e12a0-5d68-44b4-9b43-d4a3862da3d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767869929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2767869929
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2828302342
Short name T514
Test name
Test status
Simulation time 561369944196 ps
CPU time 607.2 seconds
Started Jul 26 06:53:56 PM PDT 24
Finished Jul 26 07:04:04 PM PDT 24
Peak memory 201252 kb
Host smart-839702e7-6697-4509-a049-64773e2fa082
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828302342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2828302342
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4013343949
Short name T782
Test name
Test status
Simulation time 407529415755 ps
CPU time 906.9 seconds
Started Jul 26 06:53:57 PM PDT 24
Finished Jul 26 07:09:04 PM PDT 24
Peak memory 201248 kb
Host smart-4281c586-a06e-4d9b-8770-522e6b28cc6d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013343949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.4013343949
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1627006484
Short name T605
Test name
Test status
Simulation time 89873644789 ps
CPU time 327.63 seconds
Started Jul 26 06:53:57 PM PDT 24
Finished Jul 26 06:59:25 PM PDT 24
Peak memory 201612 kb
Host smart-edc2c120-a594-4ae7-b3f1-923fcde32842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627006484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1627006484
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3245371432
Short name T796
Test name
Test status
Simulation time 38609590737 ps
CPU time 43.8 seconds
Started Jul 26 06:53:55 PM PDT 24
Finished Jul 26 06:54:39 PM PDT 24
Peak memory 200988 kb
Host smart-bd002c43-8358-475c-bfb9-07b0f2c59d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245371432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3245371432
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3416024029
Short name T453
Test name
Test status
Simulation time 4913069124 ps
CPU time 3.73 seconds
Started Jul 26 06:53:56 PM PDT 24
Finished Jul 26 06:53:59 PM PDT 24
Peak memory 200848 kb
Host smart-cf86f06b-b7db-4f03-b108-9c4ff997d7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416024029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3416024029
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2716304914
Short name T437
Test name
Test status
Simulation time 6006804496 ps
CPU time 4 seconds
Started Jul 26 06:53:46 PM PDT 24
Finished Jul 26 06:53:50 PM PDT 24
Peak memory 201036 kb
Host smart-5ec4ebd8-2797-4424-b956-354af75a4444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716304914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2716304914
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1525697427
Short name T288
Test name
Test status
Simulation time 329653941968 ps
CPU time 202.66 seconds
Started Jul 26 06:53:55 PM PDT 24
Finished Jul 26 06:57:18 PM PDT 24
Peak memory 201136 kb
Host smart-42120772-d1fc-4640-9292-d49562417bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525697427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1525697427
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.716639417
Short name T240
Test name
Test status
Simulation time 142119378348 ps
CPU time 68.32 seconds
Started Jul 26 06:53:57 PM PDT 24
Finished Jul 26 06:55:05 PM PDT 24
Peak memory 209448 kb
Host smart-46891fa5-f032-4a3b-b6ea-ab7dbb04a137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716639417 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.716639417
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1115918863
Short name T530
Test name
Test status
Simulation time 361123598 ps
CPU time 0.81 seconds
Started Jul 26 06:54:12 PM PDT 24
Finished Jul 26 06:54:13 PM PDT 24
Peak memory 200948 kb
Host smart-ab73427d-253b-4af1-ad99-f7b2d5d4633b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115918863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1115918863
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.738827285
Short name T456
Test name
Test status
Simulation time 489416516150 ps
CPU time 202.2 seconds
Started Jul 26 06:54:05 PM PDT 24
Finished Jul 26 06:57:28 PM PDT 24
Peak memory 201196 kb
Host smart-db38c3cf-519a-44f4-995b-767ce6f1f754
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=738827285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.738827285
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1297061857
Short name T463
Test name
Test status
Simulation time 165157780505 ps
CPU time 329.79 seconds
Started Jul 26 06:54:04 PM PDT 24
Finished Jul 26 06:59:34 PM PDT 24
Peak memory 201176 kb
Host smart-27eca7b5-ab4f-4b40-8f4b-809f09b0563a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297061857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1297061857
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1345325211
Short name T152
Test name
Test status
Simulation time 357777450126 ps
CPU time 425.16 seconds
Started Jul 26 06:54:04 PM PDT 24
Finished Jul 26 07:01:09 PM PDT 24
Peak memory 201176 kb
Host smart-6fdddc17-30d1-4754-a5f7-9920363c84a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345325211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1345325211
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2711374134
Short name T797
Test name
Test status
Simulation time 187578315356 ps
CPU time 434.85 seconds
Started Jul 26 06:54:04 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 201120 kb
Host smart-b4a22bcb-8be9-49ed-8d93-30c30f80e75b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711374134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2711374134
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1922791243
Short name T589
Test name
Test status
Simulation time 31630189987 ps
CPU time 37.62 seconds
Started Jul 26 06:54:10 PM PDT 24
Finished Jul 26 06:54:48 PM PDT 24
Peak memory 201036 kb
Host smart-3e7711f8-ac36-4be1-93e7-8aa8df8b37c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922791243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1922791243
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2157883320
Short name T619
Test name
Test status
Simulation time 3206329550 ps
CPU time 3.97 seconds
Started Jul 26 06:54:03 PM PDT 24
Finished Jul 26 06:54:07 PM PDT 24
Peak memory 200988 kb
Host smart-d72e9382-e6af-4d9f-b71a-56590a96634c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157883320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2157883320
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3773043471
Short name T360
Test name
Test status
Simulation time 5775195055 ps
CPU time 13.99 seconds
Started Jul 26 06:54:04 PM PDT 24
Finished Jul 26 06:54:18 PM PDT 24
Peak memory 201104 kb
Host smart-e4941eac-703e-47d5-8cf9-2fabb948eec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773043471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3773043471
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.554303293
Short name T329
Test name
Test status
Simulation time 257021237347 ps
CPU time 559.92 seconds
Started Jul 26 06:54:11 PM PDT 24
Finished Jul 26 07:03:31 PM PDT 24
Peak memory 201128 kb
Host smart-5bc2279b-54ee-41b4-b587-07ef5e48080e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554303293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
554303293
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.589102241
Short name T31
Test name
Test status
Simulation time 103006724927 ps
CPU time 237.32 seconds
Started Jul 26 06:54:12 PM PDT 24
Finished Jul 26 06:58:09 PM PDT 24
Peak memory 209944 kb
Host smart-55ee9d57-1834-408c-b326-fd8a40219277
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589102241 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.589102241
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2251176509
Short name T741
Test name
Test status
Simulation time 421301548 ps
CPU time 0.97 seconds
Started Jul 26 06:54:18 PM PDT 24
Finished Jul 26 06:54:20 PM PDT 24
Peak memory 201200 kb
Host smart-b44a9e85-adbb-402d-b19d-7ae196a533d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251176509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2251176509
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1870812452
Short name T293
Test name
Test status
Simulation time 490781890599 ps
CPU time 411.43 seconds
Started Jul 26 06:54:20 PM PDT 24
Finished Jul 26 07:01:12 PM PDT 24
Peak memory 201196 kb
Host smart-7443fd21-001c-4552-bdf7-15d0b2fbc1d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870812452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1870812452
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2406926980
Short name T331
Test name
Test status
Simulation time 158413432838 ps
CPU time 349.56 seconds
Started Jul 26 06:54:12 PM PDT 24
Finished Jul 26 07:00:01 PM PDT 24
Peak memory 201164 kb
Host smart-7f263ea4-55f9-4031-85d5-fb94842fd54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406926980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2406926980
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2409796074
Short name T682
Test name
Test status
Simulation time 488832997488 ps
CPU time 1210.07 seconds
Started Jul 26 06:54:12 PM PDT 24
Finished Jul 26 07:14:22 PM PDT 24
Peak memory 201208 kb
Host smart-bd1d1e03-fc07-412a-859c-89f9e55f6d46
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409796074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2409796074
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3560952734
Short name T750
Test name
Test status
Simulation time 334593079092 ps
CPU time 478.02 seconds
Started Jul 26 06:54:11 PM PDT 24
Finished Jul 26 07:02:09 PM PDT 24
Peak memory 201236 kb
Host smart-0232cebd-2e12-48c0-a27d-0dde48507720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560952734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3560952734
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.725598378
Short name T532
Test name
Test status
Simulation time 164759203498 ps
CPU time 392.71 seconds
Started Jul 26 06:54:12 PM PDT 24
Finished Jul 26 07:00:44 PM PDT 24
Peak memory 201140 kb
Host smart-c548b2f4-36c3-4163-b767-19def445c25c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=725598378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.725598378
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2286070642
Short name T75
Test name
Test status
Simulation time 357590037499 ps
CPU time 781.83 seconds
Started Jul 26 06:54:11 PM PDT 24
Finished Jul 26 07:07:13 PM PDT 24
Peak memory 201128 kb
Host smart-71de4ded-1936-4f4a-b6c7-360b303b9368
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286070642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2286070642
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2071602670
Short name T464
Test name
Test status
Simulation time 195454686564 ps
CPU time 439.72 seconds
Started Jul 26 06:54:11 PM PDT 24
Finished Jul 26 07:01:31 PM PDT 24
Peak memory 201168 kb
Host smart-d3155c15-3338-46ac-bfe0-636bbaf56d9d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071602670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2071602670
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1213748338
Short name T502
Test name
Test status
Simulation time 110570017955 ps
CPU time 547.13 seconds
Started Jul 26 06:54:20 PM PDT 24
Finished Jul 26 07:03:27 PM PDT 24
Peak memory 201676 kb
Host smart-b5bf8d36-c12a-4c33-94bb-19370a291390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213748338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1213748338
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1253630827
Short name T384
Test name
Test status
Simulation time 24432272333 ps
CPU time 10.08 seconds
Started Jul 26 06:54:20 PM PDT 24
Finished Jul 26 06:54:30 PM PDT 24
Peak memory 201000 kb
Host smart-e0f41687-5788-4e94-b003-11b566e5f8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253630827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1253630827
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1829936399
Short name T424
Test name
Test status
Simulation time 3262731738 ps
CPU time 1.48 seconds
Started Jul 26 06:54:22 PM PDT 24
Finished Jul 26 06:54:24 PM PDT 24
Peak memory 201016 kb
Host smart-4342223e-fb0d-476f-9bad-49e8852abca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829936399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1829936399
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.580780001
Short name T667
Test name
Test status
Simulation time 5782183737 ps
CPU time 9.63 seconds
Started Jul 26 06:54:12 PM PDT 24
Finished Jul 26 06:54:22 PM PDT 24
Peak memory 201108 kb
Host smart-a8679675-421f-4f44-b28d-63dd3f3e4b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580780001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.580780001
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2922481564
Short name T447
Test name
Test status
Simulation time 1095146591 ps
CPU time 2.89 seconds
Started Jul 26 06:54:22 PM PDT 24
Finished Jul 26 06:54:25 PM PDT 24
Peak memory 200976 kb
Host smart-43428f5a-730f-4721-801d-fa9815924cb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922481564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2922481564
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2986915013
Short name T731
Test name
Test status
Simulation time 30108842488 ps
CPU time 65.96 seconds
Started Jul 26 06:54:22 PM PDT 24
Finished Jul 26 06:55:28 PM PDT 24
Peak memory 209540 kb
Host smart-bfa6b0a1-b70c-4fdf-85b6-d3560e7fb472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986915013 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2986915013
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1095797332
Short name T399
Test name
Test status
Simulation time 398852186 ps
CPU time 0.82 seconds
Started Jul 26 06:54:32 PM PDT 24
Finished Jul 26 06:54:33 PM PDT 24
Peak memory 200952 kb
Host smart-d10252ca-5da6-4d76-9bca-aca607669d1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095797332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1095797332
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.4002498557
Short name T190
Test name
Test status
Simulation time 168730886828 ps
CPU time 91.04 seconds
Started Jul 26 06:54:29 PM PDT 24
Finished Jul 26 06:56:00 PM PDT 24
Peak memory 201236 kb
Host smart-5f5f34a4-5dfa-4bc3-945b-693dcdf210dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002498557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.4002498557
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.961480706
Short name T43
Test name
Test status
Simulation time 437497745346 ps
CPU time 206.81 seconds
Started Jul 26 06:54:30 PM PDT 24
Finished Jul 26 06:57:57 PM PDT 24
Peak memory 201224 kb
Host smart-6a37e71c-3162-4483-8cb8-a5dfb66b2183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961480706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.961480706
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1397210761
Short name T465
Test name
Test status
Simulation time 322267814203 ps
CPU time 50.66 seconds
Started Jul 26 06:54:22 PM PDT 24
Finished Jul 26 06:55:13 PM PDT 24
Peak memory 201184 kb
Host smart-fe1bafb5-aec6-438b-9b0c-e57a79db1533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397210761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1397210761
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1812994165
Short name T516
Test name
Test status
Simulation time 329931187527 ps
CPU time 384.89 seconds
Started Jul 26 06:54:20 PM PDT 24
Finished Jul 26 07:00:45 PM PDT 24
Peak memory 201176 kb
Host smart-a98c7ea2-884f-4008-96fc-4c0d4db7e58b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812994165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1812994165
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.490712709
Short name T736
Test name
Test status
Simulation time 323085478510 ps
CPU time 194.52 seconds
Started Jul 26 06:54:19 PM PDT 24
Finished Jul 26 06:57:34 PM PDT 24
Peak memory 201180 kb
Host smart-82d45a52-9235-4b79-9107-f9d6af7a74fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490712709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.490712709
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2850179185
Short name T798
Test name
Test status
Simulation time 332097891369 ps
CPU time 129.29 seconds
Started Jul 26 06:54:19 PM PDT 24
Finished Jul 26 06:56:29 PM PDT 24
Peak memory 201144 kb
Host smart-0a650c9f-5766-4a53-b7e4-817e11a83fb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850179185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2850179185
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2795785899
Short name T666
Test name
Test status
Simulation time 546892003394 ps
CPU time 1197.49 seconds
Started Jul 26 06:54:20 PM PDT 24
Finished Jul 26 07:14:18 PM PDT 24
Peak memory 201308 kb
Host smart-0439568b-7dde-4c98-aa1a-c9b46b238d0e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795785899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2795785899
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2558626153
Short name T706
Test name
Test status
Simulation time 604909342348 ps
CPU time 344.58 seconds
Started Jul 26 06:54:20 PM PDT 24
Finished Jul 26 07:00:05 PM PDT 24
Peak memory 201112 kb
Host smart-78a91789-fd2b-4a03-913b-c3811f6acd4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558626153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2558626153
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2751496304
Short name T201
Test name
Test status
Simulation time 106738153220 ps
CPU time 435.64 seconds
Started Jul 26 06:54:32 PM PDT 24
Finished Jul 26 07:01:48 PM PDT 24
Peak memory 201600 kb
Host smart-02ddd713-f399-4efc-aa15-0b56d31f221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751496304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2751496304
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.4057500414
Short name T353
Test name
Test status
Simulation time 43161052852 ps
CPU time 23.92 seconds
Started Jul 26 06:54:30 PM PDT 24
Finished Jul 26 06:54:54 PM PDT 24
Peak memory 201024 kb
Host smart-3c09acab-4aca-4851-8577-c7811f921c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057500414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.4057500414
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2756752511
Short name T352
Test name
Test status
Simulation time 3292135446 ps
CPU time 2.23 seconds
Started Jul 26 06:54:31 PM PDT 24
Finished Jul 26 06:54:33 PM PDT 24
Peak memory 200980 kb
Host smart-425c5739-db3f-4ea8-b675-80cb7646be54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756752511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2756752511
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.738688942
Short name T597
Test name
Test status
Simulation time 5682763103 ps
CPU time 14.84 seconds
Started Jul 26 06:54:21 PM PDT 24
Finished Jul 26 06:54:36 PM PDT 24
Peak memory 201044 kb
Host smart-4c3019e8-0270-4625-b65a-9a0eba92786b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738688942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.738688942
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1587134548
Short name T55
Test name
Test status
Simulation time 264662406598 ps
CPU time 168.45 seconds
Started Jul 26 06:54:32 PM PDT 24
Finished Jul 26 06:57:21 PM PDT 24
Peak memory 218096 kb
Host smart-d372c831-09e6-4557-830f-8597a022dc90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587134548 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1587134548
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3990526641
Short name T105
Test name
Test status
Simulation time 514092103 ps
CPU time 0.9 seconds
Started Jul 26 06:54:37 PM PDT 24
Finished Jul 26 06:54:38 PM PDT 24
Peak memory 200824 kb
Host smart-fcd3cbd0-369a-4db8-aee8-0378e7ca275c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990526641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3990526641
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2940930171
Short name T298
Test name
Test status
Simulation time 554439300064 ps
CPU time 270.96 seconds
Started Jul 26 06:54:30 PM PDT 24
Finished Jul 26 06:59:01 PM PDT 24
Peak memory 201044 kb
Host smart-73c1b1c0-ec47-4d1e-bcc1-ee91674fd595
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940930171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2940930171
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1616107415
Short name T505
Test name
Test status
Simulation time 496816930572 ps
CPU time 178.03 seconds
Started Jul 26 06:54:28 PM PDT 24
Finished Jul 26 06:57:26 PM PDT 24
Peak memory 201172 kb
Host smart-e9ea7cd7-9ee7-42ee-9210-a0907b0ead40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616107415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1616107415
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1502409304
Short name T393
Test name
Test status
Simulation time 323742523681 ps
CPU time 701.59 seconds
Started Jul 26 06:54:30 PM PDT 24
Finished Jul 26 07:06:12 PM PDT 24
Peak memory 201108 kb
Host smart-2c32cc40-b5cf-441c-988b-4ae6bb05f3ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502409304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1502409304
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1151549108
Short name T396
Test name
Test status
Simulation time 165740115725 ps
CPU time 202.41 seconds
Started Jul 26 06:54:29 PM PDT 24
Finished Jul 26 06:57:52 PM PDT 24
Peak memory 201172 kb
Host smart-3173f320-daf3-4ef1-8335-459ba0b20589
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151549108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1151549108
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.27709600
Short name T287
Test name
Test status
Simulation time 551556368828 ps
CPU time 662.07 seconds
Started Jul 26 06:54:31 PM PDT 24
Finished Jul 26 07:05:33 PM PDT 24
Peak memory 201156 kb
Host smart-ff398e37-b201-4b93-9ad3-07f427fa8298
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27709600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_w
akeup.27709600
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.4216368915
Short name T440
Test name
Test status
Simulation time 199963165758 ps
CPU time 116.64 seconds
Started Jul 26 06:54:28 PM PDT 24
Finished Jul 26 06:56:25 PM PDT 24
Peak memory 201148 kb
Host smart-8a8bfe13-ddec-4182-ae92-359e9014846c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216368915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.4216368915
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2899773563
Short name T208
Test name
Test status
Simulation time 107334281456 ps
CPU time 376.1 seconds
Started Jul 26 06:54:37 PM PDT 24
Finished Jul 26 07:00:53 PM PDT 24
Peak memory 201612 kb
Host smart-761d43d4-d3f2-47f0-9154-7d4138891e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899773563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2899773563
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1087524088
Short name T567
Test name
Test status
Simulation time 22969671230 ps
CPU time 57.1 seconds
Started Jul 26 06:54:38 PM PDT 24
Finished Jul 26 06:55:35 PM PDT 24
Peak memory 200988 kb
Host smart-0d102e57-f5d0-4c4f-afd8-3758b782f476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087524088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1087524088
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1925335189
Short name T490
Test name
Test status
Simulation time 3987951605 ps
CPU time 3.1 seconds
Started Jul 26 06:54:37 PM PDT 24
Finished Jul 26 06:54:40 PM PDT 24
Peak memory 201028 kb
Host smart-c4c53c26-aa4d-45bc-8ca8-2313f5a0d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925335189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1925335189
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2728035685
Short name T472
Test name
Test status
Simulation time 6061133723 ps
CPU time 10.76 seconds
Started Jul 26 06:54:30 PM PDT 24
Finished Jul 26 06:54:41 PM PDT 24
Peak memory 201052 kb
Host smart-f7582403-d39e-4fa2-989e-9b14ba6d5239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728035685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2728035685
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3994281092
Short name T211
Test name
Test status
Simulation time 486087416967 ps
CPU time 585.29 seconds
Started Jul 26 06:54:38 PM PDT 24
Finished Jul 26 07:04:23 PM PDT 24
Peak memory 209816 kb
Host smart-b6dcddf6-58c3-4977-9ed3-6d38aeea64dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994281092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3994281092
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1515240868
Short name T487
Test name
Test status
Simulation time 65052362697 ps
CPU time 69.17 seconds
Started Jul 26 06:54:38 PM PDT 24
Finished Jul 26 06:55:47 PM PDT 24
Peak memory 209508 kb
Host smart-95da5158-5f4d-4ac9-ba42-54a60b4c8939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515240868 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1515240868
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1649341599
Short name T509
Test name
Test status
Simulation time 511758254 ps
CPU time 1.26 seconds
Started Jul 26 06:49:48 PM PDT 24
Finished Jul 26 06:49:49 PM PDT 24
Peak memory 201044 kb
Host smart-fb5faf1c-0b76-4cff-aa82-1432d40e7fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649341599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1649341599
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1975967553
Short name T707
Test name
Test status
Simulation time 524239363334 ps
CPU time 1031.14 seconds
Started Jul 26 06:49:46 PM PDT 24
Finished Jul 26 07:06:57 PM PDT 24
Peak memory 201152 kb
Host smart-d5c3fa16-5f97-425d-9c2b-73e8c2ba7ba6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975967553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1975967553
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1119302509
Short name T301
Test name
Test status
Simulation time 504003581815 ps
CPU time 1246.63 seconds
Started Jul 26 06:49:47 PM PDT 24
Finished Jul 26 07:10:33 PM PDT 24
Peak memory 201224 kb
Host smart-c20340fc-ecbd-4f2b-9d3a-eef137d12358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119302509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1119302509
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2716426687
Short name T653
Test name
Test status
Simulation time 505068460576 ps
CPU time 660.96 seconds
Started Jul 26 06:49:35 PM PDT 24
Finished Jul 26 07:00:36 PM PDT 24
Peak memory 201220 kb
Host smart-9cb95cbd-c423-4da7-beab-a928165a79c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716426687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2716426687
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.16327273
Short name T403
Test name
Test status
Simulation time 165397193128 ps
CPU time 85.2 seconds
Started Jul 26 06:49:37 PM PDT 24
Finished Jul 26 06:51:02 PM PDT 24
Peak memory 201200 kb
Host smart-1150c814-f4bc-429f-afc2-c818df104919
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=16327273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_
fixed.16327273
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.4181045134
Short name T708
Test name
Test status
Simulation time 487836362616 ps
CPU time 162.87 seconds
Started Jul 26 06:49:35 PM PDT 24
Finished Jul 26 06:52:18 PM PDT 24
Peak memory 201120 kb
Host smart-3ce1616a-f5c5-402a-85b6-ff7661789919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181045134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.4181045134
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1047749942
Short name T441
Test name
Test status
Simulation time 156333807614 ps
CPU time 381.12 seconds
Started Jul 26 06:49:35 PM PDT 24
Finished Jul 26 06:55:56 PM PDT 24
Peak memory 201152 kb
Host smart-206bc3e8-5f01-4a7a-b01e-966a033a6594
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047749942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1047749942
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2455924508
Short name T166
Test name
Test status
Simulation time 650533860689 ps
CPU time 392.81 seconds
Started Jul 26 06:49:36 PM PDT 24
Finished Jul 26 06:56:09 PM PDT 24
Peak memory 201168 kb
Host smart-3d067c74-b95c-4d39-bd41-8266aa2d931b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455924508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2455924508
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3577264621
Short name T83
Test name
Test status
Simulation time 394459050603 ps
CPU time 163.45 seconds
Started Jul 26 06:49:37 PM PDT 24
Finished Jul 26 06:52:20 PM PDT 24
Peak memory 201160 kb
Host smart-481b23f2-1ebd-4448-a911-c2a51bc74268
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577264621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3577264621
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.281769308
Short name T546
Test name
Test status
Simulation time 77044087129 ps
CPU time 295.56 seconds
Started Jul 26 06:49:44 PM PDT 24
Finished Jul 26 06:54:40 PM PDT 24
Peak memory 201624 kb
Host smart-013c4a6b-6652-4f16-b66b-ce690619295a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281769308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.281769308
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3034932091
Short name T445
Test name
Test status
Simulation time 24910638745 ps
CPU time 13.06 seconds
Started Jul 26 06:49:47 PM PDT 24
Finished Jul 26 06:50:00 PM PDT 24
Peak memory 201000 kb
Host smart-24245c1f-ef1e-4fd9-beb8-8345d5594539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034932091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3034932091
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1020785714
Short name T420
Test name
Test status
Simulation time 4965722180 ps
CPU time 12.83 seconds
Started Jul 26 06:49:45 PM PDT 24
Finished Jul 26 06:49:58 PM PDT 24
Peak memory 201020 kb
Host smart-0eed16a8-b43f-4a5a-9581-e0d771c17995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020785714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1020785714
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3735716374
Short name T620
Test name
Test status
Simulation time 6156233014 ps
CPU time 4.14 seconds
Started Jul 26 06:49:35 PM PDT 24
Finished Jul 26 06:49:40 PM PDT 24
Peak memory 200992 kb
Host smart-9cbcf176-eb0d-4c13-9da7-107797cf7fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735716374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3735716374
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1198101137
Short name T781
Test name
Test status
Simulation time 123837465402 ps
CPU time 150.54 seconds
Started Jul 26 06:49:45 PM PDT 24
Finished Jul 26 06:52:15 PM PDT 24
Peak memory 218128 kb
Host smart-80173d4b-2e24-4df5-b8b6-e6f02b98b0c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198101137 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1198101137
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1937377152
Short name T414
Test name
Test status
Simulation time 343778997 ps
CPU time 1.35 seconds
Started Jul 26 06:54:52 PM PDT 24
Finished Jul 26 06:54:54 PM PDT 24
Peak memory 200964 kb
Host smart-4b2b59ab-d4a0-4f2f-a483-7cd8fe76ba34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937377152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1937377152
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.199265142
Short name T332
Test name
Test status
Simulation time 542495956504 ps
CPU time 490.68 seconds
Started Jul 26 06:54:51 PM PDT 24
Finished Jul 26 07:03:02 PM PDT 24
Peak memory 201172 kb
Host smart-54bf4383-02a4-484f-a9ce-4d8e10cd70eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199265142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.199265142
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1346760966
Short name T774
Test name
Test status
Simulation time 366973385346 ps
CPU time 438.25 seconds
Started Jul 26 06:54:51 PM PDT 24
Finished Jul 26 07:02:10 PM PDT 24
Peak memory 201156 kb
Host smart-f6e86a52-eb61-4d5a-9795-39ec2cb329a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346760966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1346760966
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.534061434
Short name T422
Test name
Test status
Simulation time 329972198336 ps
CPU time 716.47 seconds
Started Jul 26 06:54:38 PM PDT 24
Finished Jul 26 07:06:34 PM PDT 24
Peak memory 201132 kb
Host smart-11d99ee9-7f7d-4698-98bb-ea4e2299f46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534061434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.534061434
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1746098455
Short name T466
Test name
Test status
Simulation time 163429497152 ps
CPU time 102.38 seconds
Started Jul 26 06:54:46 PM PDT 24
Finished Jul 26 06:56:28 PM PDT 24
Peak memory 201160 kb
Host smart-4044373f-5a37-45ac-ab23-6356a99464c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746098455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1746098455
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.300470153
Short name T646
Test name
Test status
Simulation time 327593941632 ps
CPU time 44.34 seconds
Started Jul 26 06:54:38 PM PDT 24
Finished Jul 26 06:55:23 PM PDT 24
Peak memory 201216 kb
Host smart-8d3e9e68-edd2-404b-ac12-963146db0b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300470153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.300470153
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.4099247054
Short name T398
Test name
Test status
Simulation time 165611290793 ps
CPU time 155 seconds
Started Jul 26 06:54:39 PM PDT 24
Finished Jul 26 06:57:14 PM PDT 24
Peak memory 201152 kb
Host smart-e169f7cb-da0e-425b-987f-10b7ccb3e7bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099247054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.4099247054
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.4013633765
Short name T237
Test name
Test status
Simulation time 624413260195 ps
CPU time 808.88 seconds
Started Jul 26 06:54:46 PM PDT 24
Finished Jul 26 07:08:15 PM PDT 24
Peak memory 201136 kb
Host smart-f373f8a4-6fbc-4472-9857-472757e30daa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013633765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.4013633765
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3869157425
Short name T504
Test name
Test status
Simulation time 609960685613 ps
CPU time 1428.96 seconds
Started Jul 26 06:54:46 PM PDT 24
Finished Jul 26 07:18:36 PM PDT 24
Peak memory 201140 kb
Host smart-76e604cc-54d8-4e1d-8241-b7559284a3e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869157425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3869157425
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.789672399
Short name T343
Test name
Test status
Simulation time 138464816814 ps
CPU time 439.77 seconds
Started Jul 26 06:54:52 PM PDT 24
Finished Jul 26 07:02:12 PM PDT 24
Peak memory 201684 kb
Host smart-2d95e5fc-d0a0-4c51-b306-e7343adbffbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789672399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.789672399
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2213974925
Short name T462
Test name
Test status
Simulation time 39435068653 ps
CPU time 25.13 seconds
Started Jul 26 06:54:51 PM PDT 24
Finished Jul 26 06:55:16 PM PDT 24
Peak memory 201008 kb
Host smart-aa4bdfc1-f1e3-4931-aa36-19defee233b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213974925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2213974925
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1363296465
Short name T703
Test name
Test status
Simulation time 4740178651 ps
CPU time 6.63 seconds
Started Jul 26 06:54:54 PM PDT 24
Finished Jul 26 06:55:01 PM PDT 24
Peak memory 201016 kb
Host smart-07bd857e-c7e8-4570-a393-64a7034f2549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363296465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1363296465
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.4264200303
Short name T374
Test name
Test status
Simulation time 5763665676 ps
CPU time 7.63 seconds
Started Jul 26 06:54:37 PM PDT 24
Finished Jul 26 06:54:45 PM PDT 24
Peak memory 201052 kb
Host smart-827ea907-e58f-4fb3-89d4-df7d2327ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264200303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.4264200303
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1830102761
Short name T25
Test name
Test status
Simulation time 283476069344 ps
CPU time 600.01 seconds
Started Jul 26 06:54:51 PM PDT 24
Finished Jul 26 07:04:51 PM PDT 24
Peak memory 209844 kb
Host smart-35d7ba54-effd-49f3-a964-d616f95235e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830102761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1830102761
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3970779350
Short name T705
Test name
Test status
Simulation time 455141219972 ps
CPU time 245.67 seconds
Started Jul 26 06:54:53 PM PDT 24
Finished Jul 26 06:58:58 PM PDT 24
Peak memory 217524 kb
Host smart-b70743f0-dce9-455f-957f-354acd7e3f42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970779350 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3970779350
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.557719558
Short name T628
Test name
Test status
Simulation time 587772332 ps
CPU time 0.78 seconds
Started Jul 26 06:55:11 PM PDT 24
Finished Jul 26 06:55:12 PM PDT 24
Peak memory 200948 kb
Host smart-721b4d34-a6ad-46cd-8921-bd12dc1137ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557719558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.557719558
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3942468660
Short name T247
Test name
Test status
Simulation time 568882547132 ps
CPU time 921.48 seconds
Started Jul 26 06:55:04 PM PDT 24
Finished Jul 26 07:10:26 PM PDT 24
Peak memory 201108 kb
Host smart-fe3589b0-91f5-4182-8e2a-b116955c7522
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942468660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3942468660
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3220327294
Short name T630
Test name
Test status
Simulation time 164480040915 ps
CPU time 202.79 seconds
Started Jul 26 06:55:04 PM PDT 24
Finished Jul 26 06:58:27 PM PDT 24
Peak memory 201244 kb
Host smart-10315b47-6fb2-4334-aaba-3e7b96d42ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220327294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3220327294
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1824174542
Short name T678
Test name
Test status
Simulation time 499126515124 ps
CPU time 1103.55 seconds
Started Jul 26 06:55:04 PM PDT 24
Finished Jul 26 07:13:28 PM PDT 24
Peak memory 201124 kb
Host smart-dd2bdf6a-bdaf-41ff-ac45-f3d943abf706
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824174542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1824174542
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.977785497
Short name T783
Test name
Test status
Simulation time 166328393959 ps
CPU time 393.55 seconds
Started Jul 26 06:54:51 PM PDT 24
Finished Jul 26 07:01:25 PM PDT 24
Peak memory 201228 kb
Host smart-95fb02e1-d561-47e0-bfa5-9a93ae662ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977785497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.977785497
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3433263622
Short name T627
Test name
Test status
Simulation time 336487554051 ps
CPU time 143.46 seconds
Started Jul 26 06:54:51 PM PDT 24
Finished Jul 26 06:57:15 PM PDT 24
Peak memory 201152 kb
Host smart-fd360654-e8d0-4802-b504-55c6ccdf2851
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433263622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3433263622
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.282535514
Short name T3
Test name
Test status
Simulation time 168860589097 ps
CPU time 64.4 seconds
Started Jul 26 06:55:06 PM PDT 24
Finished Jul 26 06:56:10 PM PDT 24
Peak memory 201152 kb
Host smart-4e5bc0cc-72ee-4c7e-bac4-8e9ca123434c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282535514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.282535514
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1845161436
Short name T755
Test name
Test status
Simulation time 197796499898 ps
CPU time 429.94 seconds
Started Jul 26 06:55:04 PM PDT 24
Finished Jul 26 07:02:14 PM PDT 24
Peak memory 201140 kb
Host smart-a8f16d6a-4aab-4970-af9f-cefa517f0b1a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845161436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1845161436
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1806389741
Short name T752
Test name
Test status
Simulation time 25399210978 ps
CPU time 59.61 seconds
Started Jul 26 06:55:08 PM PDT 24
Finished Jul 26 06:56:08 PM PDT 24
Peak memory 200996 kb
Host smart-fe9c81df-e227-43cf-b732-0609e082094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806389741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1806389741
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2755630063
Short name T759
Test name
Test status
Simulation time 3469892399 ps
CPU time 7.7 seconds
Started Jul 26 06:55:13 PM PDT 24
Finished Jul 26 06:55:21 PM PDT 24
Peak memory 201016 kb
Host smart-9384aee0-c975-4c09-b39e-4cba6a77d73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755630063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2755630063
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1376410285
Short name T84
Test name
Test status
Simulation time 5740491635 ps
CPU time 4.04 seconds
Started Jul 26 06:54:53 PM PDT 24
Finished Jul 26 06:54:57 PM PDT 24
Peak memory 201104 kb
Host smart-4f52555b-23fc-4fdf-8628-26f9573f3d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376410285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1376410285
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.511947384
Short name T157
Test name
Test status
Simulation time 204486969552 ps
CPU time 448.93 seconds
Started Jul 26 06:55:12 PM PDT 24
Finished Jul 26 07:02:41 PM PDT 24
Peak memory 201176 kb
Host smart-421a3f47-95ca-4269-99db-ce3e5415cde0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511947384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
511947384
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2488332362
Short name T778
Test name
Test status
Simulation time 212472467310 ps
CPU time 205.53 seconds
Started Jul 26 06:55:09 PM PDT 24
Finished Jul 26 06:58:35 PM PDT 24
Peak memory 209948 kb
Host smart-a989e499-387c-4d6c-9ae0-6e99d543459e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488332362 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2488332362
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3555060763
Short name T523
Test name
Test status
Simulation time 510428920 ps
CPU time 1.71 seconds
Started Jul 26 06:55:18 PM PDT 24
Finished Jul 26 06:55:19 PM PDT 24
Peak memory 200956 kb
Host smart-55797d7d-b371-4c4e-81a6-1984ec446f51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555060763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3555060763
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1859109338
Short name T571
Test name
Test status
Simulation time 498013995565 ps
CPU time 713.58 seconds
Started Jul 26 06:55:18 PM PDT 24
Finished Jul 26 07:07:11 PM PDT 24
Peak memory 201116 kb
Host smart-8bb4dad1-a46f-4400-be65-ed9e9bb2e5fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859109338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1859109338
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2384725970
Short name T154
Test name
Test status
Simulation time 160539021190 ps
CPU time 351.78 seconds
Started Jul 26 06:55:09 PM PDT 24
Finished Jul 26 07:01:01 PM PDT 24
Peak memory 201248 kb
Host smart-370c1a8b-7b14-4ebc-8dd3-031648ce9793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384725970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2384725970
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1823364531
Short name T612
Test name
Test status
Simulation time 336395865689 ps
CPU time 731.79 seconds
Started Jul 26 06:55:17 PM PDT 24
Finished Jul 26 07:07:29 PM PDT 24
Peak memory 201212 kb
Host smart-ee1a54bc-5028-4c97-a4e7-1332aea99ec5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823364531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1823364531
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1465015779
Short name T622
Test name
Test status
Simulation time 160263896909 ps
CPU time 32.31 seconds
Started Jul 26 06:55:11 PM PDT 24
Finished Jul 26 06:55:44 PM PDT 24
Peak memory 201140 kb
Host smart-3ce6c13f-4930-4091-9d74-fa0d83309987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465015779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1465015779
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3663255674
Short name T533
Test name
Test status
Simulation time 328797708623 ps
CPU time 381.73 seconds
Started Jul 26 06:55:10 PM PDT 24
Finished Jul 26 07:01:31 PM PDT 24
Peak memory 201148 kb
Host smart-d6a3e524-8d65-4231-93db-100904ae257a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663255674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3663255674
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1683352142
Short name T264
Test name
Test status
Simulation time 645570873526 ps
CPU time 396.92 seconds
Started Jul 26 06:55:17 PM PDT 24
Finished Jul 26 07:01:54 PM PDT 24
Peak memory 201164 kb
Host smart-04bd7e3d-d423-4ac7-ae22-deeba058bf80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683352142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1683352142
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.332750011
Short name T568
Test name
Test status
Simulation time 618175600542 ps
CPU time 332.78 seconds
Started Jul 26 06:55:18 PM PDT 24
Finished Jul 26 07:00:51 PM PDT 24
Peak memory 201236 kb
Host smart-64602a36-b2d4-4672-8557-466908a3c4aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332750011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.332750011
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1629589234
Short name T341
Test name
Test status
Simulation time 78250924148 ps
CPU time 422.15 seconds
Started Jul 26 06:55:17 PM PDT 24
Finished Jul 26 07:02:19 PM PDT 24
Peak memory 201632 kb
Host smart-8d9d18d4-415d-4d63-8c67-6a425fd625d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629589234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1629589234
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2729180771
Short name T142
Test name
Test status
Simulation time 24116669520 ps
CPU time 25.49 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 06:55:42 PM PDT 24
Peak memory 201004 kb
Host smart-ec0f0ccd-1596-4198-b8f3-770bb84bb762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729180771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2729180771
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.59466230
Short name T681
Test name
Test status
Simulation time 5116683170 ps
CPU time 6.11 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 06:55:22 PM PDT 24
Peak memory 200956 kb
Host smart-09a8e8a1-9b52-4a15-b7bf-39d3740cc334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59466230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.59466230
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1355763288
Short name T677
Test name
Test status
Simulation time 5971037525 ps
CPU time 15.02 seconds
Started Jul 26 06:55:11 PM PDT 24
Finished Jul 26 06:55:26 PM PDT 24
Peak memory 201044 kb
Host smart-b142c24e-9cb0-4555-b437-f7de522455b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355763288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1355763288
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2088745265
Short name T274
Test name
Test status
Simulation time 332355878148 ps
CPU time 416.16 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 07:02:13 PM PDT 24
Peak memory 201180 kb
Host smart-3d1df7f6-fd6e-4b66-854d-b1f9213c0bf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088745265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2088745265
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1389651965
Short name T23
Test name
Test status
Simulation time 41972175864 ps
CPU time 112 seconds
Started Jul 26 06:55:19 PM PDT 24
Finished Jul 26 06:57:11 PM PDT 24
Peak memory 209924 kb
Host smart-5b3fd193-e145-4862-9ec1-4478d5c1bdeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389651965 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1389651965
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3929894084
Short name T65
Test name
Test status
Simulation time 287176438 ps
CPU time 0.93 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 06:55:17 PM PDT 24
Peak memory 200964 kb
Host smart-f4ce51af-b4de-4b7e-b32c-7129ed3a63bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929894084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3929894084
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.4135505044
Short name T669
Test name
Test status
Simulation time 167494768542 ps
CPU time 362.91 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 07:01:19 PM PDT 24
Peak memory 201140 kb
Host smart-7c62314c-b2ee-410e-8896-a5a38db6bacb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135505044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.4135505044
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.197519586
Short name T160
Test name
Test status
Simulation time 536879820522 ps
CPU time 310.7 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 07:00:27 PM PDT 24
Peak memory 201120 kb
Host smart-29e478e6-a86d-4585-91b1-131d81c18ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197519586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.197519586
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.636609396
Short name T382
Test name
Test status
Simulation time 501079369863 ps
CPU time 625.48 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 07:05:41 PM PDT 24
Peak memory 201144 kb
Host smart-5964611a-14db-495e-b35f-c39a8ee96f78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=636609396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.636609396
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1763011612
Short name T159
Test name
Test status
Simulation time 170107250473 ps
CPU time 30.54 seconds
Started Jul 26 06:55:19 PM PDT 24
Finished Jul 26 06:55:49 PM PDT 24
Peak memory 201208 kb
Host smart-29fb15d4-65fa-4051-9f00-538ec7a89f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763011612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1763011612
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1239121644
Short name T418
Test name
Test status
Simulation time 502665915157 ps
CPU time 639.02 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 07:05:56 PM PDT 24
Peak memory 201164 kb
Host smart-1ac703ef-8731-4a5b-a33d-3763db8d5dd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239121644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1239121644
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3155053595
Short name T754
Test name
Test status
Simulation time 575674178181 ps
CPU time 87.99 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 06:56:44 PM PDT 24
Peak memory 201160 kb
Host smart-29637afd-e0c0-4c8c-9fca-ab68aee5b84f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155053595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3155053595
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.453504763
Short name T212
Test name
Test status
Simulation time 120101980921 ps
CPU time 502.29 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 07:03:38 PM PDT 24
Peak memory 201640 kb
Host smart-54256443-c6cc-4db7-9136-1c2913c9e9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453504763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.453504763
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3619785503
Short name T439
Test name
Test status
Simulation time 20856349969 ps
CPU time 32.23 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 06:55:49 PM PDT 24
Peak memory 201072 kb
Host smart-ca698697-0487-41b8-80ae-d50a1fe681b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619785503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3619785503
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3105635516
Short name T410
Test name
Test status
Simulation time 5248210981 ps
CPU time 7.06 seconds
Started Jul 26 06:55:17 PM PDT 24
Finished Jul 26 06:55:24 PM PDT 24
Peak memory 201008 kb
Host smart-925dc75e-dbb7-4c86-98e8-e91405f5b727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105635516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3105635516
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2203346793
Short name T489
Test name
Test status
Simulation time 5659534656 ps
CPU time 14.18 seconds
Started Jul 26 06:55:15 PM PDT 24
Finished Jul 26 06:55:29 PM PDT 24
Peak memory 201044 kb
Host smart-367c1678-9b03-4fdb-b503-39e051d81680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203346793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2203346793
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.4207516162
Short name T33
Test name
Test status
Simulation time 172732928114 ps
CPU time 97.72 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 06:56:54 PM PDT 24
Peak memory 201168 kb
Host smart-3c1b1710-9930-431a-9833-4bc1ad8a5f29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207516162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.4207516162
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2135017852
Short name T299
Test name
Test status
Simulation time 243022340767 ps
CPU time 152.8 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 06:57:49 PM PDT 24
Peak memory 216976 kb
Host smart-7e8eeb8e-7f80-4e97-9d8a-fad61e7df7de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135017852 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2135017852
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.845691368
Short name T579
Test name
Test status
Simulation time 453548354 ps
CPU time 1.61 seconds
Started Jul 26 06:55:26 PM PDT 24
Finished Jul 26 06:55:28 PM PDT 24
Peak memory 200928 kb
Host smart-9ee33408-002d-4e2b-a8fe-b50c69a0de8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845691368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.845691368
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1404372514
Short name T474
Test name
Test status
Simulation time 368698032683 ps
CPU time 896.06 seconds
Started Jul 26 06:55:25 PM PDT 24
Finished Jul 26 07:10:22 PM PDT 24
Peak memory 201180 kb
Host smart-216aaf55-7765-4887-a4a1-17b8fd7d444c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404372514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1404372514
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.164669293
Short name T633
Test name
Test status
Simulation time 543068624849 ps
CPU time 1122.64 seconds
Started Jul 26 06:55:25 PM PDT 24
Finished Jul 26 07:14:08 PM PDT 24
Peak memory 201196 kb
Host smart-f0c99a24-7a88-4266-b35e-c38d1fbef294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164669293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.164669293
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2105413295
Short name T572
Test name
Test status
Simulation time 169986504909 ps
CPU time 389.14 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 07:01:46 PM PDT 24
Peak memory 201144 kb
Host smart-b1eecb25-0793-4673-bf47-6f4f34a4cea6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105413295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2105413295
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3300786171
Short name T363
Test name
Test status
Simulation time 163218463198 ps
CPU time 291.8 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 07:00:08 PM PDT 24
Peak memory 201148 kb
Host smart-ea958858-191f-4e8a-b021-566e664cef46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300786171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3300786171
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1220082728
Short name T582
Test name
Test status
Simulation time 320278427276 ps
CPU time 208.14 seconds
Started Jul 26 06:55:18 PM PDT 24
Finished Jul 26 06:58:46 PM PDT 24
Peak memory 201144 kb
Host smart-4a9d3e15-b549-4b7c-a324-732629d5b78a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220082728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1220082728
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.577711888
Short name T151
Test name
Test status
Simulation time 550535877055 ps
CPU time 255.61 seconds
Started Jul 26 06:55:25 PM PDT 24
Finished Jul 26 06:59:41 PM PDT 24
Peak memory 201148 kb
Host smart-d3828308-4af2-426e-9f62-b067a0c12f49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577711888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.577711888
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2904664185
Short name T27
Test name
Test status
Simulation time 191811474017 ps
CPU time 108.12 seconds
Started Jul 26 06:55:24 PM PDT 24
Finished Jul 26 06:57:12 PM PDT 24
Peak memory 201132 kb
Host smart-7e53fd79-e968-4fe0-b033-a038f8b3d648
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904664185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2904664185
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.4209366175
Short name T446
Test name
Test status
Simulation time 62424206224 ps
CPU time 251.99 seconds
Started Jul 26 06:55:27 PM PDT 24
Finished Jul 26 06:59:39 PM PDT 24
Peak memory 201624 kb
Host smart-420e5675-a87f-47dc-be86-e39a52527af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209366175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.4209366175
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.508564551
Short name T427
Test name
Test status
Simulation time 28712878222 ps
CPU time 7.85 seconds
Started Jul 26 06:55:26 PM PDT 24
Finished Jul 26 06:55:34 PM PDT 24
Peak memory 200964 kb
Host smart-3b26e243-2151-41fe-8e48-cc8bbdbe480d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508564551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.508564551
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1522391860
Short name T185
Test name
Test status
Simulation time 2975163815 ps
CPU time 3.83 seconds
Started Jul 26 06:55:26 PM PDT 24
Finished Jul 26 06:55:30 PM PDT 24
Peak memory 201020 kb
Host smart-9be8a55a-c98f-460d-ba16-1bea28be0912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522391860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1522391860
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2785993186
Short name T29
Test name
Test status
Simulation time 5861991247 ps
CPU time 13.85 seconds
Started Jul 26 06:55:16 PM PDT 24
Finished Jul 26 06:55:30 PM PDT 24
Peak memory 201000 kb
Host smart-71279c2d-b445-4058-b5de-ec69ad9061a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785993186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2785993186
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.979355756
Short name T34
Test name
Test status
Simulation time 337076629174 ps
CPU time 756.07 seconds
Started Jul 26 06:55:26 PM PDT 24
Finished Jul 26 07:08:03 PM PDT 24
Peak memory 201220 kb
Host smart-0d95ccba-1e46-4990-b2f6-07ef6767bdea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979355756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
979355756
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3165956863
Short name T325
Test name
Test status
Simulation time 126017483603 ps
CPU time 103.49 seconds
Started Jul 26 06:55:26 PM PDT 24
Finished Jul 26 06:57:10 PM PDT 24
Peak memory 210184 kb
Host smart-7c9b8649-654d-4702-a2b0-78f8018a484e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165956863 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3165956863
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.729582618
Short name T680
Test name
Test status
Simulation time 351808819 ps
CPU time 1.15 seconds
Started Jul 26 06:55:40 PM PDT 24
Finished Jul 26 06:55:41 PM PDT 24
Peak memory 200920 kb
Host smart-0e99e03b-ea5e-4d1a-a584-ce98eb5fde68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729582618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.729582618
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2267449318
Short name T493
Test name
Test status
Simulation time 200730735203 ps
CPU time 131.1 seconds
Started Jul 26 06:55:34 PM PDT 24
Finished Jul 26 06:57:45 PM PDT 24
Peak memory 201180 kb
Host smart-3894709c-7c0d-4cb8-9d5c-faa9f643f012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267449318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2267449318
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.848998099
Short name T787
Test name
Test status
Simulation time 164798559451 ps
CPU time 123.67 seconds
Started Jul 26 06:55:32 PM PDT 24
Finished Jul 26 06:57:35 PM PDT 24
Peak memory 201156 kb
Host smart-c996657c-bf8d-4dde-b442-5d877c8b2420
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=848998099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.848998099
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3152235191
Short name T289
Test name
Test status
Simulation time 487651195100 ps
CPU time 539.64 seconds
Started Jul 26 06:55:25 PM PDT 24
Finished Jul 26 07:04:24 PM PDT 24
Peak memory 201160 kb
Host smart-eb9ca8ea-deca-451d-88d7-3bb81c58f078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152235191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3152235191
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1756808167
Short name T449
Test name
Test status
Simulation time 333944260571 ps
CPU time 244.27 seconds
Started Jul 26 06:55:34 PM PDT 24
Finished Jul 26 06:59:38 PM PDT 24
Peak memory 201248 kb
Host smart-a2e0124e-f481-4a0f-975a-79c8e43b6adf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756808167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1756808167
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.723077302
Short name T792
Test name
Test status
Simulation time 196332716218 ps
CPU time 356.21 seconds
Started Jul 26 06:55:33 PM PDT 24
Finished Jul 26 07:01:29 PM PDT 24
Peak memory 201248 kb
Host smart-5b3b4189-5e27-4d96-b82e-150a2aafc85e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723077302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.723077302
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2781159508
Short name T408
Test name
Test status
Simulation time 390425317075 ps
CPU time 461.21 seconds
Started Jul 26 06:55:33 PM PDT 24
Finished Jul 26 07:03:14 PM PDT 24
Peak memory 201100 kb
Host smart-b9431ef9-3849-41ed-98a6-4dc9f35fd9ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781159508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2781159508
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.219930359
Short name T656
Test name
Test status
Simulation time 127042235041 ps
CPU time 396.89 seconds
Started Jul 26 06:55:41 PM PDT 24
Finished Jul 26 07:02:18 PM PDT 24
Peak memory 201584 kb
Host smart-548e3483-9b98-4d7c-8e85-32a7663f62ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219930359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.219930359
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.277759280
Short name T648
Test name
Test status
Simulation time 25694479306 ps
CPU time 17.22 seconds
Started Jul 26 06:55:41 PM PDT 24
Finished Jul 26 06:55:58 PM PDT 24
Peak memory 200980 kb
Host smart-91f3fca0-a81a-4b1e-9d72-032fbf4ae1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277759280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.277759280
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1958495550
Short name T478
Test name
Test status
Simulation time 3650232832 ps
CPU time 4.98 seconds
Started Jul 26 06:55:32 PM PDT 24
Finished Jul 26 06:55:37 PM PDT 24
Peak memory 201008 kb
Host smart-cb1fb88d-beb6-41d5-afa2-f995286908fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958495550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1958495550
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3766332426
Short name T480
Test name
Test status
Simulation time 5622071166 ps
CPU time 11.1 seconds
Started Jul 26 06:55:25 PM PDT 24
Finished Jul 26 06:55:36 PM PDT 24
Peak memory 201036 kb
Host smart-a0d65818-8f49-477d-a46a-7528cd5c3649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766332426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3766332426
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3726384757
Short name T652
Test name
Test status
Simulation time 165926075090 ps
CPU time 109.55 seconds
Started Jul 26 06:55:45 PM PDT 24
Finished Jul 26 06:57:34 PM PDT 24
Peak memory 201152 kb
Host smart-80f648d9-0e74-47f4-a9b9-61f393ff4dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726384757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3726384757
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2742112896
Short name T618
Test name
Test status
Simulation time 427570539 ps
CPU time 1.49 seconds
Started Jul 26 06:55:47 PM PDT 24
Finished Jul 26 06:55:48 PM PDT 24
Peak memory 200976 kb
Host smart-22cb71dd-762f-4b23-bfd9-5523e713188d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742112896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2742112896
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.636753813
Short name T333
Test name
Test status
Simulation time 523098397863 ps
CPU time 825.81 seconds
Started Jul 26 06:55:41 PM PDT 24
Finished Jul 26 07:09:27 PM PDT 24
Peak memory 201248 kb
Host smart-8b607c16-0611-4c4f-ba0b-e77cedb40f88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636753813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.636753813
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3760113093
Short name T407
Test name
Test status
Simulation time 161752435783 ps
CPU time 346.03 seconds
Started Jul 26 06:55:39 PM PDT 24
Finished Jul 26 07:01:26 PM PDT 24
Peak memory 201224 kb
Host smart-761e3182-3085-4803-9216-0fee7d12cbaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760113093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3760113093
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3482969251
Short name T273
Test name
Test status
Simulation time 163017888513 ps
CPU time 355.86 seconds
Started Jul 26 06:55:41 PM PDT 24
Finished Jul 26 07:01:37 PM PDT 24
Peak memory 201220 kb
Host smart-b8dbace1-0156-4fce-b7eb-1b4e72bb3a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482969251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3482969251
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.971174094
Short name T406
Test name
Test status
Simulation time 164261930483 ps
CPU time 54.73 seconds
Started Jul 26 06:55:40 PM PDT 24
Finished Jul 26 06:56:35 PM PDT 24
Peak memory 201168 kb
Host smart-a03d24be-050d-4dd1-82e0-16adf2bb6781
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=971174094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.971174094
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.858352636
Short name T296
Test name
Test status
Simulation time 165653862125 ps
CPU time 91.05 seconds
Started Jul 26 06:55:41 PM PDT 24
Finished Jul 26 06:57:12 PM PDT 24
Peak memory 201200 kb
Host smart-e4274932-220c-46d6-ac3e-95259ef38294
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858352636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.858352636
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3218103060
Short name T425
Test name
Test status
Simulation time 390267464857 ps
CPU time 970.69 seconds
Started Jul 26 06:55:40 PM PDT 24
Finished Jul 26 07:11:51 PM PDT 24
Peak memory 201212 kb
Host smart-8b8b60c2-2803-4813-8135-316267d0fe1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218103060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3218103060
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2334543194
Short name T602
Test name
Test status
Simulation time 34729794272 ps
CPU time 68.12 seconds
Started Jul 26 06:55:47 PM PDT 24
Finished Jul 26 06:56:55 PM PDT 24
Peak memory 201024 kb
Host smart-41fcf03e-12c9-4b31-ad9c-c7d10009eca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334543194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2334543194
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2162009506
Short name T617
Test name
Test status
Simulation time 3590369123 ps
CPU time 8.81 seconds
Started Jul 26 06:55:47 PM PDT 24
Finished Jul 26 06:55:56 PM PDT 24
Peak memory 201016 kb
Host smart-e8f4cc23-7003-4200-aa61-c1a5f2b5dfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162009506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2162009506
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.4180627633
Short name T402
Test name
Test status
Simulation time 5761727147 ps
CPU time 13.72 seconds
Started Jul 26 06:55:41 PM PDT 24
Finished Jul 26 06:55:55 PM PDT 24
Peak memory 201020 kb
Host smart-e921d658-f3a0-44a8-af21-312231d9dada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180627633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.4180627633
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1317504294
Short name T800
Test name
Test status
Simulation time 9155637952 ps
CPU time 8.57 seconds
Started Jul 26 06:55:48 PM PDT 24
Finished Jul 26 06:55:57 PM PDT 24
Peak memory 201376 kb
Host smart-8a59fb5e-59fd-44f6-9b6d-c6de3c2feb97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317504294 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1317504294
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3239821430
Short name T528
Test name
Test status
Simulation time 499955024 ps
CPU time 1.2 seconds
Started Jul 26 06:55:55 PM PDT 24
Finished Jul 26 06:55:57 PM PDT 24
Peak memory 201044 kb
Host smart-8b20d4f1-3235-4530-8353-6148f74a2f0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239821430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3239821430
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3559389420
Short name T535
Test name
Test status
Simulation time 523319845059 ps
CPU time 337.16 seconds
Started Jul 26 06:55:54 PM PDT 24
Finished Jul 26 07:01:32 PM PDT 24
Peak memory 201208 kb
Host smart-278dc3ce-c03b-4f0b-96e1-022ef1d56435
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559389420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3559389420
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3842510931
Short name T255
Test name
Test status
Simulation time 164796328752 ps
CPU time 112.49 seconds
Started Jul 26 06:55:54 PM PDT 24
Finished Jul 26 06:57:46 PM PDT 24
Peak memory 201152 kb
Host smart-ad363001-bd26-4c16-b583-48f02bf23f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842510931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3842510931
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2052775792
Short name T644
Test name
Test status
Simulation time 506363961744 ps
CPU time 1143.54 seconds
Started Jul 26 06:55:48 PM PDT 24
Finished Jul 26 07:14:52 PM PDT 24
Peak memory 201212 kb
Host smart-08907d1c-a928-4b40-b413-bcc3f1a76d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052775792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2052775792
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.324572943
Short name T719
Test name
Test status
Simulation time 166024502314 ps
CPU time 379.86 seconds
Started Jul 26 06:55:48 PM PDT 24
Finished Jul 26 07:02:08 PM PDT 24
Peak memory 201240 kb
Host smart-1c30b272-9bde-4470-b7e8-f84f64cc2585
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=324572943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.324572943
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.4013944573
Short name T104
Test name
Test status
Simulation time 167154854467 ps
CPU time 197.58 seconds
Started Jul 26 06:55:47 PM PDT 24
Finished Jul 26 06:59:04 PM PDT 24
Peak memory 201148 kb
Host smart-381eaf18-72c4-40f0-baa3-7c4510f41088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013944573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.4013944573
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.921866350
Short name T639
Test name
Test status
Simulation time 327541635239 ps
CPU time 181.13 seconds
Started Jul 26 06:55:49 PM PDT 24
Finished Jul 26 06:58:50 PM PDT 24
Peak memory 201240 kb
Host smart-35a953ab-a3fb-4416-9832-300b52206368
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=921866350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.921866350
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.316201436
Short name T527
Test name
Test status
Simulation time 181963129569 ps
CPU time 393.12 seconds
Started Jul 26 06:55:55 PM PDT 24
Finished Jul 26 07:02:29 PM PDT 24
Peak memory 201244 kb
Host smart-05995f47-33cd-4daa-b63a-48ca1051048e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316201436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.316201436
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2574670106
Short name T685
Test name
Test status
Simulation time 196882551139 ps
CPU time 179.23 seconds
Started Jul 26 06:55:55 PM PDT 24
Finished Jul 26 06:58:54 PM PDT 24
Peak memory 201140 kb
Host smart-b965324f-7ce4-4ff4-a816-0a966f541cb0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574670106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2574670106
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1671318370
Short name T206
Test name
Test status
Simulation time 115935490659 ps
CPU time 401.44 seconds
Started Jul 26 06:55:56 PM PDT 24
Finished Jul 26 07:02:37 PM PDT 24
Peak memory 201620 kb
Host smart-3532e7e7-09e4-4a22-84d3-29adbb85d03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671318370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1671318370
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1847660723
Short name T534
Test name
Test status
Simulation time 32780743047 ps
CPU time 41.25 seconds
Started Jul 26 06:55:57 PM PDT 24
Finished Jul 26 06:56:38 PM PDT 24
Peak memory 200888 kb
Host smart-43c5851a-ba21-486f-84e4-eeb6103c5e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847660723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1847660723
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1608605994
Short name T638
Test name
Test status
Simulation time 2859687682 ps
CPU time 1.25 seconds
Started Jul 26 06:55:54 PM PDT 24
Finished Jul 26 06:55:56 PM PDT 24
Peak memory 200976 kb
Host smart-78f36dd4-0c03-4899-a5fd-7e5821e1c00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608605994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1608605994
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3277837950
Short name T714
Test name
Test status
Simulation time 5873048392 ps
CPU time 4.49 seconds
Started Jul 26 06:55:48 PM PDT 24
Finished Jul 26 06:55:52 PM PDT 24
Peak memory 201104 kb
Host smart-d03e8fe5-afb6-4c4f-a858-565c467c34a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277837950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3277837950
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2976757703
Short name T312
Test name
Test status
Simulation time 175785708793 ps
CPU time 19.24 seconds
Started Jul 26 06:55:55 PM PDT 24
Finished Jul 26 06:56:14 PM PDT 24
Peak memory 201160 kb
Host smart-778aa3aa-17e5-4ae5-9554-20d7ba60d6ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976757703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2976757703
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1957769350
Short name T801
Test name
Test status
Simulation time 338365677465 ps
CPU time 308.09 seconds
Started Jul 26 06:55:54 PM PDT 24
Finished Jul 26 07:01:02 PM PDT 24
Peak memory 218288 kb
Host smart-726aabd6-3c39-4602-8375-f37f58649ff2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957769350 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1957769350
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.24106976
Short name T370
Test name
Test status
Simulation time 378928223 ps
CPU time 0.7 seconds
Started Jul 26 06:56:02 PM PDT 24
Finished Jul 26 06:56:02 PM PDT 24
Peak memory 200948 kb
Host smart-57fd45bd-2071-40f4-9e85-a4bf0cc10f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24106976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.24106976
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2941567658
Short name T313
Test name
Test status
Simulation time 325472218977 ps
CPU time 677.91 seconds
Started Jul 26 06:56:01 PM PDT 24
Finished Jul 26 07:07:20 PM PDT 24
Peak memory 201132 kb
Host smart-fc685c97-0aad-4af2-874e-76c078ceca8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941567658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2941567658
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.902744843
Short name T481
Test name
Test status
Simulation time 174973762126 ps
CPU time 26.63 seconds
Started Jul 26 06:56:03 PM PDT 24
Finished Jul 26 06:56:29 PM PDT 24
Peak memory 201164 kb
Host smart-e90e2a15-56f0-47fe-ba28-e00f96c3c22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902744843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.902744843
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.4062536109
Short name T223
Test name
Test status
Simulation time 166775916111 ps
CPU time 363.19 seconds
Started Jul 26 06:55:55 PM PDT 24
Finished Jul 26 07:01:58 PM PDT 24
Peak memory 201136 kb
Host smart-6e044d9d-711c-45e6-9d8c-a0f88719da14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062536109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4062536109
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3645503923
Short name T510
Test name
Test status
Simulation time 169503193376 ps
CPU time 150.65 seconds
Started Jul 26 06:55:55 PM PDT 24
Finished Jul 26 06:58:25 PM PDT 24
Peak memory 201248 kb
Host smart-2c447b26-cc48-4086-867d-51c081348778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645503923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3645503923
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.519365191
Short name T345
Test name
Test status
Simulation time 486850918740 ps
CPU time 614.34 seconds
Started Jul 26 06:55:57 PM PDT 24
Finished Jul 26 07:06:12 PM PDT 24
Peak memory 201172 kb
Host smart-8c890b55-6eaa-489b-b151-2827e9cb0acc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=519365191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.519365191
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2676906108
Short name T183
Test name
Test status
Simulation time 345064170937 ps
CPU time 153.11 seconds
Started Jul 26 06:56:03 PM PDT 24
Finished Jul 26 06:58:37 PM PDT 24
Peak memory 201124 kb
Host smart-1eb3d8df-0d10-4719-aa3f-edd185a99aae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676906108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2676906108
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.268409613
Short name T728
Test name
Test status
Simulation time 196856351523 ps
CPU time 166.19 seconds
Started Jul 26 06:56:01 PM PDT 24
Finished Jul 26 06:58:47 PM PDT 24
Peak memory 201152 kb
Host smart-b59aa3fe-b996-4d66-8cde-06b9e44fc709
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268409613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.268409613
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3689348039
Short name T339
Test name
Test status
Simulation time 88552608291 ps
CPU time 261.39 seconds
Started Jul 26 06:56:03 PM PDT 24
Finished Jul 26 07:00:24 PM PDT 24
Peak memory 201652 kb
Host smart-166aea73-a06f-49e8-a32a-b5c43f9d4efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689348039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3689348039
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.326249077
Short name T404
Test name
Test status
Simulation time 25904424773 ps
CPU time 57.28 seconds
Started Jul 26 06:56:03 PM PDT 24
Finished Jul 26 06:57:00 PM PDT 24
Peak memory 201020 kb
Host smart-32f3a0dd-a82c-4eff-ade1-8b84d70252c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326249077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.326249077
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1743306531
Short name T701
Test name
Test status
Simulation time 4121188704 ps
CPU time 3.23 seconds
Started Jul 26 06:56:04 PM PDT 24
Finished Jul 26 06:56:07 PM PDT 24
Peak memory 200848 kb
Host smart-4f53cfd4-509f-41f2-982d-a7992d6c38ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743306531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1743306531
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.4141949674
Short name T367
Test name
Test status
Simulation time 5757577476 ps
CPU time 4.09 seconds
Started Jul 26 06:55:58 PM PDT 24
Finished Jul 26 06:56:02 PM PDT 24
Peak memory 200884 kb
Host smart-18a92b6f-ae5b-4e46-9ef6-7cb04ddfe9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141949674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.4141949674
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3922172137
Short name T261
Test name
Test status
Simulation time 186832108269 ps
CPU time 228.43 seconds
Started Jul 26 06:56:03 PM PDT 24
Finished Jul 26 06:59:51 PM PDT 24
Peak memory 209928 kb
Host smart-ce3862f3-f027-4e41-85de-066cfb1bbacf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922172137 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3922172137
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1967654757
Short name T368
Test name
Test status
Simulation time 410896446 ps
CPU time 1.08 seconds
Started Jul 26 06:56:10 PM PDT 24
Finished Jul 26 06:56:11 PM PDT 24
Peak memory 200936 kb
Host smart-72cf31ae-deec-4d59-9246-6c3f9f0e9f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967654757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1967654757
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4064059090
Short name T521
Test name
Test status
Simulation time 331434664713 ps
CPU time 214.57 seconds
Started Jul 26 06:56:12 PM PDT 24
Finished Jul 26 06:59:46 PM PDT 24
Peak memory 201224 kb
Host smart-8ab626a5-c697-423b-9b75-93922747ef70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064059090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4064059090
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.200546214
Short name T389
Test name
Test status
Simulation time 323298496219 ps
CPU time 781.16 seconds
Started Jul 26 06:56:12 PM PDT 24
Finished Jul 26 07:09:13 PM PDT 24
Peak memory 201168 kb
Host smart-29f6a2db-1fd4-42a3-9ed4-8f6b2cd6b5ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=200546214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.200546214
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1416714224
Short name T727
Test name
Test status
Simulation time 331623444525 ps
CPU time 233.52 seconds
Started Jul 26 06:56:09 PM PDT 24
Finished Jul 26 07:00:03 PM PDT 24
Peak memory 201204 kb
Host smart-9b70743f-bb70-429e-a51a-3076d9265278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416714224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1416714224
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2771520771
Short name T744
Test name
Test status
Simulation time 165477685694 ps
CPU time 381.74 seconds
Started Jul 26 06:56:09 PM PDT 24
Finished Jul 26 07:02:31 PM PDT 24
Peak memory 201160 kb
Host smart-1f0178d0-43d7-4381-a114-23b087141f82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771520771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2771520771
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2770140104
Short name T305
Test name
Test status
Simulation time 348987784555 ps
CPU time 203.93 seconds
Started Jul 26 06:56:10 PM PDT 24
Finished Jul 26 06:59:34 PM PDT 24
Peak memory 201192 kb
Host smart-af5d2c27-81f7-445a-af63-1e4ce1cde0f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770140104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2770140104
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2894293331
Short name T775
Test name
Test status
Simulation time 590652633858 ps
CPU time 237.38 seconds
Started Jul 26 06:56:09 PM PDT 24
Finished Jul 26 07:00:07 PM PDT 24
Peak memory 201184 kb
Host smart-7eec0229-b441-4529-8a4b-1be4a67b4438
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894293331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2894293331
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4013883404
Short name T712
Test name
Test status
Simulation time 69497290865 ps
CPU time 213.32 seconds
Started Jul 26 06:56:11 PM PDT 24
Finished Jul 26 06:59:44 PM PDT 24
Peak memory 201624 kb
Host smart-dc4805f1-5231-481e-ad0a-55d186a6599e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013883404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4013883404
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1264447337
Short name T468
Test name
Test status
Simulation time 40773652925 ps
CPU time 100.01 seconds
Started Jul 26 06:56:11 PM PDT 24
Finished Jul 26 06:57:51 PM PDT 24
Peak memory 201024 kb
Host smart-0bfd3f7f-c96d-47cb-aee2-d622cb6960f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264447337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1264447337
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2856257111
Short name T564
Test name
Test status
Simulation time 4587651859 ps
CPU time 11.14 seconds
Started Jul 26 06:56:09 PM PDT 24
Finished Jul 26 06:56:21 PM PDT 24
Peak memory 201032 kb
Host smart-327957b1-0717-4f1e-a89b-b12c65e1599b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856257111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2856257111
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1635051761
Short name T615
Test name
Test status
Simulation time 5793762175 ps
CPU time 7.65 seconds
Started Jul 26 06:56:09 PM PDT 24
Finished Jul 26 06:56:16 PM PDT 24
Peak memory 201000 kb
Host smart-3d07c402-e489-4d2d-9e67-4fb2f847c4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635051761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1635051761
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2531080058
Short name T292
Test name
Test status
Simulation time 358041413715 ps
CPU time 205.36 seconds
Started Jul 26 06:56:12 PM PDT 24
Finished Jul 26 06:59:37 PM PDT 24
Peak memory 201164 kb
Host smart-0edbbfeb-0e89-4a94-a256-eb9a574e53a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531080058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2531080058
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2585420550
Short name T16
Test name
Test status
Simulation time 155621079847 ps
CPU time 364.63 seconds
Started Jul 26 06:56:11 PM PDT 24
Finished Jul 26 07:02:16 PM PDT 24
Peak memory 209916 kb
Host smart-92e93135-ba3b-4b9b-8120-f397afb75cfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585420550 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2585420550
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1408527791
Short name T379
Test name
Test status
Simulation time 459526150 ps
CPU time 1.08 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:50:00 PM PDT 24
Peak memory 200920 kb
Host smart-2904c32d-3b52-46d4-a96c-9b83e816b4c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408527791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1408527791
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2680157807
Short name T552
Test name
Test status
Simulation time 178090029677 ps
CPU time 390.35 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 06:56:26 PM PDT 24
Peak memory 201148 kb
Host smart-a3fcfc38-1e78-425f-9297-a3b7510621fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680157807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2680157807
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2090509210
Short name T742
Test name
Test status
Simulation time 159288849371 ps
CPU time 386.84 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:56:25 PM PDT 24
Peak memory 201144 kb
Host smart-f99c58a3-ceb9-4b61-93b2-d753ab11c1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090509210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2090509210
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3189051774
Short name T174
Test name
Test status
Simulation time 164800025959 ps
CPU time 78.24 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:51:15 PM PDT 24
Peak memory 201216 kb
Host smart-31a820b5-c3fa-428d-b3a7-4751cc25d19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189051774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3189051774
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.685215497
Short name T378
Test name
Test status
Simulation time 161306234120 ps
CPU time 401.63 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:56:39 PM PDT 24
Peak memory 201232 kb
Host smart-b6975531-693e-4530-835c-b3568577b694
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=685215497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.685215497
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.609886447
Short name T9
Test name
Test status
Simulation time 503465965933 ps
CPU time 729.73 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 07:02:05 PM PDT 24
Peak memory 201152 kb
Host smart-9c11b426-e447-4ec9-b7be-dd8a9500a327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609886447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.609886447
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2525446810
Short name T526
Test name
Test status
Simulation time 326326630391 ps
CPU time 141.82 seconds
Started Jul 26 06:49:55 PM PDT 24
Finished Jul 26 06:52:17 PM PDT 24
Peak memory 201144 kb
Host smart-71e77a09-cda4-4f38-a989-f63234737f29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525446810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2525446810
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2881246264
Short name T365
Test name
Test status
Simulation time 612079476688 ps
CPU time 694.64 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 07:01:33 PM PDT 24
Peak memory 201144 kb
Host smart-e021e4b8-250e-490b-8221-04e2fef57768
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881246264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2881246264
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3989786435
Short name T659
Test name
Test status
Simulation time 97366657009 ps
CPU time 357.41 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:55:54 PM PDT 24
Peak memory 201612 kb
Host smart-de4f81cf-6bcd-4aa2-a71a-5b1fb33350f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989786435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3989786435
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2437166461
Short name T673
Test name
Test status
Simulation time 40418689719 ps
CPU time 96.25 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:51:36 PM PDT 24
Peak memory 201000 kb
Host smart-f513495e-aa5a-426a-98e0-681704021f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437166461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2437166461
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1553062239
Short name T347
Test name
Test status
Simulation time 3222143992 ps
CPU time 8.47 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 06:50:05 PM PDT 24
Peak memory 200992 kb
Host smart-dd076b84-6667-4055-b732-a696b13612f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553062239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1553062239
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2040917641
Short name T30
Test name
Test status
Simulation time 5613930914 ps
CPU time 4.28 seconds
Started Jul 26 06:49:44 PM PDT 24
Finished Jul 26 06:49:49 PM PDT 24
Peak memory 200980 kb
Host smart-7f543acb-801c-4683-80a0-fab2cda7dffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040917641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2040917641
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3030190180
Short name T213
Test name
Test status
Simulation time 132336481178 ps
CPU time 325.04 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:55:23 PM PDT 24
Peak memory 201652 kb
Host smart-8a6ecf33-200a-4793-a1a8-ae0c71f651c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030190180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3030190180
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.916617837
Short name T20
Test name
Test status
Simulation time 266526614094 ps
CPU time 107.39 seconds
Started Jul 26 06:49:55 PM PDT 24
Finished Jul 26 06:51:42 PM PDT 24
Peak memory 211316 kb
Host smart-ab9898b8-2356-4ada-a515-1133e147530d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916617837 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.916617837
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2048731843
Short name T42
Test name
Test status
Simulation time 527581372 ps
CPU time 0.96 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:49:58 PM PDT 24
Peak memory 200876 kb
Host smart-f9931e6c-f39b-407d-9545-2ba734d2df46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048731843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2048731843
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2512773106
Short name T244
Test name
Test status
Simulation time 166486745219 ps
CPU time 196.76 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 06:53:13 PM PDT 24
Peak memory 201168 kb
Host smart-aef8071b-0031-4d01-b74b-a51d95a9e1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512773106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2512773106
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3808372136
Short name T642
Test name
Test status
Simulation time 319392235386 ps
CPU time 757.75 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 07:02:35 PM PDT 24
Peak memory 201088 kb
Host smart-cf38e93c-414f-4bf5-96d4-a6d278886477
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808372136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3808372136
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1946506087
Short name T497
Test name
Test status
Simulation time 165210101268 ps
CPU time 48.14 seconds
Started Jul 26 06:49:59 PM PDT 24
Finished Jul 26 06:50:47 PM PDT 24
Peak memory 201164 kb
Host smart-493562ec-3615-4efb-a0c0-742388f8409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946506087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1946506087
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2426420509
Short name T710
Test name
Test status
Simulation time 161256838199 ps
CPU time 23.72 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 06:50:20 PM PDT 24
Peak memory 201164 kb
Host smart-bea9aed8-3f9b-4eaa-bd0f-83af70490e20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426420509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2426420509
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1012031266
Short name T90
Test name
Test status
Simulation time 358504782937 ps
CPU time 122.85 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:52:00 PM PDT 24
Peak memory 200992 kb
Host smart-0366e58d-94a8-4947-a91f-9025595e7824
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012031266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1012031266
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1924398608
Short name T762
Test name
Test status
Simulation time 590443567873 ps
CPU time 339.54 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:55:36 PM PDT 24
Peak memory 201244 kb
Host smart-56d392b7-c967-45cd-93f5-74dc131ce329
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924398608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1924398608
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3810750106
Short name T634
Test name
Test status
Simulation time 89008376632 ps
CPU time 371.36 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 06:56:08 PM PDT 24
Peak memory 201632 kb
Host smart-9f2a28be-c4b8-4acf-899a-ed80bbf2d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810750106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3810750106
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2848556236
Short name T716
Test name
Test status
Simulation time 41880830521 ps
CPU time 50.23 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:50:50 PM PDT 24
Peak memory 200852 kb
Host smart-d5e8c037-b8e1-4882-91db-3006bebdbec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848556236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2848556236
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1770120789
Short name T511
Test name
Test status
Simulation time 4184018372 ps
CPU time 10.11 seconds
Started Jul 26 06:50:01 PM PDT 24
Finished Jul 26 06:50:12 PM PDT 24
Peak memory 200848 kb
Host smart-a2d188c6-0d43-465a-b153-1c7e7444aaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770120789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1770120789
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2367371166
Short name T452
Test name
Test status
Simulation time 5933627500 ps
CPU time 3.73 seconds
Started Jul 26 06:49:55 PM PDT 24
Finished Jul 26 06:49:59 PM PDT 24
Peak memory 201036 kb
Host smart-22be3c36-9f26-45ac-8d74-9a49dffc06f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367371166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2367371166
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2382172759
Short name T241
Test name
Test status
Simulation time 571146226206 ps
CPU time 314.18 seconds
Started Jul 26 06:49:55 PM PDT 24
Finished Jul 26 06:55:09 PM PDT 24
Peak memory 201160 kb
Host smart-77cd4ccf-c666-4040-b84b-1b979092b81e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382172759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2382172759
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3296670197
Short name T99
Test name
Test status
Simulation time 149258420355 ps
CPU time 235.56 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:53:53 PM PDT 24
Peak memory 209908 kb
Host smart-e25f3ec5-931c-4b6a-8722-22d3002681b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296670197 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3296670197
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.906944393
Short name T405
Test name
Test status
Simulation time 337222275 ps
CPU time 1.37 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:50:00 PM PDT 24
Peak memory 200964 kb
Host smart-0cb69a89-85b9-4bbf-960b-7a1df6152f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906944393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.906944393
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4116278031
Short name T721
Test name
Test status
Simulation time 357988228918 ps
CPU time 787.25 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 07:03:04 PM PDT 24
Peak memory 201188 kb
Host smart-8cdcaf99-0416-4359-8c19-77deb85c9aad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116278031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4116278031
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1525611287
Short name T221
Test name
Test status
Simulation time 163643784787 ps
CPU time 180.96 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:52:59 PM PDT 24
Peak memory 201244 kb
Host smart-609ee238-df05-44b1-bd96-b01625f86872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525611287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1525611287
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1187222505
Short name T373
Test name
Test status
Simulation time 333707669996 ps
CPU time 210.38 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 06:53:27 PM PDT 24
Peak memory 201232 kb
Host smart-bed962ad-6590-4b29-9aec-c11c7e3765aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187222505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1187222505
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1314321891
Short name T136
Test name
Test status
Simulation time 327065362257 ps
CPU time 54.74 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:50:52 PM PDT 24
Peak memory 201188 kb
Host smart-e37f7a24-0aa0-4572-b850-09eb47239a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314321891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1314321891
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.305121989
Short name T690
Test name
Test status
Simulation time 325799027579 ps
CPU time 731.09 seconds
Started Jul 26 06:49:59 PM PDT 24
Finished Jul 26 07:02:11 PM PDT 24
Peak memory 201028 kb
Host smart-54ff7a5b-f73c-475f-95c9-0a027fff448a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=305121989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.305121989
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.756650640
Short name T550
Test name
Test status
Simulation time 598749367773 ps
CPU time 370.43 seconds
Started Jul 26 06:49:55 PM PDT 24
Finished Jul 26 06:56:06 PM PDT 24
Peak memory 201152 kb
Host smart-11809de0-c9cb-4f5d-aff0-1ea59aebf34a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756650640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.756650640
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1571412541
Short name T732
Test name
Test status
Simulation time 57781810734 ps
CPU time 288.99 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:54:47 PM PDT 24
Peak memory 201584 kb
Host smart-f9560c19-2a17-4b47-a5ea-37f513a0e7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571412541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1571412541
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4239695332
Short name T506
Test name
Test status
Simulation time 25638177811 ps
CPU time 14.9 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:50:13 PM PDT 24
Peak memory 201012 kb
Host smart-3c4e965e-422a-43c5-b9db-2823e6ab095a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239695332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4239695332
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1329099102
Short name T684
Test name
Test status
Simulation time 3339437089 ps
CPU time 2.56 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:50:00 PM PDT 24
Peak memory 200808 kb
Host smart-9ae910ba-0a59-4fb3-b707-6aff75d30cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329099102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1329099102
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.353455899
Short name T375
Test name
Test status
Simulation time 6048401269 ps
CPU time 14.23 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 06:50:10 PM PDT 24
Peak memory 201000 kb
Host smart-56b7bc5d-5365-4178-aaf8-c586f7900f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353455899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.353455899
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1899784519
Short name T231
Test name
Test status
Simulation time 359071272072 ps
CPU time 298.56 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:54:56 PM PDT 24
Peak memory 209904 kb
Host smart-a6c7aa3f-e7b8-456a-9637-5b5bd72dd9aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899784519 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1899784519
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3394671086
Short name T632
Test name
Test status
Simulation time 469631880 ps
CPU time 1.78 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:50:02 PM PDT 24
Peak memory 200960 kb
Host smart-c5c17bf1-85e8-4796-9363-d8740e39df23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394671086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3394671086
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1492366596
Short name T486
Test name
Test status
Simulation time 165690381314 ps
CPU time 88.4 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:51:26 PM PDT 24
Peak memory 201196 kb
Host smart-b06717de-6c64-4ba6-9a25-453a1a1ec0ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492366596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1492366596
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1632924570
Short name T227
Test name
Test status
Simulation time 436278720036 ps
CPU time 1035.01 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 07:07:13 PM PDT 24
Peak memory 201136 kb
Host smart-a3cd480f-4a07-4ef8-a41b-a3d21ea3c98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632924570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1632924570
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3449207139
Short name T794
Test name
Test status
Simulation time 331913778130 ps
CPU time 75.32 seconds
Started Jul 26 06:50:25 PM PDT 24
Finished Jul 26 06:51:40 PM PDT 24
Peak memory 201172 kb
Host smart-031641b5-e799-43b1-98c9-d09742ce2b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449207139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3449207139
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.914649605
Short name T549
Test name
Test status
Simulation time 489629956249 ps
CPU time 281.69 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:54:40 PM PDT 24
Peak memory 201164 kb
Host smart-501ebbe9-9234-4687-9d9b-f4039ea881d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=914649605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.914649605
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3270253198
Short name T107
Test name
Test status
Simulation time 168451407057 ps
CPU time 372.55 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 06:56:09 PM PDT 24
Peak memory 201152 kb
Host smart-6f6db2da-8046-4f9d-84ae-ecaa2a1a82d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270253198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3270253198
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2618608227
Short name T435
Test name
Test status
Simulation time 166043567954 ps
CPU time 390.97 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:56:29 PM PDT 24
Peak memory 201132 kb
Host smart-6771a01d-7178-426f-8b30-e91d9b7753f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618608227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2618608227
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3207598256
Short name T135
Test name
Test status
Simulation time 551637403784 ps
CPU time 113.52 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:51:52 PM PDT 24
Peak memory 201248 kb
Host smart-5d6a1c7e-a561-4aba-b4a4-2e15dfa010e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207598256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3207598256
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.816894459
Short name T11
Test name
Test status
Simulation time 200032455017 ps
CPU time 429.04 seconds
Started Jul 26 06:49:59 PM PDT 24
Finished Jul 26 06:57:08 PM PDT 24
Peak memory 201224 kb
Host smart-cd1cd4e0-4df7-4e2a-8dcc-5ce342db8f12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816894459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.816894459
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.4140414269
Short name T629
Test name
Test status
Simulation time 81280653378 ps
CPU time 271.59 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:54:30 PM PDT 24
Peak memory 201624 kb
Host smart-0b4ba4fc-9cc4-4d37-a7c3-fbec7b84caa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140414269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.4140414269
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.927119812
Short name T545
Test name
Test status
Simulation time 27343819417 ps
CPU time 9.56 seconds
Started Jul 26 06:49:57 PM PDT 24
Finished Jul 26 06:50:07 PM PDT 24
Peak memory 200964 kb
Host smart-42ce012b-3424-49ad-aeb2-c86f537d1368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927119812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.927119812
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2945439928
Short name T349
Test name
Test status
Simulation time 2658242143 ps
CPU time 1.61 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 06:49:58 PM PDT 24
Peak memory 200988 kb
Host smart-c81f5a2e-7328-4a48-b0ca-37fc18629f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945439928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2945439928
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.4216966390
Short name T517
Test name
Test status
Simulation time 5955147308 ps
CPU time 14.1 seconds
Started Jul 26 06:49:59 PM PDT 24
Finished Jul 26 06:50:14 PM PDT 24
Peak memory 201096 kb
Host smart-dc13a989-e343-4f8c-b162-75b293f44ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216966390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.4216966390
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3842171833
Short name T146
Test name
Test status
Simulation time 266367790162 ps
CPU time 161.82 seconds
Started Jul 26 06:49:56 PM PDT 24
Finished Jul 26 06:52:38 PM PDT 24
Peak memory 201124 kb
Host smart-cd292750-768c-4bd7-8b58-7cb928681ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842171833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3842171833
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2549619383
Short name T760
Test name
Test status
Simulation time 409277137 ps
CPU time 0.83 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:49:59 PM PDT 24
Peak memory 200932 kb
Host smart-cbf6c639-f91f-46ca-a407-ed3bbb8c461b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549619383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2549619383
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1619356641
Short name T529
Test name
Test status
Simulation time 526719994777 ps
CPU time 334.18 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:55:32 PM PDT 24
Peak memory 201224 kb
Host smart-7e1b69f2-8615-4061-a88c-10a783031794
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619356641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1619356641
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.867356925
Short name T94
Test name
Test status
Simulation time 161767554763 ps
CPU time 385.33 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:56:24 PM PDT 24
Peak memory 201144 kb
Host smart-58f70636-407e-47de-b687-bbf925aa2130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867356925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.867356925
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.4041547574
Short name T654
Test name
Test status
Simulation time 160056849863 ps
CPU time 87.72 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:51:28 PM PDT 24
Peak memory 201152 kb
Host smart-0e7fb0f6-d8a1-43af-b8f0-bf6f37d6b68b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041547574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.4041547574
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1586610153
Short name T226
Test name
Test status
Simulation time 486348343039 ps
CPU time 278.54 seconds
Started Jul 26 06:49:59 PM PDT 24
Finished Jul 26 06:54:37 PM PDT 24
Peak memory 201128 kb
Host smart-9146f079-9c48-4739-acb8-e421bfdb7407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586610153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1586610153
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.653598853
Short name T524
Test name
Test status
Simulation time 325264142070 ps
CPU time 97.94 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:51:36 PM PDT 24
Peak memory 201156 kb
Host smart-3eb6133f-3de4-4d98-88ec-58b52fe1e839
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=653598853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.653598853
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1537140935
Short name T591
Test name
Test status
Simulation time 193081931547 ps
CPU time 221.68 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:53:42 PM PDT 24
Peak memory 201168 kb
Host smart-3cd79b04-1af1-4665-9392-4e705bd045c5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537140935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1537140935
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.236344588
Short name T746
Test name
Test status
Simulation time 108740673672 ps
CPU time 381.49 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:56:21 PM PDT 24
Peak memory 201680 kb
Host smart-5dc32bb1-6913-49ca-961f-25e8c8111563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236344588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.236344588
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.805945247
Short name T651
Test name
Test status
Simulation time 31744796511 ps
CPU time 35.28 seconds
Started Jul 26 06:49:58 PM PDT 24
Finished Jul 26 06:50:33 PM PDT 24
Peak memory 200972 kb
Host smart-de3a4bf8-acc5-4418-989f-3332416b005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805945247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.805945247
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.186626464
Short name T575
Test name
Test status
Simulation time 4302186214 ps
CPU time 11.67 seconds
Started Jul 26 06:50:00 PM PDT 24
Finished Jul 26 06:50:11 PM PDT 24
Peak memory 201056 kb
Host smart-54216b86-7097-40a3-a348-3cac5fab8fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186626464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.186626464
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1839703797
Short name T637
Test name
Test status
Simulation time 6169646358 ps
CPU time 3.98 seconds
Started Jul 26 06:49:59 PM PDT 24
Finished Jul 26 06:50:03 PM PDT 24
Peak memory 201044 kb
Host smart-13593099-1e40-4ca4-a335-096d710a345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839703797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1839703797
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2599776373
Short name T2
Test name
Test status
Simulation time 494427765993 ps
CPU time 1131.29 seconds
Started Jul 26 06:50:02 PM PDT 24
Finished Jul 26 07:08:54 PM PDT 24
Peak memory 201252 kb
Host smart-90232e76-6917-49d5-9844-410ba6b1ae20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599776373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2599776373
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3931888338
Short name T32
Test name
Test status
Simulation time 63135795232 ps
CPU time 119.67 seconds
Started Jul 26 06:49:59 PM PDT 24
Finished Jul 26 06:51:59 PM PDT 24
Peak memory 201352 kb
Host smart-3a453a07-2feb-4b93-8cdf-7a28f95c94cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931888338 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3931888338
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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