Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23057

1

T1

193

T2

16

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3758

1

T2

35

T8

35

T10

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20957

1

T1

193

T2

8

T3

12

auto[1]

5858

1

T2

43

T4

1

T8

64

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T206	23		-	-		-	-
values[0]	32	1			T207	12		T26	20		-	-
values[1]	696	1			T10	9		T11	1		T49	13
values[2]	782	1			T8	9		T10	22		T14	18
values[3]	664	1			T2	16		T44	1		T110	1
values[4]	881	1			T11	1		T161	4		T138	33
values[5]	2893	1			T4	1		T9	19		T136	1
values[6]	902	1			T2	27		T44	6		T46	11
values[7]	732	1			T11	1		T12	8		T134	1
values[8]	598	1			T2	8		T14	7		T155	1
values[9]	1394	1			T7	21		T8	55		T13	38
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	963	1			T10	9		T11	1		T14	8
values[1]	685	1			T8	9		T10	22		T14	10
values[2]	869	1			T2	16		T110	1		T49	11
values[3]	2830	1			T4	1		T9	19		T136	1
values[4]	874	1			T11	1		T44	6		T45	7
values[5]	825	1			T2	27		T11	1		T46	25
values[6]	650	1			T12	8		T134	1		T50	1
values[7]	571	1			T2	8		T7	21		T14	7
values[8]	1157	1			T8	55		T13	38		T44	25
values[9]	171	1			T44	37		T208	18		T209	2
minimum	17220	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T14	1		T57	6		T137	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	1		T11	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	7		T10	13		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T47	20		T147	2		T193	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	9		T144	8		T163	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T110	1		T49	5		T35	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1499	1			T4	1		T9	2		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T44	1		T161	4		T18	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T11	1		T44	1		T45	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T47	16		T135	5		T210	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	1		T46	11		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	12		T46	14		T28	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T171	1		T175	1		T190	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	6		T134	1		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T7	10		T194	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	8		T14	1		T45	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T8	11		T13	20		T161	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T8	21		T44	14		T190	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T44	25		T208	15		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T208	3		T195	1		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17099	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T212	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	7		T57	14		T137	25
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T10	8		T49	12		T27	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	2		T10	9		T14	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T47	13		T213	7		T214	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T2	7		T144	11		T215	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T49	6		T35	11		T39	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T9	17		T138	15		T216	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T18	2		T61	4		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T44	5		T49	13		T194	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T47	12		T217	9		T177	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T140	9		T218	14		T219	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	15		T35	12		T220	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T190	14		T202	11		T221	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	2		T57	12		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	11		T194	1		T191	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	6		T33	12		T37	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T8	9		T13	18		T33	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	14		T44	11		T190	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T44	12		T209	1		T222	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T93	16		T223	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T206	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T207	7		T26	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T57	9		T137	7		T141	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	1		T11	1		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	7		T10	13		T14	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T47	21		T49	5		T147	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	9		T133	12		T144	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T44	1		T110	1		T35	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	1		T138	18		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T161	4		T184	11		T225	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1606	1			T4	1		T9	2		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T47	16		T135	5		T217	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T44	1		T46	11		T49	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	12		T210	14		T141	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	1		T157	1		T158	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	6		T134	1		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T155	1		T175	1		T141	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	8		T14	1		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	446	1			T7	10		T8	11		T13	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T8	21		T44	14		T45	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T206	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T207	5		T26	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T57	2		T137	14		T226	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	8		T49	12		T27	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	2		T10	9		T14	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T47	13		T49	6		T227	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T2	7		T144	11		T228	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T35	11		T39	11		T40	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T138	15		T227	14		T226	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T225	13		T198	2		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T9	17		T17	23		T35	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T47	12		T217	9		T177	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T44	5		T49	13		T194	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	15		T220	12		T221	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T190	14		T219	12		T221	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	2		T57	12		T33	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T191	5		T229	6		T202	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	6		T230	13		T231	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T7	11		T8	9		T13	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T8	14		T44	11		T37	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T14	8		T57	15		T137	27
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T10	9		T11	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	3		T10	10		T14	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	14		T147	2		T193	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	8		T144	12		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T110	1		T49	7		T35	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T4	1		T9	19		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T44	1		T161	1		T18	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T11	1		T44	6		T45	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T47	13		T135	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	1		T46	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	16		T46	1		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T171	1		T175	1		T190	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	3		T134	1		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	12		T194	2		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	1		T14	7		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T8	10		T13	20		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T8	15		T44	12		T190	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T44	13		T208	1		T209	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T208	1		T195	1		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17219	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T212	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T57	5		T137	6		T138	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T27	2		T162	6		T227	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	6		T10	12		T135	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T47	19		T232	15		T233	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	8		T144	7		T163	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T49	4		T35	11		T39	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T159	20		T138	17		T234	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T161	3		T18	3		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T45	6		T49	13		T194	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T47	15		T135	4		T210	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T46	10		T158	7		T197	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	11		T46	13		T28	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T190	12		T202	7		T221	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	5		T57	9		T152	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T7	9		T141	2		T148	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	7		T45	16		T33	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T8	10		T13	18		T161	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	20		T44	13		T190	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T44	24		T208	14		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T208	2		T93	7		T223	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T206	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T207	6		T26	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T57	3		T137	15		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T10	9		T11	1		T49	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	3		T10	10		T14	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T47	15		T49	7		T147	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T2	8		T133	1		T144	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T44	1		T110	1		T35	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T11	1		T138	16		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T161	1		T184	1		T225	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T4	1		T9	19		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T47	13		T135	1		T217	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T44	6		T46	1		T49	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	16		T210	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	1		T157	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	3		T134	1		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T155	1		T175	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	1		T14	7		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	412	1			T7	12		T8	10		T13	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T8	15		T44	12		T45	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T206	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T207	6		T26	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T57	8		T137	6		T141	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T27	2		T162	6		T165	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	6		T10	12		T135	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T47	19		T49	4		T227	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T2	8		T133	11		T144	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T35	11		T39	8		T40	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T138	17		T227	3		T215	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T161	3		T184	10		T225	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T45	6		T17	18		T28	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T47	15		T135	4		T217	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T46	10		T49	13		T194	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	11		T210	13		T141	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T158	7		T190	12		T197	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	5		T46	13		T57	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T141	2		T202	7		T86	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	7		T165	18		T235	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T7	9		T8	10		T13	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T8	20		T44	13		T45	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22937

1

T1

193

T3

12

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3878

1

T2

51

T8

29

T10

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20624

1

T1

193

T2

16

T3

12

auto[1]

6191

1

T2

35

T4

1

T8

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T194	2		-	-		-	-
values[0]	3	1			T236	3		-	-		-	-
values[1]	550	1			T8	35		T11	1		T12	8
values[2]	947	1			T8	9		T11	1		T13	27
values[3]	775	1			T137	12		T163	10		T139	11
values[4]	627	1			T2	27		T11	1		T44	1
values[5]	882	1			T14	7		T45	17		T161	4
values[6]	837	1			T2	16		T10	22		T44	25
values[7]	893	1			T2	8		T44	37		T57	22
values[8]	2907	1			T4	1		T8	20		T9	19
values[9]	1174	1			T7	21		T134	1		T47	1
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	767	1			T8	44		T11	2		T12	8
values[1]	921	1			T14	8		T50	1		T45	7
values[2]	663	1			T193	1		T138	33		T217	13
values[3]	821	1			T2	27		T11	1		T44	1
values[4]	656	1			T14	7		T45	17		T161	4
values[5]	1032	1			T2	24		T10	22		T44	37
values[6]	3033	1			T4	1		T9	19		T136	1
values[7]	584	1			T10	9		T13	11		T134	1
values[8]	906	1			T7	21		T8	20		T47	1
values[9]	190	1			T49	27		T146	1		T218	21
minimum	17242	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	21		T11	1		T12	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	7		T11	1		T13	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T161	10		T137	1		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T14	1		T50	1		T45	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T138	18		T217	11		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T193	1		T165	19		T220	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	1		T35	7		T217	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	12		T44	1		T46	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T133	12		T33	16		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	1		T45	17		T161	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T44	25		T135	5		T194	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T2	17		T10	13		T158	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T4	1		T9	2		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T47	16		T57	10		T138	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	1		T134	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T13	6		T191	1		T41	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T7	10		T47	1		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	11		T49	5		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T49	14		T146	1		T218	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T237	12		T238	1		T93	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T236	2		T239	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	14		T12	2		T14	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	2		T13	13		T137	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T137	11		T27	4		T40	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T14	7		T144	11		T240	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T138	15		T217	2		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T220	12		T241	2		T213	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	2		T217	9		T225	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	15		T47	13		T57	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T33	12		T37	8		T81	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	6		T33	15		T140	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T44	12		T194	17		T35	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	7		T10	9		T217	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T9	17		T44	11		T216	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T47	12		T57	12		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	8		T44	5		T219	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T13	5		T41	1		T213	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	11		T194	1		T35	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	9		T49	6		T145	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T49	13		T218	10		T242	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T238	5		T93	13		T169	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T239	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T194	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T236	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T236	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	21		T12	6		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	1		T110	1		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	1		T49	1		T161	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T8	7		T13	14		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T137	1		T40	8		T197	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T163	10		T139	11		T165	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	1		T138	18		T217	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	12		T44	1		T46	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T133	12		T33	16		T35	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T14	1		T45	17		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T44	14		T135	5		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	9		T10	13		T158	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T44	25		T194	16		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T2	8		T57	10		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T4	1		T9	2		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	11		T13	6		T47	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	391	1			T7	10		T134	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T49	5		T193	1		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T194	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T8	14		T12	2		T14	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T144	11		T189	6		T61	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T49	12		T27	4		T217	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	2		T13	13		T14	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T137	11		T40	3		T227	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T220	12		T243	14		T240	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T138	15		T217	9		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	15		T47	13		T57	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T33	12		T35	2		T81	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	6		T57	2		T33	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T44	11		T37	8		T190	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	7		T10	9		T217	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T44	12		T194	17		T35	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T57	12		T18	3		T231	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T9	17		T10	8		T44	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	9		T13	5		T47	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T7	11		T49	13		T35	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T49	6		T145	9		T148	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4