Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26815

1

T1

193

T2

51

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20674

1

T1

193

T3

12

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

6141

1

T2

51

T4

1

T7

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20527

1

T1

193

T2

27

T3

12

auto[1]

6288

1

T2

24

T4

1

T7

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22520

1

T1

193

T2

29

T3

12

auto[1]

4295

1

T2

22

T7

11

T8

25

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	273	1			T17	44		T197	12		T224	1
values[0]	2	1			T225	1		T301	1		-	-
values[1]	963	1			T2	27		T8	9		T138	33
values[2]	709	1			T7	21		T10	9		T11	1
values[3]	765	1			T2	16		T147	1		T193	1
values[4]	707	1			T12	8		T13	27		T44	37
values[5]	708	1			T14	8		T45	7		T47	28
values[6]	620	1			T2	8		T11	1		T45	17
values[7]	707	1			T46	14		T135	18		T137	12
values[8]	760	1			T8	20		T10	22		T50	1
values[9]	3383	1			T4	1		T8	35		T9	19
minimum	17218	1			T1	193		T3	12		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	857	1			T2	27		T8	9		T11	1
values[1]	2845	1			T4	1		T7	21		T9	19
values[2]	725	1			T2	16		T110	1		T147	1
values[3]	734	1			T12	8		T13	27		T44	37
values[4]	675	1			T14	8		T45	7		T47	33
values[5]	776	1			T2	8		T11	1		T45	17
values[6]	634	1			T8	20		T50	1		T46	14
values[7]	831	1			T10	22		T11	1		T13	11
values[8]	1135	1			T8	35		T14	17		T134	1
values[9]	128	1			T224	1		T233	15		T208	14
minimum	17475	1			T1	193		T3	12		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

4348

1

T2

26

T7

9

T8

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	1		T139	11		T39	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T2	12		T8	7		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	1		T46	11		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1551	1			T4	1		T7	10		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T110	1		T193	1		T184	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	9		T147	1		T190	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	6		T44	25		T49	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	14		T47	16		T194	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T163	8		T141	3		T148	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	1		T45	7		T47	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T161	10		T135	18		T57	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	8		T11	1		T45	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	11		T147	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T50	1		T46	14		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	6		T44	15		T27	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	13		T11	1		T161	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T8	21		T49	5		T144	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T14	2		T134	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T233	15		T273	18		T102	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T224	1		T208	14		T269	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17155	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T171	1		T225	1		T208	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T39	4		T218	14		T198	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	15		T8	2		T217	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	8		T57	12		T194	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1023	1			T7	11		T9	17		T49	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T148	10		T220	12		T213	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	7		T190	14		T247	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	2		T44	12		T49	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	13		T47	12		T194	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T148	10		T295	2		T61	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	7		T47	13		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T57	16		T137	14		T35	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T137	11		T35	12		T227	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	9		T229	6		T198	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T35	11		T140	9		T229	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	5		T44	16		T27	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	9		T33	27		T246	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	14		T49	6		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T14	15		T17	23		T138	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T300	10		T307	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T269	15		T308	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	1		T48	2		T17	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T177	7		T215	6		T264	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T256	1		T209	1		T195	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T17	21		T197	12		T224	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T301	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T225	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T138	18		T139	11		T141	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T2	12		T8	7		T171	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	1		T11	1		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	10		T49	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T193	1		T184	11		T164	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	9		T147	1		T190	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	6		T44	25		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	14		T133	12		T194	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T163	8		T141	3		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	1		T45	7		T47	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T161	10		T57	15		T137	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	8		T11	1		T45	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T135	18		T175	1		T39	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T46	14		T137	1		T163	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	11		T44	1		T27	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	13		T50	1		T161	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T8	21		T13	6		T44	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1596	1			T4	1		T9	2		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T256	3		T209	1		T252	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T17	23		T196	11		T93	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T138	15		T218	14		T198	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T2	15		T8	2		T217	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	8		T57	12		T194	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	11		T49	12		T217	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T220	12		T213	13		T177	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	7		T190	14		T247	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	2		T44	12		T49	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	13		T194	17		T241	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T148	10		T295	2		T61	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	7		T47	12		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T57	16		T137	14		T35	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T47	13		T35	12		T227	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	11		T229	6		T198	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T137	11		T140	9		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	9		T44	5		T27	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	9		T33	15		T35	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T8	14		T13	5		T44	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1120	1			T9	17		T14	15		T33	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T48	2		T17	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	1		T139	1		T39	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T2	16		T8	3		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	9		T46	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1366	1			T4	1		T7	12		T9	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T110	1		T193	1		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	8		T147	1		T190	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	3		T44	13		T49	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	14		T47	13		T194	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T163	1		T141	1		T148	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	8		T45	1		T47	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T161	1		T135	1		T57	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T11	1		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	10		T147	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T50	1		T46	1		T35	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	6		T44	18		T27	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T10	10		T11	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T8	15		T49	7		T144	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T14	17		T134	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T233	1		T273	1		T102	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T224	1		T208	1		T269	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17279	1			T1	193		T3	12		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T171	1		T225	1		T208	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T139	10		T141	14		T218	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	11		T8	6		T202	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T46	10		T57	9		T165	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1208	1			T7	9		T159	20		T234	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T184	10		T165	18		T220	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	8		T190	12		T208	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	5		T44	24		T49	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	13		T47	15		T194	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T163	7		T141	2		T148	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T45	6		T47	19		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T161	9		T135	17		T57	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	7		T45	16		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	10		T264	13		T297	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T46	13		T35	11		T163	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	5		T44	13		T27	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	12		T161	3		T135	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	20		T49	4		T144	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T17	18		T138	12		T217	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T233	14		T273	17		T307	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T208	13		T269	15		T308	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T138	17		T213	10		T309	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T208	2		T177	8		T215	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T256	4		T209	2		T195	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T17	26		T197	1		T224	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T301	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T225	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T138	16		T139	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T2	16		T8	3		T171	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	9		T11	1		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	12		T49	13		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T193	1		T184	1		T164	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	8		T147	1		T190	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	3		T44	13		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	14		T133	1		T194	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T163	1		T141	1		T148	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	8		T45	1		T47	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T161	1		T57	18		T137	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T11	1		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T135	1		T175	1		T39	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T46	1		T137	12		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	10		T44	6		T27	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T10	10		T50	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	385	1			T8	15		T13	6		T44	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1490	1			T4	1		T9	19		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17218	1			T1	193		T3	12		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T252	13		T307	12		T310	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T17	18		T197	11		T237	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T138	17		T139	10		T141	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	11		T8	6		T202	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T46	10		T57	9		T165	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	9		T217	10		T165	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T184	10		T165	18		T220	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	8		T190	12		T208	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	5		T44	24		T49	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	13		T133	11		T194	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T163	7		T141	2		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T45	6		T47	15		T158	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T161	9		T57	13		T137	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	7		T45	16		T47	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T135	17		T39	8		T152	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T46	13		T163	9		T254	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	10		T27	2		T214	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	12		T161	3		T135	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T8	20		T13	5		T44	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1226	1			T33	15		T159	20		T138	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22467

1

T1

193

T2

25

T3

12

auto[1]

auto[0]

4348

1

T2

26

T7

9

T8

36